3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 FEATURES: • • • • • • • • • • • • • • 1,024 x 1,024 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay Automatic identification of ST-BUS®/GCI interfaces Accepts 8 Serial Data Streams of 8.192 Mb/s Automatic frame offset delay measurement Per-stream frame delay offset programming Per-channel high impedance output control Per-channel Processor Mode Control interface compatible to Intel/Motorola CPUs Connection memory block programming Available in 64-pin Thin Plastic Quad Flatpack (TQFP) and IDT72V70810 64-pin Small Thin Quad Flatpack (STQFP) 3.3V Power Supply Operating Temperature Range -40°°C to +85°°C 3.3V I/O with 5V Tolerant Inputs DESCRIPTION: The IDT72V70810 is a non-blocking digital switch that has a capacity of 1,024 x 1,024 channels at a serial bit rate of 8.192 Mb/s. Some of the main features are: programmable stream and channel control, Processor Mode, input offset delay and high-impedance output control. Per-stream input delay control is provided for managing large multi-chip switches that transport both voice channel and concatenated data channels. In addition, input streams can be individually calibrated for input frame offset. FUNCTIONAL BLOCK DIAGRAM VCC GND RESET ODE Loopback RX0 TX0 RX1 RX2 RX3 RX4 Receive Serial Data Streams TX1 Output MUX Data Memory TX2 Transmit Serial Data Streams RX5 TX3 TX4 TX5 RX6 Connection Memory Internal Registers RX7 Timing Unit CLK F0i FE/ WFPS HCLK TX6 TX7 Microprocessor Interface AS/ IM DS/ RD ALE CS R/W/ A0-A7 DTA D8-D15/ WR AD0-AD7 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp. CCO 5710 drw01 MARCH 2003 1 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5710/4 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE GND TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 ODE GND CCO DTA D15 D14 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCC 63 64 PIN CONFIGURATION PIN 1 GND 1 48 D13 RX0 2 47 D12 RX1 3 46 D11 RX2 4 45 D10 RX3 5 44 D9 RX4 6 43 D8 RX5 7 42 GND RX6 8 41 VCC RX7 9 40 AD7 F0i 10 39 AD6 FE/HCLK 11 38 AD5 GND 12 37 AD4 26 27 28 29 30 31 32 R/W/RW CS AS/ALE IM GND A6 A7 24 25 A5 DS/RD 22 23 A4 AD0 A3 33 21 16 A2 DNC 20 AD1 A1 34 19 15 A0 AD2 DNC 18 AD3 35 WFPS 36 14 17 13 RESET CLK VCC TQFP 0.80mm pitch, 14mm x 14mm (PN64-1, order code: PF) STQFP 0.50 pitch, 10mm x 10mm (PP64-1, order code: TF) TOP VIEW NOTES: 1. DNC - Do Not Connect. 2. All I/O pins are 5V tolerant. 2 5710 drw02 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION SYMBOL GND Vcc TX0-7 RX0-7 F0i NAME Ground. Vcc TX Output 0 to 7 (Three-state Outputs) RX Input 0 to 7 Frame Pulse I/O O I I FE/HCLK Frame Evaluation/ HCLK Clock CLK Clock RESET Device Reset (Schmitt Trigger Input) I WFPS I A0-7 Wide Frame Pulse Select Address 0-7 DS/RD Data Strobe/Read I R/W / WR Read/Write / Write I CS AS/ALE I I I I I IM Chip Select Address Strobe or Latch Enable CPU Interface Mode AD0-7 Address/Data Bus 0 to 7 I/O D8-15 DTA Data Bus 8-15 Data Transfer Acknowledgment I/O O CCO Control Output O ODE Output Drive Enable I I DESCRIPTION Ground Rail. +3.3 Volt Power Supply. Serial data output stream. These streams have a data rate of 8.192 Mb/s. Serial data input stream. These streams have a data rate of 8.192 Mb/s. When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS® and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame pulse which conforms to WFPS formats. When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK (4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode. Serial clock for shifting data in/out on the serial streams (RX/TX 0-7). This input accepts a 16.384 MHz clock. This input (active LOW) puts the IDT72V70810 in its reset state that clears the device internal counters, registers and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held LOW for a minimum of 100ns to reset the device. When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in ST-BUS®/GCI mode. When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal memories. For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This active LOW input works in conjunction with CS to enable the read and write operations. For Intel multiplexed bus operation, this input is RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs. In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus operation, this input is WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs. Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70810. This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed bus operation, connect this pin to ground. When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor port is in non-multiplexed mode. These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins are also the input address bits of the microprocessor port. These pins are the eight most significant data bits of the microprocessor port. This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is in high-impedance. This is a 16.384 Mb/s output containing 2.048 bits per frame respectively. The level of each bit is determined by the CCO bit in the connection memory. See External Drive Control Section. This is the output enable control for the TX0 to TX7 serial outputs. When ODE input is LOW and the OSB bit of the IMS register is LOW, TX0-7 are in a high-impedance state. If this input is HIGH, the TX0-7 output drivers are enabled. However, each channel may still be put into a high-impedance state by using the per channel control bit in the connection memory. 3 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE serial converter one time-slot before it is to be output. This data will be output on the TX streams in every frame until the data is changed by the microprocessor. As the IDT72V70810 can be used in a wide variety of applications, the device also has memory locations to control the outputs based on operating mode. Specifically, the IDT72V70810 provides five per-channel control bits for the following functions: processor or connection mode, constant or variable delay, enables/three-state the TX output drivers and enables/disable the loopback function. In addition, one of these bits allows the user to control the CCO output. If an output channel is set to a high-impedance state through the connection memory, the TX output will be in a high-impedance state for the duration of that channel. In addition to the per-channel control, all channels on the ST-BUS® outputs can be placed in a high impedance state by either pulling the ODE input pin low or programming the Output Stand-By (OSB) bit in the interface mode selection register. This action overrides the per-channel programming in the connection memory bits. The connection memory data can be accessed via the microprocessor interface. The addressing of the devices internal registers, data and connection memories is performed through the address input pins and the Memory Select (MS) bit of the control register. For details on device addressing, see Software Control and Control Register bits description (Table 3 and 5). FUNCTIONAL DESCRIPTION The IDT72V70810 is capable of switching up to 1,024 x 1,024, 64 Kbit/s PCM or N x 64 Kbit/s channel data. The device maintains frame integrity in data applications and minimum throughput delay for voice applications on a per channel basis. The serial input streams of the IDT72V70810 have a bit rate of 8.192 Mb/s and are arranged in 125ms wide frames, which contain 128 channels. The data rates on input and output streams are identical. In Processor Mode, the microprocessor can access input and output timeslots on a per channel basis allowing for transfer of control and status information. The IDT72V70810 automatically identifies the polarity of the frame synchronization input signal and configures the serial streams to either ST-BUS® or GCI formats. With the variety of different microprocessor interfaces, IDT72V70810 has provided an Input Mode pin (IM) to help integrate the device into different microprocessor based environments: Non-multiplexed or Multiplexed. These interfaces provide compatibility with multiplexed and Motorola non-multiplexed buses. The device can also resolve different control signals eliminating the use of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE). The frame offset calibration function allows users to measure the frame offset delay using a frame evaluation pin (FE). The input offset delay can be programmed for individual streams using internal frame input offset registers, see Table 8. The internal loopback allows the TX output data to be looped around to the RX inputs for diagnostic purposes. A functional Block Diagram of the IDT72V70810 is shown in Figure 1. SERIAL DATA INTERFACE TIMING The master clock frequency must always be twice the data rate. For serial data rates of 8.192 Mb/s, the master clock (CLK) must be 16.384 MHz. The input and output stream data rates will always be identical. The IDT72V70810 provides two different interface timing modes ST-BUS®/ GCI and WFP (wide frame pulse). If the WFPS pin is high, the IDT72V70810 is in the wide frame pulse (WFP) frame alignment mode. In ST-BUS®/GCI mode, the input 8 KHz frame pulse can be in either ST-BUS® or GCI format. The IDT72V70810 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS® or GCI. In ST-BUS® format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of CLK, three quarters of the way into the bit cell, see Figure 7. In GCI format, every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell, see Figure 8. DATA AND CONNECTION MEMORY The received serial data is converted to parallel format by internal serialto-parallel converters and stored sequentially in the data memory. The 8 KHz input frame pulse (F0i) is used to generate channel and frame boundaries of the input serial data. Depending on the interface mode select (IMS) register, the usable data memory may be as large as 1,024 bytes. Data to be output on the serial streams (TX0-7) may come from either the data memory or connection memory. For data output from data memory (connection mode), addresses in the connection memory are used. For data to be output from connection memory, the connection memory control bits must set the particular TX output in Processor Mode. One time-slot before the data is to be output, data from either connection memory or data memory is read internally. This allows enough time for memory access and parallel-to-serial conversion. WIDE FRAME PULSE (WFP) FRAME ALIGNMENT TIMING When the device is in WFP frame alignment mode, the CLK input must be at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 KHz frame pulse is in ST-BUS® format. The timing relationship between CLK, HCLK and the frame pulse is shown in Figure 9. When WFPS pin is high, the frame alignment evaluation feature is disabled. However, the frame input offset registers may still be programmed to compensate for the varying frame delays on the serial input streams. CONNECTION AND PROCESSOR MODES In the Connection Mode, the addresses of the input source data for all output channels are stored in the connection memory. The connection memory is mapped in such a way that each location corresponds to an output channel on the output streams. For details on the use of the source address data (CAB and SAB bits), see Table 10. Once the source address bits are programmed by the microprocessor, the contents of the data memory at the selected address are transferred to the parallel-to-serial converters and then onto a TX output stream. By having the each location in the connection memory specify an input channel, multiple outputs can specify the same input address. This can be a powerful tool used for broadcasting data. In Processor Mode, the microprocessor writes data to the connection memory. Each location in the connection memory corresponds to a particular output stream and channel number and is transferred directly to the parallel-to- INPUT FRAME OFFSET SELECTION Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. F0i). Although all input data comes in at the same speed, delays can be caused by variable path serial backplanes and variable path lengths which may be implemented in large centralized and distributed switching systems. Because data is often delayed, this feature is useful in compensating for the skew between clocks. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR). The maximum allowable skew is +4.5 master 4 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE clock (CLK) periods forward with resolution of ½ clock period. The output frame offset cannot be offset or adjusted. See Figure 5, Table 8 and 9 for delay offset programming. minimum delay achievable in the IDT72V70810 is three time-slots. If the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame (channel n, frame p+1). The same is true if input channel n is switched to output channel n+1 or n+2. If the input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same frame. Table 1 shows the possible delays for the IDT72V70810 in the variable delay mode. SERIAL INPUT FRAME ALIGNMENT EVALUATION The IDT72V70810 provides the frame evaluation (FE) input to determine different data input delays with respect to the frame pulse F0i. A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. When the SFE bit in the IMS register is changed from low to high, the evaluation starts. Two frames later, the complete frame evaluation (CFE) bit of the frame alignment register (FAR) changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 11 of the FAR register. The SFE bit must be set to zero before a new measurement cycle started. In ST-BUS® mode, the falling edge of the frame measurement signal (FE) is evaluated against the falling edge of the ST-BUS® frame pulse. In GCI mode, the rising edge of FE is evaluated against the rising edge of the GCI frame pulse. See Table 7 & Figure 4 for the description of the frame alignment register. This feature is not available when the WFP Frame Alignment mode is enabled (i.e., when the WFPS pin is connected to VCC). CONSTANT DELAY MODE (V/C BIT = 1) In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. Input channel data is written into the data memory buffers during frame n will be read out during frame n+2. In the IDT72V70810, the minimum throughput delay achievable in the constant delay mode will be one frame. See Table 2 for possible delays in constant delay mode. MICROPROCESSOR INTERFACE The IDT72V70810 provides a parallel microprocessor interface for multiplexed or non-multiplexed bus structures. This interface is compatible with Motorola non-multiplexed and multiplexed buses. If the IM pin is low a Motorola non-multiplexed bus should be connected to the device. If the IM pin is high, the device monitors the AS/ALE and DS/RD to determine what mode the IDT72V70810 should operate in. If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed timing is selected. If DS/RD is high at the rising edge of AS/ALE, then the mode 2 multiplexed bus timing is selected. For multiplexed operation, the required signals are the 8-bit data and address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch enable (AS/ ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR), Chip select (CS) and Data transfer acknowledge (DTA). See Figure 12 and Figure 13 for multiplexed parallel microport timing. For the Motorola non-multiplexed bus, the required signals are the 16-bit data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines (CS, DS, R/W and DTA). See Figure 14 and 15 for Motorola non-multiplexed microport timing. The IDT72V70810 microport provides access to the internal registers, connection and data memories. All locations provide read/write access except for the data memory and the frame alignment register which are read only. MEMORY BLOCK PROGRAMMING The IDT72V70810 provides users with the capability of initializing the entire connection memory block in two frames. To set bits 11 to 15 of every connection memory location, first program the desired pattern in bits 5 to 9 of the IMS register. The block programming mode is enabled by setting the memory block program (MBP) bit of the control register high. When the block programming enable (BPE) bit of the IMS register is set to high, the block programming data will be loaded into the bits 11 to 15 of every connection memory location. The other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero. LOOPBACK CONTROL The loopback control (LPBK) bit of each connection memory location allows the TX output data to be looped backed internally to the RX input for diagnostic purposes. If the LPBK bit is high, the associated TX output channel data is internally looped back to the RX input channel (i.e., data from TX n channel m routes to the RX n channel m internally); if the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of frame delay offset registers must be set to zero. MEMORY MAPPING The address bus on the microprocessor interface selects the internal registers and memories of the IDT72V70810. If the A7 address input is low, then A6 through A0 are used to address the interface mode selection (IMS), control (CR), frame alignment (FAR) and frame input offset (FOR) registers (Table 4). If the A7 is high, then A6 through A0 are used to select 128 locations corresponding to data rate of the ST-BUS®. The address input lines and the stream address bits (STA) of the control register allow access to the entire data and connection memories. The control and IMS registers together control all the major functions of the device, see Figure 3. As explained in the Serial Data Interface Timing and Switching Configurations sections, after system power-up, the IMS register should be programmed immediately to establish the desired switching configuration. The data in the control register consists of the memory block programming bit (MBP), the memory select bit (MS) and the stream address bits (STA). As explained in the Memory Block Programming section, the MBP bit allows the entire connection memory block to be programmed. The memory select bit is DELAY THROUGH THE IDT72V70810 The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on the per-channel basis. For voice applications, variable throughput delay is best as it ensures minimum delay between input and output data. In wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. The delay through the device varies according to the type of throughput delay selected in the V/C bit of the connection memory. VARIABLE DELAY MODE (V/C BIT = 0) In this mode, the delay is dependent only on the combination of source and destination channels and is independent of input and output streams. The 5 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE The processor channel (PC) bit of the connection memory selects between Processor Mode and Connection Mode. If high, the contents of the connection memory are output on the TX streams. If low, the stream address bit (SAB) and the channel address bit (CAB) of the connection memory defines the source information (stream and channel) of the time-slot that will be switched to the output from data memory. The V/C (Variable/Constant Delay) bit in each connection memory location allows the per-channel selection between variable and constant throughput delay modes. If the LPBK bit is high, the associated TX output channel data is internally looped back to the RX input channel (i.e., RX n channel m data comes from the TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of the frame delay offset registers must be set to zero. used to designate the connection memory or the data Memory. The stream address bits select internal memory subsections corresponding to input or output serial streams. The data in the IMS register consists of block programming bits (BPD0BPD4), block programming enable bit (BPE), output stand by bit (OSB) and start frame evaluation bit (SFE). The block programming and the block programming enable bits allows users to program the entire connection memory (see Memory Block Programming section). If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-BUS® output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and all TX output drivers are enabled. CONNECTION MEMORY CONTROL The CCO pin is a 16.384 Mb/s output, which carries 2,048 bits. The contents of the CCO bit of each connection memory location are output on the CCO pin once every frame. The contents of the CCO bits of the connection memory are transmitted sequentially on to the CCO pin (2 bit cells for each bit in connection memory) and are synchronous with the data rates on the other serial streams. The CCO bit is output one channel before the corresponding channel on the serial streams. If the ODE pin or the OSB bit is high, the OE bit of each connection memory location controls the output drivers-enables (if high) or disables (if low). See Table 4 for detail. INITIALIZATION OF THE IDT72V70810 After power up, the state of the connection memory is unknown. As such, the outputs should be put in high impedance by holding the ODE low. While the ODE is low, the microprocessor can initialize the device, program the active paths, and disable unused outputs by programming the OE bit in connection memory. Once the device is configured, the ODE pin (or OSB bit depending on initialization) can be switched. 6 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 Control Register CRb7 COMMERCIAL TEMPERATURE RANGE CRb6 CRb5 CRb4 CRb3 CRb2 CRb1 CRb0 CRb4 0 1 The Control Register is only accessed when A7-A0 are all zeroed. When A7 =1, up to 128 bytes are randomly accessable via A0-A6 at any one instant. Of which stream these bytes (channels) are accessed is determined by the state of CRb2 -CRb0. Connection Memory Data Memory Channel 0 Channel 1 Channel 2 Channel 127 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 127 Channel 127 Channel 127 Channel 127 Channel 127 Channel 127 Channel 127 10000000 10000001 10000010 11111111 CRb2 0 0 0 0 1 1 1 1 CRb1 0 0 1 1 0 0 1 1 CRb0 Stream 0 0 1 1 2 0 1 0 1 3 4 5 0 1 6 7 External Address Bits A7-A0 5710 drw03 Figure 3. Addressing Internal Memories 7 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE TABLE 1 — VARIABLE THROUGHPUT DELAY VALUE TABLE 2 — CONSTANT THROUGHPUT DELAY VALUE Delay for Variable Throughput Delay Mode Input Rate (m – output channel number) (n – input channel number) m<n m = n, n+1, n+2 m > n+2 8.192 Mb/s 128 – (n-m) time-slots m-n + 128 time-slots m-n time-slots Input Rate 8.192 Mb/s Delay for Constant Throughput Delay Mode (m – output channel number) (n – input channel number) 128 + (128 – n) + m time-slots TABLE 3 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING A7(1) A6 A5 A4 A3 A2 A1 A0 Location 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 0 0 0 0 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 0 0 0 1 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 0 1 1 0 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 1 0 1 0 0 1 . 0 1 0 1 . 0 1 0 1 . 0 1 Control Register, CR Interface Mode Selection Register, IMS Frame Alignment Register, FAR Frame Input Offset Register 0, FOR0 Frame Input Offset Register 1, FOR1 Ch0 Ch1 . Ch30 Ch31 Ch32 Ch33 . Ch62 Ch63 Ch64 Ch65 . Ch126 Ch127 NOTE: 1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers. TABLE 4 — OUTPUT HIGH IMPEDANCE CONTROL OE bit in Connection Memory 0 ODE pin Don’t Care OSB bit in IMS Register Don’t Care 1 1 1 1 0 0 1 1 0 1 1 0 8 TX Output Driver Status Per Channel High-Impedance High-Impedance Enable Enable Enable IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE TABLE 5 — CONTROL REGISTER (CR) BITS Read/Write Address: Reset Value: 00H, 0000H. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 MBP MS 0 Bit 15-6 5 4 3 2-0 2 1 0 STA2 STA1 STA0 Name Unused MBP (Memory Block Program) Description Must be zero for normal operation. When 1, the connection memory block programming feature is ready for the programming of Connection Memory high bits, bit 11 to bit 15. When 0, this feature is disabled. MS (Memory Select) When 0, connection memory is selected for read or write operations. When 1, the data memory is selected for read operations and connection memory is selected for write operations. (No microprocessor write operation is allowed for the data memory.) Unused Must be zero for normal operation. STA2-0 (Stream Address Bits) The binary value expressed by these bits refers to the input or output data stream, which corresponds to the subsection of memory made accessible for subsequent operations. (STA2 = MSB, STA0 = LSB) TABLE 6 — INTERFACE MODE SELECTION (IMS) REGISTER BITS Read/Write Address: Reset Value: 01H, 0000H. 15 14 13 12 11 10 0 0 0 0 0 0 Bit 15-10 9 8 7 6 5 BPD4 BPD3 BPD2 BPD1 BPD0 Name 4 3 2 1 0 BPE OSB SFE 1 0 Description Unused Must be zero for normal operation. 9-5 BPD4-0 (Block Programming Data) These bits carry the value to be loaded into the connection memory block whenever the memory block programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD4-0 are loaded into bit 15 and 11 of the connection memory. Bit 10 to bit 0 of the connection memory are set to 0. 4 BPE (Begin Block Programming Enable) A zero to one transition of this bit enables the memory block programming function. The BPE and BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set HIGH, the device requires two frames to complete the block programming. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort to ensure proper operation. When BPE = 1, the other bit in the IMS register must not be changed for two frames to ensure proper operation. 3 OSB (Output Stand By) When ODE = 0 and OSB = 0, the output drivers of TX0 to TX7 are in high impedance mode. When ODE= 0 and OSB = 1, the output driver of TX0 to TX7 function normally. When ODE = 1, TX0 to TX7 output drivers function normally. 2 SFE (Start Frame Evaluation) A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from zero to one, the evaluation procedure stops. To start another fame evaluation cycle, set this bit to zero for at least one frame. Unused For normal operation, bit 1 = 1 and bit 0 = 0. 1-0 9 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE TABLE 7 — FRAME ALIGNMENT REGISTER (FAR) BITS Read/Write Address: Reset Value: 02H, 0000H. 15 14 13 12 0 0 0 CFE Bit 15-13 12 11 10-0 11 10 FD11 FD10 9 8 7 6 5 4 3 2 1 0 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 Name Description Unused CFE (Complete Frame Evaluation) FD11 (Frame Delay Bit 11) FD10-0 (Frame Delay Bits) Must be zero for normal operation. When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0. The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle. The binary value expressed in these bits refers to the measured input offset value. These bits are rest to zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 – MSB, FD0 – LSB) ST-BUS Frame CLK Offset Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 13 14 15 FE Input (FD[10:0] = 06H) (FD11 = 0, sample at CLK LOW phase) GCI Frame CLK Offset Value 0 1 2 3 4 5 6 7 8 9 10 11 12 FE Input (FD[10:0] = 09H) (FD11 = 1, sample at CLK HIGH phase) 5710 drw04 Figure 4. Example for Frame Alignment Measurement 10 16 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE TABLE 8 — FRAME INPUT OFFSET REGISTER (FOR) BITS Read/Write Address: Reset Value: 03H for FOR0 register, 04H for FOR1 register, 0000H for all FOR registers. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0 15 14 13 12 11 10 9 8 5 4 3 2 1 0 OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF50 DLE5 OF42 OF41 OF40 DLE4 FOR0 Register 7 6 OF52 OF51 FOR1 Register Name(1) OFn2, OFn1, OFn0 (Offset Bits 2, 1 & 0) DLEn (Data Latch Edge) Description These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse input signal is applied to the F0i input of the device. See Figure 5. ST-BUS® mode: GCI mode: DLEn = 0, if clock rising edge is at the ¾ point of the bit cell. DLEn = 1, if when clock falling edge is at the ¾ of the bit cell. DLEn = 0, if clock falling edge is at the ¾ point of the bit cell. DLEn = 1, if when clock rising edge is at the ¾ of the bit cell. NOTE: 1. n denotes an input stream number from 0 to 7. 11 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE TABLE 9 — OFFSET BITS (OFN2, OFN1, OFN0, DLEN) & FRAME DELAY BITS (FD11, FD2-0) Measurement Result from Frame Delay Bits Input Stream Offset No clock period shift (Default) + 0.5 clock period shift + 1.0 clock period shift + 1.5 clock period shift + 2.0 clock period shift + 2.5 clock period shift + 3.0 clock period shift + 3.5 clock period shift + 4.0 clock period shift + 4.5 clock period shift FD11 1 0 1 0 1 0 1 0 1 0 FD2 0 0 0 0 0 0 0 0 1 1 FD1 0 0 0 0 1 1 1 1 0 0 Corresponding Offset Bits FD0 0 0 1 1 0 0 1 1 0 0 OFn2 0 0 0 0 0 0 0 0 1 1 OFn1 0 0 0 0 1 1 1 1 0 0 OFn0 0 0 1 1 0 0 1 1 0 0 DLEn 0 1 0 1 0 1 0 1 0 1 ST-BUS F0i CLK RX Stream Bit 7 RX Stream Bit 7 Bit 7 RX Stream Bit 7 RX Stream offset = 0, DLE = 0 offset = 1, DLE = 0 offset = 0, DLE = 1 offset = 1, DLE = 1 offset = 0, DLE = 0 offset = 1, DLE = 0 offset = 0, DLE = 1 offset = 1, DLE = 1 denotes the 3/4 point of the bit cell GCI F0i CLK RX Stream Bit 0 RX Stream RX Stream RX Stream Bit 0 Bit 0 Bit 0 denotes the 3/4 point of the bit cell Figure 5. Examples for Input Offset Delay Timing 12 5710 drw05 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE TABLE 10 — CONNECTION MEMORY BITS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LPBK V/C PC CCO OE 0 SAB2 SAB1 SAB0 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0 Bit 15 14 13 12 11 10 9,8,7(1) 6-0(1) Name LPBK (Per Channel Loopback) V/C (Variable/Constant Throughput Delay) PC (Processor Channel) CCO (Control Channel Output) OE (Output Enable) Unused SAB2-0 (Source Stream Address Bits) CAB6-0 (Source Channel Address Bits) Description When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback operations, set the delay offset register bits OFn[2:0] to zero for the streams which are in the loopback mode. This bit is used to select between the variable (LOW) and constant delay (HIGH) mode on a per-channel basis. When 1, the contents of the connection memory are output on the corresponding output channel and stream. Only the lower byte (bit 7 – bit 0) will be output to the TX output pins. When 0, the contents of the connection memory are the data memory address of the switched input channel and stream. This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first. This bit enables the TX output drivers on a per-channel basis. When 1, the output driver functions normally. When 0, the output driver is in a high-impedance state. Must be zero for normal operation. The binary value is the number of the data stream for the source of the connection. The binary value is the number of the channel for the source of the connection. NOTE: 1. If bit 13 (PC) of the corresponding connection memory location is 1 (device in processor mode), then these entire 8 bits (SAB0, CAB6 - CAB0) are output on the output channel and stream associated with this location. 13 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC Vi Parameter Min. Max. Unit Supply Voltage -0.3 5.0 V GND -0.3 5.5 V Voltage on Digital Inputs IO Current at Digital Outputs TS Storage Temperature PD -65 Package Power Dissapation 20 mA +125 °C 1 RECOMMENDED DC OPERATING CONDITIONS Symbol W NOTE: 1. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Parameter Min. Typ. Max. Units VCC Positive Supply 3.0 3.6 V VIH Input HIGH Voltage 2.0 Vcc V VIL Input LOW Voltage GND 0.8 V TOP Operating Temperature Commercial -40 +85 °C NOTE: 1. Voltages are with respect to ground unless other wise stated. DC ELECTRICAL CHARACTERISTICS Symbol Characteristics Min. ICC(1) Typ. Max. Units Supply Current 30 45 mA IIL Input Leakage (input pins) 15 µA IBL Input Leakage (I/O pins) 50 µA CI Input Pin Capacitance 10 pF IOZ High-impedance Leakage 5 µA VOH Output HIGH Voltage 2.4 V VOL Output LOW Voltage 0.4 V CO Output Pin Capacitance 10 pF NOTE: 1. Outputs Unloaded. Test Point S1 is open circuit except when testing output levels or high impedance states. S2 is switched to VCC or GND when testing output levels or high impedance states. VCC RL Output Pin S1 S2 CL GND GND 5710 drw06 Figure 6. Output Load 14 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLK Symbol Characteristics Min. tFPW Frame Pulse Width (ST-BUS , GCI) 26 80 ns tFPS Frame Pulse Setup time before CLK falling (ST-BUS® or GCI) 5 ns tFPH Frame Pulse Hold Time from CLK falling (ST-BUS® or GCI) 10 ns tCP CLK Period Bit rate = 8.192 Mb/s 55 70 ns tCH CLK Pulse Width HIGH Bit rate = 8.192 Mb/s 20 40 ns tCL CLK Pulse Width LOW Bit rate = 8.192 Mb/s 20 40 ns tr, tf Clock Rise/Fall Time 10 ns tHFPW Wide Frame Pulse Width 195 295 ns tHFPS Frame Pulse Setup Time before HCLK falling 5 150 ns tHFPH Frame Pulse Hold Time from HCLK falling 10 150 ns tHCP HCLK (4.096 MHz) Period Bit rate = 8.192 Mb/s 190 300 ns tHCH HCLK (4.096 MHz) Pulse Width HIGH Bit rate = 8.192 Mb/s 85 150 ns tHCL HCLK (4.096 MHz) Pulse Width LOW Bit rate = 8.192 Mb/s 85 150 ns tHr, tHf HCLK Rise/Fall Time 10 ns tDIF Delay between falling edge of HCLK and falling edge of CLK -10 10 ns ® Bit rate = 8.192 Mb/s Bit rate = 8.192 Mb/s Typ. Max. Units AC ELECTRICAL CHARACTERISTICS - SERIAL STREAMS (1) Symbol Characteristics Min. Typ. Max. Unit tSIS tSIH RX Setup Time 0 ns RX Hold Time 10 ns tSOD TX Delay – Active to Active 30 40 ns ns CL = 30pF CL = 200pF tDZ TX Delay – Active to High-Z 32 ns RL = 1KΩ, CL = 200pF tZD TX Delay – High-Z to Active 32 ns RL = 1KΩ, CL = 200pF tODE Output Driver Enable (ODE) Delay 32 ns RL = 1KΩ, CL = 200pF tXCD CCO Output Delay 30 40 ns ns CL = 30pF CL = 200pF NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 15 Test Conditions IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE tFPW F0i tFPS tFPH tCH tCP tCL tr tf CLK tSOD TX Bit 0, Last Ch (1) Bit 7, Channel 0 tSIS RX Bit 0, Last Ch(1) Bit 6, Channel 0 Bit 5, Channel 0 tSIH Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 5710 drw07 NOTE: 1. last channel = ch 127. Figure 7. ST-BUS® Timing when WFPS pin = 0. tFPW F0i tFPS tFPH tCH tCP tCL tr tf CLK tSOD TX Bit 7, Last Ch(1) Bit 0, Channel 0 tSIS RX Bit 7, Last Ch(1) Bit 1, Channel 0 Bit 2, Channel 0 tSIH Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0 5710 drw08 NOTE: 1. last channel = ch 127. Figure 8. GCI Timing when WFPS pin = 0 16 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE tHFPW tHFPS tHFPH F0i tHCP tHCL tHCH HCLK 4.096 MHz tHr tHf tCP tDIF tCH tr tCL tf CLK 16.384 MHz tSOD TX Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0 Bit 6, Ch 0 Bit 1, Ch 127 Bit 7, Ch 0 Bit 0, Ch 127 Bit 4, Ch 0 tSIH tSIS RX Bit 5, Ch 0 Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0 5710 drw09 NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. Figure 9. WFP Bus Timing for High Speed Serial Interface (8.192 Mb/s), when WFPS pin = 1 CLK (ST-BUS or WFPS mode) CLK (GCI mode) tDZ TX VALID DATA tZD TX ODE VALID DATA tODE tODE tXCD TX CCO VALID DATA 5710 drw11 5710 drw10 Figure 11. Output Driver Enable (ODE) Figure 10. Serial Output and External Control 17 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (INTEL) Symbol Parameter Min. Typ. Max. Units tALW ALE Pulse Width 20 ns tADS Address Setup from ALE falling 3 ns tADH Address Hold from ALE falling 3 ns tALRD RD Active after ALE falling 3 ns tDDR Data Setup from DTA LOW on Read 5 ns tCSRW CS Hold after RD/WR 5 ns tRW RD Pulse Width (Fast Read) 45 ns tCSR CS Setup from RD 0 ns tDHR Data Hold after RD 10 tWW WR Pulse Width (Fast Write) 45 ns tALWR WR Delay after ALE falling 3 ns tCSW CS Setup from WR 0 ns tDSW Data Setup from WR (Fast Write) 20 ns tSWD Valid Data Delay on Write (Slow Write) tDHW Data Hold after WR Inactive tAKD Acknowledgment Delay: (1) tAKH (1) 20 122 5 Test Conditions CL = 150pF ns CL = 150pF, RL = 1K ns ns Reading/Writing Registers 43/43 ns Reading/Writing Memory 220/210 ns CL = 150pF 22 ns CL = 150pF, RL = 1K Acknowledgment Hold Time CL = 150pF NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. tALW ALE tADS tADH AD0-AD7 D8-D15 DATA ADDRESS tALRD tCSRW CS tCSR tDHR tRW RD tWW tCSW tDHW tDSW WR tALWR tSWD tAKD tDDR DTA tAKH 5710 drw12 Figure 12. Multiplexed Bus Timing (Intel Mode) 18 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (MOTOROLA) Symbol Parameter tASW ALE Pulse Width Min. Typ. Max. tADS Address Setup from AS falling 3 ns tADH Address Hold from AS falling 3 ns tDDR Data Setup from DTA LOW on Read 5 ns tCSH CS Hold after DS falling 0 ns tCSS CS Setup from DS rising 0 ns 20 Units tDHW Data Hold after Write 5 ns tDWS Data Setup from DS – Write (Fast Write) 20 ns tSWD Valid Data Delay on Write (Slow Write) tRWS R/W Setup from DS Rising tRWH R/W Hold from DS Rising 5 tDHR(1) Data Hold after Read 10 tDSH DS Delay after AS falling 10 tAKD Acknowledgment Delay: tAKH(1) Test Conditions ns 122 CL = 150pF ns 60 ns ns 20 ns CL = 150pF, RL = 1K ns Reading/Writing Registers 43/43 ns Reading/Writing Memory 220/210 ns CL = 150pF 22 ns CL = 150pF, RL = 1K Acknowledgment Hold Time CL = 150pF NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. DS tRWH tRWS R/W tASW tDSH AS tADS AD0-AD7 D8-D15 WR AD0-AD7 D8-D15 RD CS tADH tSWD ADDRESS tDHW tDWS DATA tDHR ADDRESS DATA tCSH tCSS tDDR tAKD DTA tAKH 5710 drw13 Figure 13. Multiplexed Bus Timing (Motorola Mode) 19 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS-MOTOROLA NON-MULTIPLEXED BUS MODE Symbol Parameter Min. Typ. Max. Units tCSS CS Setup from DS falling 0 ns tRWS R/W Setup from DS falling 10 ns tADS Address Setup from DS falling 2 ns tCSH CS Hold after DS rising 0 ns tRWH R/W Hold after DS Rising 2 ns tADH Address Hold after DS Rising 2 ns tDDR Data Setup from DTA LOW on Read 2 tDHR Data Hold on Read 10 tDSW Data Setup on Write (Fast Write) 5 tSWD Valid Data Delay on Write (Slow Write) tDHW Data Hold on Write tAKD Acknowledgment Delay: tAKH(1) 20 Test Conditions ns CL = 150pF ns CL = 150pF, RL = 1K ns 122 ns 5 ns Reading/Writing Registers 43/43 ns Reading/Writing Memory 220/210 ns CL = 150pF 22 ns CL = 150pF, RL = 1K Acknowledgment Hold Time CL = 150pF NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. DS tCSS tCSH tCSS tCSH CS tRWS tRWH tRWS tRWH R/W tADS A0-A7 tADH tDSW AD0-AD7/ D8-D15 tADH tADS VALID READ ADDRESS VALID WRITE ADDRESS tDHR tDHW VALID WRITE DATA VALID READ DATA tDDR tAKD tAKH tAKD tAKH DTA 5710 drw14 Figure 14. Motorola Non-Multiplexed Asyncronous Bus Timing 20 IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 COMMERCIAL TEMPERATURE RANGE CLK GCI CLK ST-BUS tDSS tDSPW tDSS DS tCSS tCSH tCSS tCSH tRWS tRWH tRWS tRWH tADS tADH tADS tADH CS R/W A0-A7 tSWD AD0-AD7/ D8-D15 VALID READ ADDRESS VALID WRITE ADDRESS tDHW tDHR VALID WRITE DATA tCKAK VALID READ DATA tDDR tAKH tCKAK tAKH DTA 5710 drw15 Figure 15. Motorola Non-Multiplexed Syncronous Bus Timing 21 ORDERING INFORMATION IDT XXXXXX XX Device Type Package X Process/ Temperature Range BLANK Commercial (-40°C to +85°C) PF TF Thin Plastic Quad Flatpack (TQFP, PN64-1) Small Thin Quad Flat Pack (STQFP, PP64-1) 72V70810 1,024 x 1,024 3.3V Time Slot Interchange Digital Switch 5710 drw16 DATA SHEET DOCUMENT HISTORY 5/02/2000 1/04/2001 1/25/2001 08/06/2001 03/24/2003 pg.1 pgs. 4, 5, 10, 11, 14, 17, 19 and 20. pgs. 14 and 20. pg. 1 pg. 1 CORPORATE HEADQUARTER 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 22 for Tech Support: 408-330-1753 email: [email protected]