3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 X 16,384 FEATURES: • • • • • • • • • • • • • • • 16K x 16K non-blocking switching at 32.768Mb/s 32 serial input and output streams Accepts single-bit single-data streams at 32.768Mb/s Per-channel Variable Delay Mode for low-latency applications Per-channel Constant Delay Mode for frame integrity applications Automatic identification of ST-BUS® and GCI bus interfaces Automatic frame offset delay measurement Per-stream single data frame delay offset programming Per-channel high-impedance output control Direct microprocessor access to all internal memories Memory block programming for quick setup IEEE-1149.1 (JTAG) Test Port 3.3V Power Supply IDT72V73260 Available in 144-pin (13mm x 13mm) Plastic Ball Grid Array (PBGA) and 144-pin (20mm x 20mm) Thin Quad Flatpack (TQFP) Operating Temperature Range -40°°C to +85°°C DESCRIPTION: The IDT72V73260 has a non-blocking switch capacity of 16,384 x 16,384 channels at 32.768Mb/s. With 32 inputs and 32 outputs, programmable per stream control, and a variety of operating modes the IDT72V73260 is designed for the TDM time slot interchange function in either voice or data applications. Some of the main features of the IDT72V73260 are LOW power 3.3 Volt operation, automatic ST-BUS® /GCI sensing, memory block programming, simple microprocessor interface , JTAG Test Access Port (TAP) and per stream programmable input offset delay, variable or constant throughput modes, output enable and processor mode. FUNCTIONAL BLOCK DIAGRAM VCC RESET GND ODE TX0 RX0 Data Memory TX1 MUX RX1 Receive Serial Data Streams Transmit Serial Data Streams Connection Memory Internal Registers TX15 TX16/OEI0 TX17/OEI1 TX31/OEI15 RX31 Microprocessor Interface Timing Unit C32i F32i FE DS CS R/W A0-A15 DTA JTAG Port D0-D15 TMS TDI TCK TDO TRST 5932 drw01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS® is a trademark of Mitel Corp. OCTOBER 2003 1 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice DSC-5932/9 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATIONS A1 BALL PAD CORNER A C32i RESET ODE RX1 RX4 RX7 TX4 TX7 TX10 TX12 TX14 TX15 F32i FE RX0 RX2 RX5 TX0 TX3 TX6 TX9 TX11 TX13 RX8 NC(1) TMS TDI RX3 RX6 TX1 TX2 TX5 TX8 RX11 RX10 RX9 TDO TCK TRST DS VCC VCC VCC VCC RX15 RX14 RX13 RX12 CS R/W A0 VCC GND GND GND GND VCC RX18 RX17 RX16 A1 A2 A3 VCC GND GND GND GND VCC RX21 RX20 RX19 A6 A5 A4 VCC GND GND GND GND VCC RX22 RX23 TX16/ OEI0 A9 A8 A7 VCC GND GND GND GND VCC TX17/ OEI1 TX18/ OEI2 TX19/ OEI3 A13 A12 A11 A10 VCC VCC VCC VCC RX27 TX20/ OEI4 TX21/ OEI5 TX22/ OEI6 NC(1) A15 A14 D8 D5 D2 D1 RX30 RX26 TX31/ OEI15 TX23/ OEI7 TX24/ OEI8 D15 DTA D11 D9 D6 D3 D0 RX29 RX25 TX30/ OEI14 TX25/ OEI9 TX26/ OEI10 D14 D13 D12 D10 D7 D4 RX31 RX28 RX24 TX29/ OEI13 TX28/ OEI12 TX27/ OEI11 1 2 3 4 5 6 7 8 9 10 11 12 B C D E F G H J K L M 5932 drw02 NOTE: 1. NC = No Connect. PBGA: 1mm pitch, 13mm x13mm (BB144-1, order code: BB) TOP VIEW 2 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 RX16 RX17 RX18 RX19 RX20 RX21 RX22 RX23 GND VCC TX16/OEI0 TX17/OEI1 TX18/OEI2 TX19/OEI3 GND VCC TX20/OEI4 TX21/OEI5 TX22/OEI6 TX23/OEI7 GND VCC TX24/OEI8 TX25/OEI9 TX26/OEI10 TX27/OEI11 GND VCC PIN CONFIGURATIONS (CONTINUED) · 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 TX28/OEI12 TX29/OEI13 TX30/OEI14 TX31/OEI15 GND VCC RX24 RX25 RX26 RX27 RX28 RX29 RX30 RX31 GND VCC D0 D1 D2 D3 GND VCC D4 D5 D6 D7 GND VCC D8 D9 D10 D11 GND VCC D12 D13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 GND VCC TX15 TX14 TX13 TX12 GND VCC TX11 TX10 TX9 TX8 GND VCC TX7 TX6 TX5 TX4 GND VCC TX3 TX2 TX1 TX0 GND VCC RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 ODE RESET GND C32i F32i FE NC(1) TMS TDI TDO TCK TRST DS CS R/W VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 NC(1) DTA VCC GND D15 D14 5932 drw03 PIN 1 NOTE: 1. NC = No Connect. TQFP: 0.50mm pitch, 20mm x 20mm (DA144-1, order code: DA) TOP VIEW 3 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION SYMBOL NAME A0-15 Address 0 to 15 I/O DESCRIPTION I These address lines access all internal memories. C32i CS Clock Chip Select I I Serial clock for shifting data in/out on the serial data stream. This input accepts a 32.768 MHz clock. This active LOW input is used by a microprocessor to activate the microprocessor port of IDT72V73260. D0-15 DS Data Bus 0-15 Data Strobe I/O These pins are the data bits of the microprocessor port. I This active LOW input works in conjunction with CS to enable the read and write operations and sets the data bus lines (D0-D15). DTA Data Transfer Acknowledgment O Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is in high-impedance. FE Frame Evaluation I This input can be used to measure delay in the data path by comparing the frame pulse, F32i, with this input. F32i Frame Pulse I GND Ground This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS® and GCI specifications. Ground Rail ODE Output Drive Enable I RESET Device Reset I This is the output enable control for the TX serial outputs. When the ODE input is LOW and the Output Stand By bit of the Control Register is LOW, all TX outputs are in a high-impedance state. If this input is HIGH, the TX output drivers are enabled. However, each channel may still be put into a high-impedance state by using the per-channel control bits in the Connection Memory. This input puts the IDT72V73260 into a reset state that clears the device internal counters, registers and brings TX0-31 and D0-D15 into a high-impedance state. The RESET pin must be held LOW for a minimum of 20ns to properly reset the device. R/W RX0-31 Read/Write Data Stream Input 0 to 31 I I This input controls the direction of the data bus lines (D0-D15) during a microprocessor access. Serial data input stream. These streams have a data rate of 32.768Mb/s. TCK TDI Test Clock Test Serial Data In I I Provides the clock to the JTAG test logic. JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up when not driven. TDO Test Serial Data Out O TMS Test Mode Select I JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when JTAG scan is not enabled. JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-up when not driven. TRST Test Reset I TX0-15 TX Output 0 to 15 (Three-State Outputs) O TX16-31/ TX Output 16 to 31/ OEI0-15 Output Enable Indication 0 to 15 (Three-State Outputs) V CC V CC O Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure that the IDT72V73260 is in the normal functional mode. Serial data output stream. These streams have a data rate of 32.768Mb/s. When all 32 output streams are selected via Control Register, these pins are the output streams TX16 to TX31 and operate at 32.768Mb/s. When output enable function is selected, these pins reflect the active or high-impedance status for the corresponding output stream Output Enable Indication0-15. +3.3 Volt Power Supply. 4 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE DESCRIPTION (CONTINUED) SERIAL DATA INTERFACE TIMING For a 32.768Mb/s serial data rate , the master clock frequency will be running at 32.768 MHz resulting in a single-bit per clock. The IDT72V73260 provides two different interface timing modes, ST-BUS® or GCI. The IDT72V73260 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS® or GCI. In ST-BUS® Mode, data is clocked out on the falling edge and is clocked in on the subsequent rising-edge. See Figure 14 for timing. In GCI Mode, data is clocked out on the rising edge and is clocked in on the subsequent falling edge. See Figure 15 for timing. The IDT72V73260 is capable of switching up to 16,384 x 16,384 channels without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the device maintains frame integrity in data applications and minimizes throughput delay for voice applications on a per-channel basis. The 32 serial input streams (RX) of the IDT72V73260 are run at 32.768Mb/s allowing 512 channels per 125µs frame. The data rates on the output streams (TX) are identical to those on the input streams (RX). With two main operating modes, Processor Mode and Connection Mode, the IDT72V73260 can easily switch data from incoming serial streams (Data Memory) or from the controlling microprocessor via Connection Memory. As control and status information is critical in data transmission, the Processor Mode is especially useful when there are multiple devices sharing the input and output streams. With data coming from multiple sources and through different paths, data entering the device is often delayed. To handle this problem, the IDT72V73260 has a Frame Evaluation feature to allow individual streams to be offset from the frame pulse in half clock-cycle intervals up to +7.5 clock cycles. The IDT72V73260 also provides a JTAG test access port, memory block programming, a simple microprocessor interface and automatic ST-BUS® /GCI sensing to shorten setup time, aid in debugging and ease use of the device without sacrificing capabilities. INPUT FRAME OFFSET SELECTION Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment. Although all input data comes in at the same speed, delays can be caused by variable path serial backplanes and variable path lengths which may be implemented in large centralized and distributed switching systems. Because data is often delayed, this feature is useful in compensating for the skew between input streams. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5 master clock (C32i) periods forward with a resolution of ½ clock period, see Table 9. The output frame cannot be adjusted. SERIAL INPUT FRAME ALIGNMENT EVALUATION The IDT72V73260 provides the Frame Evaluation input to determine different data input delays with respect to the frame pulse F32i. A measurement cycle is started by setting the Start Frame Evaluation bit of the Control Register LOW for at least one frame. When the Start Frame Evaluation bit in the Control Register is changed from LOW to HIGH, the evaluation starts. Two frames later, the Complete Frame Evaluation bit of the Frame Alignment Register changes from LOW to HIGH to signal that a valid offset measurement is ready to be read from bits 0 to 12 of the Frame Alignment Register . The Start Frame Evaluation bit must be set to zero before a new measurement cycle is started. In ST-BUS ® mode, the falling edge of the frame measurement signal (Frame Evaluation) is evaluated against the falling edge of the ST-BUS ® frame pulse. In GCI mode, the rising edge of Frame Evaluation is evaluated against the rising edge of the GCI frame pulse. See Table 7 and Figure 1 for the description of the Frame Alignment Register. FUNCTIONAL DESCRIPTION DATA AND CONNECTION MEMORY All data that comes in through the RX inputs go through a serial-to-parallel conversion before being stored into internal Data Memory. The 8 KHz frame pulse (F32i) is used to mark the 125µs frame boundaries and to sequentially address the input channels in Data Memory. Data output on the TX streams may come from either the serial input streams (Data Memory) or from the microprocessor (Connection Memory). In the case that RX input data is to be output, the addresses in Connection Memory are used to specify a stream and channel of the input. The Connection Memory is setup in such a way that each location corresponds to an output channel for each particular stream. In that way, more than one channel can output the same data. In Processor Mode, the microprocessor writes data to the Connection Memory locations corresponding to the stream and channel that is to be output. The lower half (8 least significant bits) of the Connection Memory is output every frame until the microprocessor changes the data or mode of the channel. By using this Processor Mode capability, the microprocessor can access input and output time-slots on a per-channel basis. The two most significant bits of the Connection Memory are used to control per-channel mode of the out put streams. Specifically, the MOD1-0 bits are used to select Processor Mode, Constant or Variable delay Mode, and the highimpedance state of output drivers. If the MOD1-0 bits are set to 1-1 accordingly, only that particular output channel (8 bits) will be in the high-impedance state. If however, the ODE input pin is LOW and the Output Standby Bit in the Control Register is LOW, all of the outputs will be in a high-impedance state even if a particular channel in Connection Memory has enabled the output for that channel. In other words, the ODE pin and Output Stand By control bit are master output enables for the device (See Table 3). MEMORY BLOCK PROGRAMMING The IDT72V73260 provides users with the capability of initializing the entire Connection Memory block in two frames. To set bits 14 and 15 of every Connection Memory location, first program the desired pattern in the Block Programming Data Bits (BPD 1-0), located in bits 7 and 8 of the Control Register. The block programming mode is enabled by setting the Memory Block Program bit of the Control Register HIGH. When the Block Programming Enable bit of the Control Register is set to HIGH, the Block Programming data will be loaded into the bits 14 and 15 of every Connection Memory location. The other Connection Memory bits (bit 0 to bit 13) are loaded with zeros. When the memory block programming is complete, the device resets the Block Programming Enable, BPD 1-0 and Memory Block Program bits to zero. 5 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE DELAY THROUGH THE IDT72V73260 the Output Stand By, Start Frame Evaluation, Output Enable Indication and Software Reset . As explained in the Memory Block Programming section, the Block Programming Enable begins the programming if the Memory Block Program bit is enabled. This allows the entire Connection Memory block to be programmed with the Block Programming Data bits. If the ODE pin is LOW, the Output Stand By bit enables (if HIGH) or disables (if LOW) all TX output drivers. If the ODE pin is HIGH, the contents of the Output Stand By bit is ignored and all TX output drivers are enabled. The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, variable throughput delay is best as it ensure minimum delay between input and output data. In wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. The delay through the device varies according to the type of throughput delay selected in the MOD bits of the Connection Memory. SOFTWARE RESET The Software Reset serves the same function as the hardware reset. As with the hard reset, the Software Reset must also be set HIGH for 20ns before bringing the Software Reset LOW again for normal operation. Once the Software Reset is LOW, internal registers and other memories may be read or written. During Software Reset, the microprocessor port is still able to read from all internal memories. The only write operation allowed during a Software Reset is to the Software Reset bit in the Control Register to complete the Software Reset. VARIABLE DELAY MODE (MOD1-0 = 0-0) In this mode, the delay is dependent only on the combination of source and destination channels and is independent of input and output streams. The minimum delay achievable in the IDT72V73260 is three time-slots. If the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame (channel n, frame p+1). The same is true if the input channel n is switched to output channel n+1 or n+2. If the input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same frame. Table 2 shows the possible delays for the IDT72V73260 in Variable Delay mode. CONNECTION MEMORY CONTROL If the ODE pin and the Output Stand By bit are LOW, all output channels will be in three-state. See Table 3 for detail. If MOD1-0 of the Connection Memory is 1-0 accordingly, the output channel will be in Processor Mode. In this case the lower eight bits of the Connection Memory are output each frame until the MOD1-0 bits are changed. If MOD10 of the Connection Memory are 0-1 accordingly, the channel will be in Constant Delay Mode and bits 13-0 are used to address a location in Data Memory. If MOD1-0 of the Connection Memory are 0-0, the channel will be in Variable Delay Mode and bits 13-0 are used to address a location in Data Memory. If MOD 1-0 of the Connection Memory are 1-1, the channel will be in highImpedance mode and that channel will be in three-state. CONSTANT DELAY MODE (MOD1-0 = 0-1) In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. Input channel data is written into the data memory buffers during frame n will be read out during frame n+2. In the IDT72V73260, the minimum throughput delay achievable in Constant Delay mode will be one frame plus one channel. See Table 1. MICROPROCESSOR INTERFACE OUTPUT ENABLE INDICATION The IDT72V73260 has the capability to indicate the state of the outputs (active or three-state) by enabling the Output Enable Indication in the Control Register. In the Output Enable Indication mode however, only half of the output streams are available. If this same capability is desired with all 32 streams, this can be accomplished by using two IDT72V73260 devices. In one device, the All Output Enable bit is set to a one while in the other the All Output Enable is set to zero. In this way, one device acts as the switch and the other as a three-state control device, see Figure 5. It is important to note if the TSI device is programmed for All Output Enable and the Output Enable Indication is also set, the device will be in the All Output Enable mode not Output Enable Indication. To use all 32 streams, set Output Enable Indication in the Control Register to zero. The IDT72V73260’s microprocessor interface looks like a standard RAM interface to improve integration into a system. With a 16-bit address bus and a 16-bit data bus, reads and writes are mapped directly into Data and Connection memories. By allowing the internal memories to be randomly accessed, the controlling microprocessor has more time to manage other peripheral devices and can more easily and quickly gather information and setup the switch paths. Table 4 shows the mapping of the addresses into internal memory blocks. MEMORY MAPPING The address bus on the microprocessor interface selects the internal registers and memories of the IDT72V73260. The two most significant bits of the address select between the registers, Data Memory, and Connection Memory. If A15 and A14 are HIGH, A13-A0 are used to address the Data Memory. If A15 is HIGH and A14 is LOW, A13-A0 are used to address Connection Memory. If A15 is LOW and A14 is HIGH A13-A0 are used to select the Control Register, Frame Alignment Register, and Frame Offset Registers. See Table 4 for mappings. As explained in the Initialization sections, after system power-up, the Control Register should be programmed immediately to establish the desired switching configuration. The data in the Control Register consists of the Memory Block Programming bit , the Block Programming Data bits, the Begin Block Programming Enable, INITIALIZATION OF THE IDT72V73260 After power up, the state of the Connection Memory is unknown. As such, the outputs should be put in high-impedance by holding the ODE pin LOW. While the ODE is LOW, the microprocessor can initialize the device by using the Block Programming feature and program the active paths via the microprocessor bus. Once the device is configured, the ODE pin (or Output Stand By bit depending on initialization) can be switched to enable the TSI switch. 6 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE TABLE — 1 CONSTANT THROUGHPUT DELAY VALUE TABLE 2 — VARIABLE THROUGHPUT DELAY VALUE Delay for Constant Throughput Delay Mode (m – output channel number) (n – input channel number) Input Rate 32.768Mb/s Delay for Variable Throughput Delay Mode (m – output channel number; n – input channel number) Input Rate 512 + (512 -n) +m time-slots 32.768Mb/s m ≤ n+2 m > n+2 512 - (n-m) time-slots (m-n) time-slots TABLE 3 — OUTPUT HIGH-IMPEDANCE CONTROL Bits MOD1-0 Values in Connection Memory ODE pin OSB bit in Control Register Output Status 1 and 1 Don’t Care Don’t Care Per-channel high-Impedance Any, other than 1 and 1 0 0 high-Impedance Any, other than 1 and 1 0 1 Enable Any, other than 1 and 1 1 0 Enable Any, other than 1 and 1 1 1 Enable TABLE 4 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 R/W Location R Data Memory R/W Connection Memory R/W Control Register 1 1 STA4 STA3 STA2 STA1 STA0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 1 0 STA4 STA3 STA2 STA1 STA0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 0 1 0 0 0 0 x x x x x x x x x x 0 1 0 0 0 1 x x x x x x x x x x R Frame Align Register 0 1 1 0 0 0 x x x x x x x x x x R/W Frame Offset Register 0 0 1 1 0 0 1 x x x x x x x x x x R/W Frame Offset Register 1 0 1 1 0 1 0 x x x x x x x x x x R/W Frame Offset Register 2 0 1 1 0 1 1 x x x x x x x x x x R/W Frame Offset Register 3 0 1 1 1 0 0 x x x x x x x x x x R/W Frame Offset Register 4 0 1 1 1 0 1 x x x x x x x x x x R/W Frame Offset Register 5 0 1 1 1 1 0 x x x x x x x x x x R/W Frame Offset Register 6 0 1 1 1 1 1 x x x x x x x x x x R/W Frame Offset Register 7 7 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE TABLE 5 — CONTROL REGISTER (CR) BITS Reset Value: 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRS OEI OEPOL AOE 0 0 MBP BPD1 BPD0 BPE OSB SFE 0 0 0 0 BIT NAME 15 SRS (Software Reset) A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation. 14 OEI (Output Enable Indication) When 1, the TX16-31/Output Enable Indication0-15 pins will be Output Enable Indication 0-15 and reflect the active or high-impedance state of their corresponding output data streams. When 0, this feature is disabled and these pins are used as output data streams TX16-31. 13 OEPOL (Output Enable Polarity) When 1, a one on an Output Enable Indication pin denotes an active state on the output data stream; zero on an Output Enable Indication pin denotes high-impedance state. When 0, a one on an Output Enable Indication pin denotes high-impedance and a zero denotes an active state. 12 AOE (All Output Enable) When 1, TX0-31 will behave as Output Enable Indication0-31 accordingly. These outputs will reflect the active or high-impedance state of the corresponding output data streams (TX0-31) in another IDT72V73260 if programmed identically. When 0, the TSI operates in the normal switch mode. Unused Must be zero for normal operation. 11-10 9 DESCRIPTION MBP When 1, the Connection Memory block programming feature is ready for the programming of Connection Memory HIGH bits, (Memory Block Program) bit 14 to bit 15. When 0, this feature is disabled. 8-7 BPD1-0 (Block Programming Data) These bits carry the value to be loaded into the Connection Memory block whenever the memory block programming feature is activated. After the Memory Block Program bit in the Control Register is set to 1 and the Block Programming Enable is set to 1, the contents of the bits BPD1-0 are loaded into bit 15 and 14 of the Connection Memory. Bit 13 to bit 0 of the Connection Memory are set to 0. 6 BPE (Begin Block Programming Enable) A zero to one transition of this bit enables the memory block programming function. The Block Programming Enable and BPD1-0 bits in the Control Register have to be defined in the same write operation. Once the Block Programming Enable bit is set HIGH, the device requires two frames to complete the block programming. After the programming function has finished, the Block Programming Enable, Memory Block Program and BPD 1-0 bits will be reset to zero by the device to indicate the operation is complete. 5 OSB (Output Stand By) When ODE = 0 and Output Stand By = 0, the output drivers of the transmit serial streams are in high-impedance mode. When either ODE =1 or Output Stand By =1, the output serial streams drivers function normally. 4 SFE (Start Frame Evaluation) A zero to one transition in this bit starts the Frame Evaluation procedure. When the Complete Frame Evaluation bit in the Frame Alignment Register changes from zero to one, the evaluation procedure stops. To start another Frame Evaluation cycle, set this bit to zero for at least one frame. Unused Must be zero for normal operation. 3-0 TABLE 6 — CONNECTION MEMORY BITS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD1 MOD0 SAB4 SAB3 SAB2 SAB1 SAB0 CAB8 CAB7 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0 Bit 15, 14 13-9 8-0 Name Description MOD1-0 (Switching Mode Selection) MOD1 MOD0 0 0 0 1 1 0 1 1 MODE Variable Delay mode Constant Delay mode Processor mode Output high-impedance SAB4-0 The binary value is the number of the data stream for the source of the connection. (Source Stream Address Bits) CAB8-0 The binary value is the number of the channel for the source of the connection. (Source Channel Address Bits) 8 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE TABLE 7 — FRAME ALIGNMENT REGISTER (FAR) BITS Reset Value: 0000H. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 CFE FD12 FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 Bit 15-14 Name Description Unused Must be zero for normal operation 13 CFE (Complete Frame Evaluation) When Complete Frame Evaluation = 1, the Frame Evaluation is completed and bits FD12 to FD0 bits contains a valid frame alignment offset. This bit is reset to zero, when Start Frame Evaluation bit in the Control Register is changed from 1 to 0. 12 FD12 The falling edge of Frame Evaluation (or rising edge for GCI mode) is sampled during the C32i-HIGH phase (FD12 = 1) or during the (Frame Delay Bit 12) C32i-LOW phase (FD12 = 0). This bit allows the measurement resolution to ½ C32i cycle. This bit is reset to zero when the Start Frame Evaluation bit of the Control Register changes from 1 to 0. 11-0 FD11-0 (Frame Delay Bits) The binary value expressed in these bits refers to the measured input offset value. These bits are reset to zero when the Start Frame Evaluation bit of the Control Register changes from 1 to 0. (FD11 – MSB, FD0 – LSB) ST-BUS Frame C32i Offset Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 13 14 15 FE Input (FD[11:0] = 06H) (FD12 = 0, sample at CLK LOW phase) GCI Frame C32i Offset Value 0 1 2 3 4 5 6 7 8 9 10 11 12 FE Input (FD[11:0] = 09H) (FD12 = 1, sample at CLK HIGH phase) 5932 drw04 Figure 1. Example for Frame Alignment Measurement 9 16 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE TABLE 8 — FRAME INPUT OFFSET REGISTER (FOR) BITS Reset Value:0000H for all FOR registers. Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FOR0 Register OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0 FOR1 Register OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4 FOR2 Register OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92 OF91 OF90 DLE9 OF82 OF81 OF80 DLE8 FOR3 Register OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12 FOR4 Register OF192 OF191 OF190 DLE19 OF182 OF181 OF180 DLE18 OF172 OF171 OF170 DLE17 OD162 OD161 OF160 DLE16 FOR5 Register OF232 OF231 OF230 DLE23 OF222 OF221 OF220 DLE22 OF212 OF211 OF210 DLE21 OF202 OF201 OF200 DLE20 FOR6 Register OF272 OF271 OF270 DLE27 OF262 OF261 OF260 DLE26 OF252 OF251 OF250 DLE25 OF242 OF241 OF240 DLE24 FOR7 Register OF312 OF311 OF310 DLE31 OF302 OF301 OF300 DLE30 OF292 OF291 OF290 DLE29 OF282 OF281 OF280 DLE28 Name(1) Description OFn2, OFn1, OFn0 (Offset Bits 2, 1 & 0) These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame. The input frame offset can be selected to +7.5 clock periods from the point where the external frame pulse input signal is applied to the F32i input of the device. See Figure 2. DLEn ST-BUS® and GCI mode: DLEn = 0, offset is on the clock boundary. DLEn = 1, offset is a half clock cycle off of the clock boundary. NOTE: 1. n denotes an input stream number from 0 to 31. 10 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE TABLE 9 — OFFSET BITS (OFn2, OFn1, OFn0, DLEN) & FRAME DELAY BITS (FD12, FD2-0) Input Stream Measurement Result from Corresponding Frame Delay Bits Offset Bits Offset FD12 FD2 FD1 FD0 OFn2 OFn1 OFn0 DLEn No clock period shift (Default) 1 0 0 0 0 0 0 0 + 0.5 clock period shift 0 0 0 0 0 0 0 1 + 1.0 clock period shift 1 0 0 1 0 0 1 0 + 1.5 clock period shift 0 0 0 1 0 0 1 1 + 2.0 clock period shift 1 0 1 0 0 1 0 0 + 2.5 clock period shift 0 0 1 0 0 1 0 1 + 3.0 clock period shift 1 0 1 1 0 1 1 0 + 3.5 clock period shift 0 0 1 1 0 1 1 1 + 4.0 clock period shift 1 1 0 0 1 0 0 0 + 4.5 clock period shift 0 1 0 0 1 0 0 1 +5.0 clock period shift 1 1 0 1 1 0 1 0 +5.5 clock period shift 0 1 0 1 1 0 1 1 +6.0 clock period shift 1 1 1 0 1 1 0 0 +6.5 clock period shift 0 1 1 0 1 1 0 1 +7.0 clock period shift 1 1 1 1 1 1 1 0 +7.5 clock period shift 0 1 1 1 1 1 1 1 F32i (ST-BUS) C32i (ST-BUS) RX Stream (32.768 Mb/s) Bit 7 RX Stream (32.768 Mb/s) RX Stream (32.768 Mb/s) Bit 6 Bit 5 Bit 4 offset = 0, DLE = 0 Bit 7 Bit 6 Bit 5 offset = 1, DLE = 0 Bit 7 Bit 6 offset = 0, DLE = 1 Bit 4 Bit 5 F32i (GCI) C32i (GCI) RX Stream (32.768 Mb/s) Bit 0 RX Stream (32.768 Mb/s) RX Stream (32.768 Mb/s) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 offset = 0, DLE = 0 offset = 1, DLE = 0 Bit 2 offset = 0, DLE = 1 Bit 2 Bit 1 5932 drw05 Figure 2. Examples for Input Offset Delay Timing in 32.768Mb/s mode 11 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE JTAG SUPPORT The IDT72V73260 JTAG interface conforms to the Boundary-Scan standard IEEE-1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller. TEST ACCESS PORT (TAP) The Test Access Port (TAP) provides access to the test functions of the IDT72V73260. It consists of three input pins and one output pin. •Test Clock Input (TCK) TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. •Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VCC when it is not driven from an external source. •Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to VCC when it is not driven from an external source. •Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out through the TDO pin on the falling edge of each TCK pulse. When no data is shifted through the boundary scan cells, the TDO driver is set to a high-impedance state. •Test Reset (TRST) Reset the JTAG scan structure. This pin is internally pulled to VCC when it is not driven from an external source. INSTRUCTION REGISTER In accordance with the IEEE-1149.1 standard, the IDT72V73260 uses public instructions. The IDT72V73260 JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shift-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. See Table 12 for Instruction decoding. TEST DATA REGISTER As specified in IEEE-1149.1, the IDT72V73260 JTAG Interface contains two test data registers: •The Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the IDT72V73260 core logic. •The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO. The IDT72V73260 boundary scan register bits are shown in Table 14. Bit 0 is the first bit clocked out. All three-state enable bits are active HIGH. ID CODE REGISTER As specified in IEEE-1149.1, this instruction loads the IDR with the Revision Number, Device ID, JEDEC ID, and ID Register Indicator Bit. See Table 10. TABLE 10 — IDENTIFICATION REGISTER DEFINITIONS INSTRUCTION FIELD Revision Number (31:28) VALUE 0x0 DESCRIPTION Reserved for version number IDT Device ID (27:12) 0x436 Defines IDT part number IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register TABLE 11 — SCAN REGISTER SIZES REGISTER NAME Instruction (IR) BIT SIZE 4 Bypass (BYR) 1 Identification (IDR) 32 Boundary Scan (BSR) Note(1) NOTES: 1. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative. 12 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE TABLE 12 — SYSTEM INTERFACE PARAMETERS INSTRUCTION CODE EXTEST 0000 Forces contents of the boundary scan cells onto the device outputs(1). Places the boundary scan register (BSR) between TDI and TDO. BYPASS 1111 Places the bypass register (BYR) between TDI and TDO. IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. HIGH-Z 0100 Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state. CLAMP 0011 Places the bypass register (BYR) between TDI and TDO. Forces contents of the boundary scan cells onto the device outputs. SAMPLE/PRELOAD 0001 Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs(2) and outputs(1) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. RESERVED DESCRIPTION All other codes Several combinations are reserved. Do not use other codes than those identified above. NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS and TRST. TABLE 13 — JTAG AC ELECTRICAL CHARACTERISTICS (1,2,3,4) SYMBOL PARAMETER MIN. MAX. UNITS tJCYC JTAG Clock Input Period 100 ns tJCH JTAG Clock HIGH 40 ns tJCL JTAG Clock LOW 40 ns tJR JTAG Clock Rise Time 3(1) ns tJF JTAG Clock Fall Time 3(1) ns tJRST JTAG Reset 50 ns tJRSR JTAG Reset Recovery 50 ns tJCD JTAG Data Output 25 ns tJDC JTAG Data Output Hold 0 ns tJS JTAG Setup 15 ns tJH JTAG Hold 15 ns NOTES: 1. Guaranteed by design. 2. 30pF loading on external output signals. 3. Refer to AC Electrical Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet. tJCYC tJR tJF tJCL tJCH TCK Device Inputs(1) TDI/TMS tJH tJS Device tJDC Outputs(2) TDO tJCD tJRSR 5932 drw06 TRST tJRST NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. 2. Device outputs = All device outputs except TDO. Figure 3. JTAG Timing Specifications 13 x IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE TABLE 14 — BOUNDARY SCAN REGISTER BITS Device Pin ODE RESET C32i F32i FE DS CS R/W A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DTA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RX31 RX30 RX29 RX28 RX27 RX26 RX25 RX24 TX31/OEI15 TX30/OEI14 TX29/OEI13 TX28/OEI12 Boundary Scan Bit 0 to bit 168 Input Output Three-State Scan Cell Scan Cell Control 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Device Pin TX27/OEI11 TX26/OEI10 TX25/OEI9 TX24/OEI8 TX23/OEI7 TX22/OEI6 TX21OEI5 TX20/OEI4 TX19/OEI3 TX18/OEI2 TX17/OEI1 TX16/OEI0 RX23 RX22 RX21 RX20 RX19 RX18 RX17 RX16 RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 14 Boundary Scan Bit 0 to bit 168 Input Output Three-State Scan Cell Scan Cell Control 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE APPLICATIONS Device #2 is used to switch out on TX 32-63. Likewise Device #3 and Device #4 are used in the same way as Device #1 and Device #2 but switch RX 32-63 to TX0-31 and TX32-63, respectively. With this configuration all possible combinations of input and output streams are possible. In short, Device #1 is used to switch RX0-31 to TX0-31, Device #2 to switch RX0-31 to TX32-63, Device #3 to switch RX 32-63 to TX0-31, and Device #4 to switch RX32-63 to TX32-63. CREATING LARGE SWITCH MATRICES To create a switch matrix with twice the capacity of a given TSI device, four devices must be used. In the example below, four IDT72V73260, 16K x 16K channel capacity devices are used to create an 32K x 32K channel switch matrix. As can be seen, Device #1 and Device #2 will receive the same incoming RX0-31 data and thus have the same contents in Data Memory. On the output side, however Device #1 is used to switch data out on to TX0-31 where as RX0-31 Device 1 IDT72V73260 TX0-31 Device 2 IDT72V73260 RX32-63 TX32-63 Device 3 IDT72V73260 Device 4 IDT72V73260 5932 drw07 Figure 4. Creating Larger Switch Matrices 15 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE Using OEI RX0-15 AOE=0 OEI=1 RX0-15 TX0-15 RX16-31 OEI0-15 AOE=0 OEI=0 RX0-15 TX0-15 RX16-31 TX16-31 TX16-31 OEI=1 AOE=0 RX0-15 RX16-31 TX0-15 TX0-15 OEI0-15 RX16-31 AOE=0 OEI=0 RX0-15 TX0-15 RX16-31 TX16-31 AOE=0 Using AOE OEI16-31 OEI0-15 OEI=0 RX0 RX0 TX0 TX0 RX31 RX31 TX31 TX31 OEI=0 AOE=1 RX0 RX31 RX0 RX31 OEI0 OEI0 OEI 31 OEI31 5932 drw08 Figure 5. Using All Output Enable (AOE) 16 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC Vi Parameter Min. Max. Unit Supply Voltage -0.5 +4.0 V GND -0.3 VCC +0.3 V Voltage on Digital Inputs IO Current at Digital Outputs -50 50 mA TS Storage Temperature -55 +125 °C PD Package Power Dissapation 2 RECOMMENDED OPERATING CONDITIONS(1) Symbol W NOTE: 1. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Parameter Min. Typ. Max. Unit VCC Positive Supply 3.0 3.3 3.6 V VIH Input HIGH Voltage 2.0 VCC V VIL Input LOW Voltage -0.3 0.8 V TOP Operating Temperature Industrial -40 25 +85 °C NOTE: 1. Voltages are with respect to Ground unless otherwise stated. DC ELECTRICAL CHARACTERISTICS Symbol ICC (2) IIL(3,4) Parameter Supply Current Input Leakage (input pins) @32.768Mb/s Min. Typ. Max. Units 140 200 mA 60 µA High-Impedance Leakage 60 µA VOH(5) Output HIGH Voltage 2.4 V VOL(6) Output LOW Voltage 0.4 V IOZ (3,4) NOTES: 1. Voltages are with respect to ground (GND) unless otherwise stated. 2. Outputs unloaded. 3. 0 ≤ V ≤ VCC. 4. Maximum leakage on pins (output or I/O pins in high-impedance state) is over an applied voltage (V). 5. IOH = 10 mA. 6. IOL = 10 mA. 17 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - TIMING PARAMETER MEASUREMENT VOLTAGE LEVELS Symbol Rating Level Unit VTT TTL Threshold 1.5 V VHM TTL Rise/Fall Threshold Voltage HIGH 2.0 V VLM TTL Rise/Fall Threshold Voltage LOW 0.8 V 1 ns Input Pulse Levels tr,tf V Input Rise/Fall Times (1) Input Timing Reference Levels V Output Reference Levels V CL Output Load 50 pF Cin(2) Input Capacitance 8 pF NOTES: 1. JTAG CL is 30 pF 2. For 144 TQFP 3.3v VDD 330Ω 50Ω Z0 = 50Ω I/O D.U.T. 5932 drw10 510Ω 30pF* 5932 Drw09 Figure 6. Output Load Figure 7. Output Load ∆tSOD (Typical, ns) 6 5 4 Not Yet 3 2 Cha rac teri 1 20 30 50 80 100 Capacitance (pF) zed 200 5932 drw11 Figure 8. Lumped Capacitive Load, Typical Derating 18 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLOCK Symbol Parameter Min. Typ. tFPW Frame Pulse Width Bit rate = 32.768Mb/s 13 tFPS Frame Pulse Setup time before C32i falling 5 tFPH Frame Pulse Hold Time from C32i falling tCP C32i Period Bit rate = 32.768Mb/s tCH C32i Pulse Width HIGH Bit rate = 32.768Mb/s tCL C32i Pulse Width LOW Bit rate = 32.768Mb/s 19 Max. Units 31 ns ns 10 ns 29 30.5 35 ns 13 15 20 ns 13 15 20 ns IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE tODE(1) RESET tZR tRZ tRZ tRS TX tODELZ ODE 5932 drw12 NOTE: 1. To guarantee TX outputs remain in high-Impedance. Figure 9. Reset and ODE Timing C32i (ST-BUS mode) C32i (GCI mode) tSOD ODE tCHZ TX tODEA tODEL tODEHZ Z VALID DATA TX tCLZ VALID DATA 5932 drw14 TX tSIH VALID DATA 5932 drw13 Figure 10. Serial Output and External Control Figure 11. Output Driver Enable (ODE) 20 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - MICROPROCESSOR INTERFACE TIMING Symbol Parameter Min. Typ. Max. Units tCSS tRWS CS Setup from DS falling 0 ns R/W Setup from DS falling 3 ns tADS Address Setup from DS falling 2 ns tCSH CS Hold after DS rising 0 ns tRWH R/W Hold after DS Rising 3 ns tADH Address Hold after DS Rising 2 ns tDDR Data Setup from DTA LOW on Read 1 ns tDHR Data Hold on Read 10 15 25 ns tDSW Data Setup on Write (Register Write) 10 ns tSWD Valid Data Delay on Write (Connection Memory Write) 0 ns tDHW Data Hold on Write 5 ns tAKD Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory 32 80 ns ns @ 32.768Mb/s tAKH Acknowledgment Hold Time 20 ns tDSS Data Strobe Setup Time 6 ns 21 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE C32i GCI C32i ST-BUS tDSS DS tCSH tCSS CS tRWH tRWS R/W tADH tADS VALID ADDRESS A0-A11 tDHR D0-D15 READ VALID READ DATA tSWD tDSW D0-D15 WRITE tDHW VALID WRITE DATA tDDR tAKD DTA tAKH 5932 drw15 NOTE: 1. For quick microprocessor access tDSS must be met. In this case tAKD = tAKD (max) - C32i (period)+ tDSS. Figure 12. Motorola Non-Multiplexed Bus Timing 22 tr tf tOEI tOEI tFPS tclz tFPH tFPW Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 tCH tCP Figure 13. Output Enable Timing (ST-BUS® ) NOTES: 1. When Output Enable Polarity = 1, Output Enable Indication is HIGH when TX is active and LOW when TX is in Three-State. 2. When Output Enable Polarity = 0, Output Enable Indication is LOW when TX is active and HIGH when TX is in Three-State. OEI(2) OEI(1) TX C32i F32i tCL Bit 2 Bit 1 Bit 0 tOEI tOEI tCHZ 5932 drw16 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE 23 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS — SERIAL STREAM (ST-BUS® and GCI) Symbol Parameter tSIS RX Setup Time Min. Typ. Max. Units 2 ns tSIH tSOD RX Hold Time 4 ns Clock to Valid Data 4 12 ns tCHZ Clock to High-Z 9 ns tCLZ Clock to Low-Z 3 ns tODE Output Driver Enable to Reset HIGH 5 ns tODEHZ Output Driver Enable (ODE) to High-Z 9 ns tODELZ Output Driver Enable (ODE) to Low-Z 5 ns tOEI Output Enable Indicator 8 12 ns tRZ Active to High-Z on Master Reset 12 ns tZR High-Z to Active on Master Reset 12 ns tRS Reset pulse width 20 ns tODEA Output Driver Enable to Active 6 16 ns 24 Bit 2 Bit 2 tr Bit 1 Bit 1 tf Bit 0 Bit 0 tFPS tSIS 25 Bit 5 Bit 6 Bit 6 tr Bit 7 Bit 7 tf tSIS Bit 0 Bit 0 tSOD tFP H tFPW tFPS 1. @ 32.768Mb/s mode, last channel = ch 512. NOTE: RX 32 Mb/s TX 32 Mb/s C32i F32i Bit 7 Bit 7 tSOD tFPH tFPW tSIH 1. @ 32.768 Mb/s mode, last channel = ch 512. NOTE: RX 32 Mb/s TX 32 Mb/s C32i F32i Bit 6 Bit 1 Bit 1 tSIH Bit 6 Bit 2 Bit 2 Bit 5 Bit 5 Bit 3 Bit 3 Bit 3 Bit 3 tCP tCL Bit 2 Bit 2 Bit 1 Bit 1 Bit 0 Bit 0 Bit 7 Bit 7 tCL Bit 4 tCP Bit 5 Bit 5 Bit 6 Bit 6 Bit 7 Bit 7 Bit 0 Bit 0 Figure 15. Serial Interface Timing (GCI Style) Bit 4 tCH Bit 1 Bit 6 Bit 1 Bit 6 Figure 14. Serial Interface Timing (ST-BUS Style) Bit 4 Bit 4 tCH Bit 5 Bit 2 Bit 2 Bit 5 Bit 4 Bit 3 Bit 3 Bit 4 Bit 4 Bit 3 Bit 4 Bit 3 Bit 5 Bit 2 Bit 5 Bit 2 Bit 6 Bit 1 Bit 6 Bit 1 Bit 0 Bit 7 Bit 7 Bit 7 5932 drw17 5932 drw18 Bit 0 Bit 7 IDT72V73260 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 x 16,384 INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXXX Device Type X XX Package Process/ Temperature Range BLANK Commercial (-40°C to +85°C) BB DA Plastic Ball Grid Array (PBGA, BB144-1) Thin Quad Flatpacks (TQFP, DA144-1) 72V73260 16,384 x 16,3843.3V Time Slot Interchange Digital Switch 5932 drw19 DATASHEET DOCUMENT HISTORY 08/15/2001 09/24/2001 12/19/2001 12/21/2001 03/25/2002 08/02/2002 05/27/2003 10/10/2003 pgs. 2, 3, 18, 19, 21, 22, 23 and 24. pgs. 11, 21, 23 and 24. pgs. 1-7, 9-15, 18-25 and 27. pgs. 1, 6, 7, 9, 13, 14, 18, 19, 20, 21 and 25. pgs. 18 and 19. pg. 9 pgs. 1, 3, 19 and 26. pg. 1 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 26 for Tech Support: 408-330-1753 email: [email protected]