HD74CBT1G125 Single FET Bus Switch ADE-205-645 (Z) Rev. 0 Jan. 2002 Description The HD74CBT1G125 features a single high-speed line switch. The switch is disabled when the output enable (OE) input is high. Features • Minimal propagation delay through the switch. • 5 Ω switch connection between two ports. • TTL-compatible input levels. • Ultra low quiescent power. -Ideally suited for notebook applications. • Package type Package type Package code Package suffix Taping code CMPAK–5pin CMPAK–5 CM E (3000pcs / Reel) HD74CBT1G125 Outline and Article Indication • HD74CBT1G125 Index band Marking B = Control code ( or blank) CMPAK–5 Function Table Input OE Function L A port = B port H Disconnect H: L: High level Low level Pin Arrangement OE 1 A 2 GND 3 (Top view) Rev.0, Jan. 2002, page 2 of 9 B 5 VCC 4 B HD74CBT1G125 Absolute Maximum Ratings Item Symbol Ratings Unit VCC −0.5 to 7.0 V VI −0.5 to 7.0 V Input clamp current IIK −50 mA VI < 0 Continuous output current IO 128 mA VO = 0 to VCC Continuous current through VCC or GND ICC or IGND ±100 mA Maximum power dissipation *2 at Ta = 25°C (in still air) PT 200 mW Storage temperature Tstg −65 to 150 °C Supply voltage range Input voltage range Notes: *1 Conditions The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded even if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation was calculated using a junction temperature of 150°C. Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC 4.0 5.5 V Input voltage range VI 0 5.5 V Output voltage range VI/O 0 5.5 V Input transition rise or fall rate ∆t / ∆v 0 5 ns / V Operating free-air temperature Ta −40 85 °C Conditions VCC = 4.5 to 5.5 V Note: Unused or floating inputs must be held high or low. Rev.0, Jan. 2002, page 3 of 9 HD74CBT1G125 DC Electrical Characteristics (Ta = −40 to 85°C) Item Symbol VCC (V) Min Typ Clamp diode voltage VIK 4.5 Input voltage VIH 4.0 to 5.5 VIL RON On-state switch *2 resistance *1 Max Unit Test conditions −1.2 V IIN = −18 mA 2.0 V 4.0 to 5.5 0.8 4.0 14 20 4.5 5 7 VIN = 0 V, IIN = 64 mA 4.5 5 7 VIN = 0 V, IIN = 30 mA 4.5 10 15 VIN = 2.4 V, IIN = 15 mA Ω VIN = 2.4 V, IIN = 15 mA Typ at VCC = 4.0 V Input current IIN 0 to 5.5 ±1.0 µA VIN = 5.5 V or GND Off-state leakage current IOZ 5.5 ±1.0 µA 0 ≤ A, B ≤ VCC Quiescent supply current ICC 5.5 1.0 µA VIN = VCC or GND, IO = 0 mA Increase in ICC *3 per input ∆ICC 5.5 2.5 mA One input at 3.4 V, other inputs at VCC or GND Notes: For condition shown as Min or Max use the appropriate values under recommended operating conditions. 1. All typical values are at VCC = 5 V (unless otherwise noted), Ta = 25°C. 2. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals. 3. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Capacitance (Ta = 25°C) Item Symbol VCC (V) Min Typ Max Unit Test conditions Control input capacitance CIN 5.0 3 pF VIN = 0 or 3 V Input / output capacitance CI/O (OFF) 5.0 5 pF VO = 0 or 3 V OE = VCC Note: This parameter is determined by device characterization is not production tested. Rev.0, Jan. 2002, page 4 of 9 HD74CBT1G125 Switching Characteristics (Ta = −40 to 85°C) • VCC = 4.0 V Test conditions FROM (Input) TO (Output) ns CL = 50 pF RL = 500 Ω A or B B or A 5.5 ns CL = 50 pF RL = 500 Ω OE A or B 4.5 ns OE A or B tLZ 4.5 CL = 50 pF RL = 500 Ω Item Symbol Min Max Unit Test conditions FROM (Input) TO (Output) Propagation delay *1 time tPLH tPHL 0.25 ns CL = 50 pF RL = 500 Ω A or B B or A Enable time tZH tZL 1.6 4.9 ns CL = 50 pF RL = 500 Ω OE A or B Disable time tHZ 1.0 4.2 ns OE A or B tLZ 1.0 4.8 CL = 50 pF RL = 500 Ω Item Symbol Min Max Unit Propagation delay *1 time tPLH tPHL 0.35 Enable time tZH tZL Disable time tHZ • VCC = 5.0±0.5 V Note: 1. The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Rev.0, Jan. 2002, page 5 of 9 HD74CBT1G125 Test Circuit See under table 500 Ω S1 OPEN GND *1 CL = 50 pF 500 Ω Load circuit for outputs Symbol S1 t PLH / tPHL OPEN t ZH / t HZ OPEN t ZL / t LZ 7V Note: 1. CL includes probe and jig capacitance. Rev.0, Jan. 2002, page 6 of 9 HD74CBT1G125 Waveforms – 1 tr tf 90 % 1.5 V Input 3V 90 % 1.5 V 10 % 10 % t PLH GND t PHL V OH 1.5 V Output 1.5 V V OL Waveforms – 2 tf tr 90 % Output Control 3V 90 % 1.5 V 1.5 V 10 % t ZL 10 % GND t LZ 3.5 V Waveform - A 1.5 V V OL + 0.3 V t ZH t HZ V OH - 0.3 V Waveform - B V OL V OH 1.5 V GND Notes: 1. All input pulses are supplied by generators having the following characteristics : PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. 2. Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.0, Jan. 2002, page 7 of 9 HD74CBT1G125 Package Dimensions As of July, 2001 (0.65) 1.25 ± 0.1 (0.65) 0 – 0.1 (0.2) 2.0 ± 0.2 0.9 ± 0.1 (0.425) 5 – 0.2 ± 0.05 + 0.1 0.15– 0.05 2.1 ± 0.3 1.3 ± 0.2 (0.425) Unit: mm Hitachi Code JEDEC JEITA Mass (reference value) Rev.0, Jan. 2002, page 8 of 9 CMPAK-5(T) — Conforms 0.006 g HD74CBT1G125 Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Sales Offices Hitachi, Ltd. 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(Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 5.0 Rev.0, Jan. 2002, page 9 of 9