ETC HD74CBT3253

HD74CBT3253
Dual 1-of-4 FET Multiplexer / Demultiplexer
ADE-205-616A (Z)
Rev.1
May 2001
Description
The HD74CBT3253 is a dual 1-of-4 high-speed TTL-compatible FET multiplexer / demultiplexer. The
low on-state resistance of the switch allows connections to be made with minimal propagation delay.
1OE, 2OE, S0, and S1 select the appropriate B output for the A-input data.
Features
• Minimal propagation delay through the switch.
• 5 Ω switch connection between two ports.
• TTL-compatible input levels.
• Ultra low quiescent power.
-Ideally suited for notebook applications.
HD74CBT3253
Function Table
Inputs
1OE
OE
2OE
OE
S1
S0
Function
X
H
X
X
Disconnect 1A and 2A
H
X
X
X
Disconnect 1A and 2A
L
L
L
L
1A to 1B1 and 2A to 2B1
L
L
L
H
1A to 1B2 and 2A to 2B2
L
L
H
L
1A to 1B3 and 2A to 2B3
L
H
H
1A to 1B4 and 2A to 2B4
L
H:
L:
X:
High level
Low level
Immaterial
Pin Arrangement
1OE
1
16 VCC
S1
2
15 2OE
1B4
3
14 S0
1B3
4
13 2B4
1B2
5
12 2B3
1B1
6
11 2B2
1A
7
10 2B1
GND
8
9
(Top view)
Rev.1, May 2001, page 2 of 10
2A
HD74CBT3253
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
VCC
−0.5 to 7.0
V
VI
−0.5 to 7.0
V
Input clamp current
IIK
−50
mA
VI < 0
Continuous output current
IO
128
mA
VO = 0 to VCC
Continuous current through
VCC or GND
ICC or IGND
±100
mA
Maximum power dissipation
*2
at Ta = 25°C (in still air)
PT
500
mW
Storage temperature
Tstg
−65 to 150
°C
Supply voltage range
Input voltage range
Notes:
*1
Conditions
TSSOP
The absolute maximum ratings are values which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded even if the input and output clamp-current
ratings are observed.
2. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage range
VCC
4.0
5.5
V
Input voltage range
VI
0
5.5
V
Output voltage range
VI/O
0
5.5
V
Input transition rise or fall rate
∆t / ∆v
0
5
ns / V
Operating free-air temperature
Ta
−40
85
°C
Conditions
VCC = 4.5 to 5.5 V
Note: Unused or floating inputs must be held high or low.
Rev.1, May 2001, page 3 of 10
HD74CBT3253
Block Diagram
1A
7
6
1B1
5
1B2
4
1B3
3
2A
9
10
1B4
2B1
11
2B2
12
2B3
13
S0
S1
14
2
1
1OE
15
2OE
Rev.1, May 2001, page 4 of 10
2B4
HD74CBT3253
DC Electrical Characteristics
(Ta = −40 to 85°C)
Item
Symbol
VCC (V)
Clamp diode voltage
VIK
Input voltage
VIH
On-state switch
*2
resistance
Min
Typ
4.5

4.0 to 5.5
2.0
VIL
4.0 to 5.5
RON
*1
Max
Unit
Test conditions

−1.2
V
IIN = −18 mA


V


0.8
4.5

5
7
4.5

5
7
VIN = 0 V,
IIN = 30 mA
4.5

10
15
VIN = 2.4 V,
IIN = 15 mA
Ω
VIN = 0 V,
IIN = 64 mA
Input current
IIN
0 to 5.5


±1.0
µA
VIN = 5.5 V or GND
Off-state leakage
current
IOZ
5.5


±1.0
µA
0 ≤ A, B ≤ VCC
Quiescent supply
current
ICC
5.5


3
µA
VIN = VCC or GND,
IO = 0 mA
Increase in ICC
*3
per input
∆ICC
5.5


2.5
mA
One input at 3.4 V,
other inputs at VCC or
GND
Notes:
For condition shown as Min or Max use the appropriate values under recommended operating
conditions.
1. All typical values are at VCC = 5 V (unless otherwise noted), Ta = 25°C.
2. Measured by the voltage drop between the A and B terminals at the indicated current through the
switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals.
3. This is the increase in supply current for each input that is at the specified TTL voltage level
rather than VCC or GND.
Capacitance
(Ta = 25°C)
Item
Symbol
VCC (V)
Min
Typ
Max
Unit
Test conditions
Control input
capacitance
CIN
5.0

3.5

pF
VIN = 0 or 3 V
CI/O (OFF)
5.0

15

pF
VO = 0 or 3 V
5.0

5

Input / output
A port
capacitance
B port
OE = VCC
Note: This parameter is determined by device characterization is not production tested.
Rev.1, May 2001, page 5 of 10
HD74CBT3253
Switching Characteristics
(Ta = −40 to 85°C)
•
VCC = 4.0 V
Test
conditions
FROM
(Input)
TO
(Output)
ns
CL = 50 pF
RL = 500 Ω
A or B
B or A
6.6
ns
CL = 50 pF
RL = 500 Ω
S
A

7.1
ns
CL = 50 pF
RL = 500 Ω
S
B

7.3
OE
A or B

7.9
S
B

7.3
OE
A or B
Test
conditions
FROM
(Input)
TO
(Output)
Item
Symbol
Min
Max
Unit
Propagation delay
*1
time
tPLH
tPHL

0.35
Propagation delay
time
tPLH
tPHL

Enable time
tZH
tZL
Disable time
•
tHZ
tLZ
ns
CL = 50 pF
RL = 500 Ω
VCC = 5.0±0.5 V
Item
Symbol
Min
Max
Unit
Propagation delay
*1
time
tPLH
tPHL

0.25
ns
CL = 50 pF
RL = 500 Ω
A or B
B or A
Propagation delay
time
tPLH
tPHL
1.6
6.2
ns
CL = 50 pF
RL = 500 Ω
S
A
Enable time
tZH
tZL
1.3
6.3
ns
CL = 50 pF
RL = 500 Ω
S
B
1.4
6.4
OE
A or B
Disable time
tHZ
tLZ
1.1
7.4
ns
CL = 50 pF
RL = 500 Ω
S
B
2.3
7.0
OE
A or B
Note:
1. The propagation delay is the calculated RC time constant of the typical on-state resistance of the
switch and the specified load capacitance, when driven by an ideal voltage source (zero output
impedance).
Rev.1, May 2001, page 6 of 10
HD74CBT3253
Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
CL = 50 pF
500 Ω
Load circuit for outputs
Symbol
S1
t PLH / tPHL
OPEN
t ZH / t HZ
OPEN
t ZL / t LZ
7V
Note: 1. CL includes probe and jig capacitance.
Rev.1, May 2001, page 7 of 10
HD74CBT3253
Waveforms – 1
tr
tf
90 %
1.5 V
Input
3V
90 %
1.5 V
10 %
10 %
t PLH
GND
t PHL
V OH
1.5 V
Output
1.5 V
V OL
Waveforms – 2
tf
tr
90 %
Output
Control
3V
90 %
1.5 V
1.5 V
10 %
t ZL
10 %
GND
t LZ
3.5 V
Waveform - A
1.5 V
V OL + 0.3 V
t ZH
t HZ
V OH - 0.3 V
Waveform - B
V OL
V OH
1.5 V
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform - A is for an output with internal conditions such that the output is low except
when disabled by the output control.
3. Waveform - B is for an output with internal conditions such that the output is high except
when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
Rev.1, May 2001, page 8 of 10
HD74CBT3253
Package Dimensions
As of January, 2001
Unit: mm
4.40
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
1.10 Max
0.65 Max
0.10
*Dimension including the plating thickness
Base material dimension
6.40 ± 0.20
0.07 +0.03
−0.04
0.20 ± 0.06
1.0
*0.17 ± 0.05
0.15 ± 0.04
0.08
*0.22 +− 0.07
0° − 8°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
TTP-16DA


0.05 g
Rev.1, May 2001, page 9 of 10
HD74CBT3253
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Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
Colophon 4.0
Rev.1, May 2001, page 10 of 10