Automotive Series Serial EEPROM 125℃ Operating tempter SPI BUS BR25□□□□Family BR25H□□□-WC series No.09001ECT01 ●Description BR25H□□□-WC series is a serial EEPROM of SPI BUS interface method. ●Features 1) High speed clock action up to 5MHz (Max.) 2) Wait function by HOLDB terminal. 3) Part or whole of memory arrays settable as read only memory area by program. 4) 2.5～5.5V single power source action most suitable for battery use. 5) Page write mode useful for initial value write at factory shipment. 6) Highly reliable connection by Au pad and Au wire. 7) For SPI bus interface (CPOL, CPHA)=(0, 0), (1, 1) 8) Auto erase and auto end function at data rewrite. 9) Low current consumption At write action (5V) : 1.5mA (Typ.) At read action (5V) : 1.0mA (Typ.) At standby action (5V) : 0.1μA (Typ.) 10) Address auto increment function at read action 11) Write mistake prevention function Write prohibition at power on. Write prohibition by command code (WRDI). Write prohibition by WPB pin. Write prohibition block setting by status registers (BP1, BP0) Write mistake prevention function at low voltage. 12) SOP8, SOP-J8, TSSOP-B8 Package 13) Data at shipment Memory array: FFh, status register WPEN, BP1, BP0 : 0 14) Data kept for 40 years. 15) Data rewrite up to 1,000,000times. ●Page write Number of pages BR25H010-WC BR25H020-WC BR25H040-WC Product number ●BR25H series Capacity 16 Byte 32 Byte BR25H080-WC BR25H160-WC BR25H320-WC Bit format Type Power source voltage SOP8 SOP-J8 1Kbit 128×8 BR25H010-WC 2.5~5.5V ● ● 2Kbit 256×8 BR25H020-WC 2.5~5.5V ● ● 4Kbit 512×8 BR25H040-WC 2.5~5.5V ● ● TSSOP-B8 8Kbit 1K×8 BR25H080-WC 2.5~5.5V ● ● ● 16Kbit 2K×8 BR25H160-WC 2.5~5.5V ● ● ● 32Kbit 4Kx8 BR25H320-WC 2.5~5.5V ● ● www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●Absolute maximum ratings (Ta=25°C) Parameter Impressed voltage Symbol Limits VCC Unit -0.3~+6.5 560(SOP8) Permissible dissipation Pd V *1 560(SOP-J8) *2 410(TSSOP-B8) Storage temperature range Tstg Operating temperature range mW *3 -65~+150 °C Topr -40~+125 °C - -0.3~VCC+0.3 V Terminal voltage ・When using at Ta=25℃ or higher, 4.5mW (*1,*2), 3.3mW(*3) to be reduced per 1℃ ●Memory cell characteristics (VCC=2.5V～5.5V) Limits Parameter Number of data rewrite times *1 Data hold years*1 Unit Condition Min. Typ. Max. 1,000,000 - - Times Ta≤85°C 500,000 - - Times Ta≤105°C 300,000 - - Times Ta≤125°C 40 - - Years Ta≤25°C 20 - - Years Ta≤85°C *1:Not 100% TESTED ●Recommended action conditions Parameter Power source voltage Input voltage Symbol Limits VCC 2.5~5.5 Vin 0~VCC Unit V ●Input / output capacity (Ta=25°C, frequency=5MHz) Parameter Input capacity*1 Output capacity*1 Symbol Conditions Min Max CIN VIN=GND - 8 COUT VOUT=GND - 8 Unit pF *1: Not 100% TESTED www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●Electrical characteristics (Unless otherwise specified, Ta=-40~+125°C, VCC=2.5~5.5V) Limits Parameter Symbol Unit Conditions Min. Typ. Max. “H” input voltage VIH 0.7xVCC - VCC +0.3 V 2.5≦VCC≦5.5V “L” input voltage VIL -0.3 - 0.3x VCC V 2.5≦VCC≦5.5V “L” output voltage VOL 0 - 0.4 V IOL=2.1mA “H” output voltage VOH VCC-0.5 - VCC V IOH=-0.4mA Input leak current ILI -10 - 10 μA VIN=0~VCC Output leak current ILO -10 - 10 μA VOUT=0~VCC, CSB=VCC ICC1 - - 2.0 mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN VCC=2.5V,fSCK=5MHz, tE/W=5ms Current consumption at write action ICC2 - - 3.0 ICC3 - - 1.5 ICC4 - - 2.0 ISB - - 10 Byte write, Page write Write status register VCC=5.5V,fSCK=5MHz, tE/W=5ms mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN Byte write, Page write Write status register VCC=2.5V,fSCK=5MHz mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN Read, Read status register VCC=5.5V,fSCK=5MHz mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN Read, Read status register Current consumption at read action Standby current μA VCC=5.5V CSB=HOLDB=WPB=VCC, SCK=SI=VCC or =GND, SO=OPEN *Radiation resistance design is not made ●Block diagram CSB VOLTAGE INSTRUCTION DECODE DETECTION CONTROL CLOCK SCK GENERATION SI WRITE HIGH VOLTAGE INHIBITION GENERATOR INSTRUCTION REGISTER STATUS REGISTER HOLDB ADDRESS REGISTER ADDRESS 7～12bit *1 DECODER 7～12bit *1 1～32K EEPROM DATA WPB REGISTER SO *1 7bit: BR25H010-WC 8bit: BR25H020-WC 9bit: BR25H040-WC 10bit: BR25H080-WC 11bit: BR25H160-WC 12bit: BR25H320-WC READ/WRITE 8bit AMP 8bit Fig.1 Block diagram ●Pin assignment and description Terminal name Vcc HOLDB SCK SI BR25H010-WC BR25H020-WC BR25H040-WC BR25H080-WC BR25H160-WC BR25H320-WC CSB SO WPB Input/Output VCC - Power source to be connected GND - All input / output reference voltage, 0V CSB Input Chip select input SCK Input Serial clock input SI Input Start bit, ope code, address, and serial data input SO Output HOLDB Input WPB Input GND Fig.2 Pin assignment diagram Function Serial data output Hold input Command communications may be suspended temporarily (HOLD status) Write protect input Write command is prohibited *1 Write status register command is prohibited. *1:BR25H010/020/040-WC www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●Operating timing characteristics ●Sync data input / output timing (Ta=-40~+125°C, unless otherwise specified, load capacity CL1=100pF) 2.5≤VCC≤5.5V Parameter Symbol Unit Min. Typ. Max. MHz tCSS tCS CSB tSCKS fSCK - - 5 SCK high time tSCKWH 85 - - ns SCK low time tSCKWL 85 - - ns CSB high time tCS 85 - - ns CSB setup time tCSS 90 - - ns CSB hold time tCSH 85 - - ns SCK setup time tSCKS 90 - - ns SCK hold time tSCKH 90 - - ns SI setup time tDIS 20 - - ns SI hold time tDIH 30 - - ns SI Data output delay time1 Data output delay time2 tPD1 - - 70 ns SO (CL2=30pF) tPD2 - - 55 ns Output hold time tOH 0 - - ns Output disable time HOLDB setting setup time HOLDB setting hold time HOLDB release setup time HOLDB release hold time Time from HOLDB to output High-Z Time from HOLDB To output change SCK rise time*1 tOZ - - 100 ns tHFS 0 - - ns tHFH 40 - - ns tHRS 0 - - ns SI High-Z SO Fig.3 Input timing SI is taken into IC inside in sync with data rise edge of SCK. Input address and data from the most significant bit MSB. tCS tCSH tSCKH CSB SCK tPD 70 - - - - 100 70 ns tRC - - 1 μs tFC - - 1 μs OUTPUT rise time tRO - - 50 ns OUTPUT fall time*1 tFO - - 50 ns Write time tE/W - - 5 ms SCK fall time*1 Input / Output timing "H" CSB "L" tHFS tHFH tHRS tHRH SCK tDIS n n+1 tHOZ SO - tOZ SO is output in sync with data fall edge of SCK. Data is output from the most significant bit MSB. ns - *1 Fig.4 ns tHPD tRO,tFO tOH High-Z SI tHOZ tFC tDIS tDIH SCK frequency tHRH tRC tSCKWH tSCKWL SCK n-1 tHPD High-Z Dn Dn+1 Dn Dn-1 HOLDB Fig.5 HOLD timing *1 NOT 100% TESTED ●AC measurement conditions Parameter Symbol Limits Min. Typ. Max. Unit Load capacity 1 CL1 - - 100 pF Load capacity 2 CL2 - - 30 pF Input rise time - - - 50 ns Input fall time - - - 50 ns Input voltage - 0.2VCC/0.8VCC V Input / Output judgment voltage - 0.3VCC/0.7VCC V www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●Characteristic data (The following characteristic data are Typ. Value.) 6 4 Ta=-40℃ Ta=25℃ Ta=125℃ 5 4 3 VIL[V] SPEC 3 2 2 1 1 0 0.6 SPEC 0.4 0.2 SPEC 0 0 0 1 Ta=-40℃ Ta=25℃ Ta=125℃ 0.8 VOL[V] 5 VIH[V] 1 6 Ta=-40℃ Ta=25℃ Ta=125℃ 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 0 6 Fig.7 "L" input voltage VIL(CSB,SCK,SI,HOLDB,WPB) Fig.6 "H" input voltage VIH(CSB,SCK,SI,HOLDB,WPB) 10 8 2.1 Ta=-40℃ Ta=25℃ Ta=125℃ SPEC 2 1.9 1.8 Ta=-40℃ Ta=25℃ Ta=125℃ 6 4 4 2 2 0.4 0.8 0 1 2 3 Vcc[V] 4 5 6 0 SPEC ICC3,4(READ)[mA] SPEC 2 Ta=-40℃ Ta=25℃ Ta=125℃ 1 fSCK=5MHz DATA=AAh 2 SPEC Ta=-40℃ Ta=25℃ Ta=125℃ 1 1 2 3 Vcc[V] 4 5 6 4 1 2 3 Vcc[V] 4 5 0 6 Ta=-40℃ Ta=25℃ Ta=125℃ 60 40 20 0 1 2 3 Vcc[V] 4 5 Fig.15 SCK frequency fSCK 1 2 3 Vcc[V] 4 5 0 40 20 SPEC 60 40 1 2 3 Vcc[V] 4 5 6 Fig.18 CSB high time tCS www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4 5 6 SPEC 60 Ta=-40℃ Ta=25℃ Ta=125℃ 40 20 0 0 0 3 Vcc[V] 80 Ta=-40℃ Ta=25℃ Ta=125℃ 20 0 2 Fig.17 SCK low time tSCKWL tCSH[ns] tCSS[ns] Ta=-40℃ Ta=25℃ Ta=125℃ 1 100 80 SPEC 60 SPEC 40 6 100 80 6 Ta=-40℃ Ta=25℃ Ta=125℃ 60 Fig.16 SCK high time tSCKWH 100 5 0 0 6 4 20 0 0.1 3 Vcc[V] 80 SPEC tSCKWL [ns] tSCKWH [ns] fSCK[MHz] Ta=-40℃ Ta=25℃ Ta=125℃ 2 100 80 1 1 Fig.14 Consumption current at standby operation ISB Fig.13 Consumption Current at READ operation ICC3,4 100 SPEC SPEC 0 Fig.12 Current consumption at WRITE operation ICC1,2 10 6 2 0 100 5 6 0 0 4 Ta=-40℃ Ta=25℃ Ta=125℃ 8 SPEC 1.5 0.5 0 3 VOUT[V] 10 ISB[μA] fSCK=5MHz DATA=00h 3 2 12 2.5 4 1 Fig.11 Output leak current ILO(SO)(Vcc=5.5V) Fig.10 Input leak current ILI(CSB,SCK,SI,HOLDB,WPB) Fig.9 "H" output voltage VOH-IOH(Vcc=2.5V) 6 0 1.2 IOH[mA] ICC1,2[mA]] 6 0 0 5 Ta=-40℃ Ta=25℃ Ta=125℃ 8 ILO[μA] ILI[μA] VOH[V] 2.2 4 SPEC 10 2.4 2.3 3 IOL[mA] 12 SPEC 2.5 tCS[ns] 2 Fig.8 "L" output voltage VOL-IOL(Vcc=2.5V) 12 2.6 1 0 1 2 3 Vcc[V] 4 Fig.19 CSB setup time tCSS 5/19 5 6 0 1 2 3 Vcc[V] 4 5 6 Fig.20 CSB hold time tCSH 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●Characteristic data (The following characteristic data are Typ. Value.) 50 Ta=-40℃ Ta=25℃ Ta=125℃ 40 10 0 SPEC 30 20 40 0 1 2 3 Vcc[V] 4 5 0 0 6 1 2 3 Vcc[V] 4 5 6 0 Fig.22 SI hold time tDIH Fig.21 SI setup time tDIS Ta=-40℃ Ta=25℃ Ta=125℃ 100 SPEC tOZ [ns] 40 3 Vcc[V] 4 5 6 Ta=-40℃ Ta=25℃ Ta=125℃ 60 80 60 2 80 SPEC Ta=-40℃ Ta=25℃ Ta=125℃ 60 40 tHFH [ns] 80 1 Fig.23 Data output delay time tPD1(CL=100pF) 120 100 Ta=-40℃ Ta=25℃ Ta=125℃ 20 0 -20 tPD2 [ns] 60 10 -10 SPEC 80 SPEC tDIH[ns] tDIS[ns] 20 100 Ta=-40℃ Ta=25℃ Ta=125℃ tPD1 [ns] 30 SPEC 20 40 20 0 20 0 0 0 1 2 3 Vcc[V] 4 5 -20 0 6 3 Vcc[V] 4 5 6 0 SPEC tHOZ [ns] 40 20 60 1 2 3 Vcc[V] 4 5 6 Fig.27 HOLDB release hold time tHRH 20 1 2 3 Vcc[V] 4 5 0 6 Fig.28 Time from HOLDB to output High-Z tHOZ 80 40 tFO [ns] 60 SPEC 20 60 40 SPEC 1 2 3 4 5 6 Vcc[V] Fig.30 Output rise time tRO www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3 Vcc[V] 4 5 6 SPEC 4 2 0 0 0 Ta=-40℃ Ta=25℃ Ta=125℃ 6 20 0 2 8 Ta=-40℃ Ta=25℃ Ta=125℃ tE/W[ms] Ta=-40℃ Ta=25℃ Ta=125℃ 1 Fig.29 Time from HOLDB to output change tHPD 100 80 Ta=-40℃ Ta=25℃ Ta=125℃ -20 0 100 6 SPEC 0 0 0 5 40 Ta=-40℃ Ta=25℃ Ta=125℃ 20 -20 4 60 40 0 3 Vcc[V] SPEC 80 tHPD [ns] Ta=-40℃ Ta=25℃ Ta=125℃ 2 80 100 60 1 Fig.26 HOLDB setting hold time tHFH 120 80 tHRH [ns] 2 Fig.25 Output disable time tOZ Fig.24 Data output delay time tPD2(CL-30pF) tRO [ns] 1 0 1 2 3 Vcc[V] 4 Fig.31 Output fall time tFO 6/19 5 6 0 1 2 3 Vcc[V] 4 5 6 Fig.32 Write cycle time tE/W 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●Features ○Status registers This IC has status registers. The status registers are of 8 bits and express the following parameters. BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are valid even when power source is turned off. Rewrite characteristics and data hold time are same as characteristics of the EEPROM. WEN can be set by write enable command and write disable command. WEN becomes write disable status when power source is turned off. R/B is for write confirmation, therefore cannot be set externally. The value of status register can be read by read status command. ●Status registers Product number bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 1 1 1 BP1 BP0 WEN R/B WPEN 0 0 0 BP1 BP0 WEN R/B BR25H010-WC ― BR25H020-WC BR25H040-WC BR25H080-WC ― BR25H160-WC BR25H320-WC bit Memory location Function Contents WPB pin enable / disable designation bit WPEN EEPROM WPEN=0=invalid WPEN=1=valid BP1 BP0 WEN EEPROM EEPROM write disable block designation bit This enables / disables the functions of WPB pin. This designates the write disable area of EEPROM. Write designation areas of product numbers are shown below. Write and write status register write enable / disable status confirmation bit Register WEN=0=prohibited WEN=1=permitted Write cycle status (READY / BUSY) status confirmation bit ― R/B Register R/B=0=READY R/B=1=BUSY ●Write disable block setting BP1 BP0 0 0 1 1 0 1 0 1 BR25H010-WC None 60h-7Fh 40h-7Fh 00h-7Fh BR25H020-WC None C0h-FFh 80h-FFh 00h-FFh Write disable block BR25H040-WC BR25H080-WC None None 180h-1FFh 300h-3FFh 100h-1FFh 200h-3FFh 000h-1FFh 000h-3FFh BR25H160-WC BR25H320-WC None None 600h-7FFh C00h-FFFh 400h-7FFh 800h-FFFh 000h-7FFh 000h-FFFh ○WPB pin By setting WPB=LOW, write command is prohibited. As for BR25H080/160/320-WC, only when WPEN bit is set “1”, the WPB pin functions become valid. And the write command to be disabled at this moment is WRSR. As for BR25H010/ 020/040-WC, both WRITE and WRSR commands are prohibited. However, when write cycle is in execution, no interruption can be made. Product number BR25H010-WC BR25H020-WC BR25H040-WC BR25H080-WC BR25H160-WC BR25H320-WC WRSR WRITE Prohibition possible Prohibition possible Prohibition possible but WPEN bit “1” Prohibition impossible ○HOLDB pin By HOLDB pin, data transfer can be interrupted. When SCK=”0”, by making HOLDB from “1” into”0”, data transfer to EEPROM is interrupted. When SCK = “0”, by making HOLDB from “0” into “1”, data transfer is restarted. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●Command mode Ope code Command Contents BR25H010-WC BR25H020-WC BR25H040-WC BR25H080-WC BR25H160-WC BR25H320-WC WREN Write enable Write enable command 0000 *110 0000 *110 0000 0110 WRDI Write disable Write disable command 0000 *100 0000 *100 0000 0100 READ Read Read command 0000 *011 0000 A8011 0000 0011 WRITE Write Write command 0000 *010 0000 A8010 0000 0010 RDSR Read status register Status register read command 0000 *101 0000 *101 0000 0101 WRSR Write status register Status register write command 0000 *001 0000 *001 0000 0001 *=Don’t Care Bit. ●Timing chart 1. Write enable (WREN) / disable (WRDI) cycle WREN (WRITE ENABLE): Write enable CSB SCK SI 0 0 1 0 2 0 3 0 4 *1 5 6 1 1 7 0 High-Z SO Fig.33 Write enable command *1 BR25H010/020/040-WC= Don’t care BR25H080/160/320-WC= “0” input WRDI (WRITE DISABLE): Write disable CSB SCK SI SO 0 0 1 0 2 0 3 0 4 *1 5 7 6 1 0 0 High-Z Fig.34 Write disable *1 BR25H010/020/040-WC= Don’t care BR25H080/160/320-WC= “0” input ○This IC has write enable status and write disable status. It is set to write enable status by write enable command, and it is set to write disable status by write disable command. As for these commands, set CSB LOW, and then input the respective ope codes. The respective commands accept command at the 7-th clock rise. Even with input over 7 clocks, command becomes valid. When to carry out write and write status register command, it is necessary to set write enable status by the write enable command. If write or write status register command is input in the write disable status, commands are cancelled. And even in the write enable status, once write and write status register command is executed, it gets in the write disable status. After power on, this IC is in write disable status. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series 2. Read command (READ) ～ ～ ～ ～ CSB Product number BR25H010-WC BR25H020-WC BR25H040-WC ～ ～ 0 1 2 3 4 5 6 7 8 9 10 11 15 ～ ～ SCK 16 22 ～ ～ 0 0 ＊1 0 0 1 A7 1 A6 A5 A4 A1 ～ ～ 0 ～ ～ SI A0 ～ ～ ～ ～ SO High-Z D7 D6 D2 D1 3 4 5 6 7 8 12 0 0 0 1 ＊ 1 ＊ BR25H080-WC BR25H160-WC BR25H320-WC 30 ＊ A11 A1 ～ ～ 0 ～ ～ 0 ～ ～ 0 24 ～ ～ ～ ～ SI 23 ～ ～ 2 ～ ～ 1 Productnumber ～ ～ ～ ～ 0 BR25H040-WC=A8 ～ ～ ～ ～ SCK D0 *1 BR25H010/020-WC=Don’t care Fig.35 Read command (BR25H010/020/040-WC) CSB Address length A6-A0 A7-A0 A8-A0 A0 Address length A9-A0 A10-A0 A11-A0 ～ ～ ～ ～ ～ ～ High-Z SO D7 D6 D2 D1 D0 *=Don’t Care *1 BR25H010/020/040-WC=15 clocks BR25H080/160/320-WC=23 clocks Fig.36 Read command (BR25H080/160/320-WC) By read command, data of EEPROM can be read. As for this command, set CSB LOW, then input address after read ope *1 code. EEPROM starts data output of the designated address. Data output is started from SCK fall of 15/23 clock, and from D7 to D0 sequentially. This IC has increment read function. After output of data for 1 byte (8bits), by continuing input of SCK, data of the next address can be read. Increment read can read all the addresses of EEPROM. After reading data of the most significant address, by continuing increment read, data of the most insignificant address is read. 3. Write command (WRITE) ～ ～ ～ ～ CSB ～ ～ 0 3 4 ＊1 0 5 0 6 1 7 8 A7 0 A6 A5 A4 16 22 A1 A0 D7 D6 D2 D1 D0 Product number BR25H080-WC BR25H160-WC BR25H320-WC ～ ～ ～ ～ ～ ～ ～ ～ 0 6 1 7 0 8 ＊ ＊ 12 ＊ A11 23 24 30 A1 A0 D7 D6 31 D2 D1 D0 Address length A9-A0 A10-A0 A11-A0 ～ ～ High-Z ～ ～ 0 5 ～ ～ 0 4 ～ ～ ～ ～ 0 3 ～ ～ 0 2 ～ ～ SO 0 1 ～ ～ SI 0 ～ ～ SCK Address length A6-A0 A7-A0 A8-A0 *1 BR25H010/020-WC=Don’t care BR25H040-WC=A8 Fig.37 Write command (BR25H010/020/040-WC) CSB Product number BR25H010-WC BR25H020-WC BR25H040-WC 23 ～ ～ ～ ～ High-Z SO 15 ～ ～ 0 2 ～ ～ 0 1 ～ ～ ～ ～ SI 0 ～ ～ SCK ＊=Don't Care Fig.38 Write command (BR25H080/160/320-WC) By write command, data of EEPROM can be written. As for this command, set CSB LOW, then input address and data after write ope code. Then, by making CSB HIGH, the EEPROM starts writing. The write time of EEPROM requires time of tE/W (Max 5ms). During tE/W, other than status read command is not accepted. Start CSB after taking the last data (D0), and before the next SCK clock starts. At other timing, write command is not executed, and this write command is cancelled. This IC has page write function, and after input of data for 1 byte (8 bits), by continuing data input without *1 *2 starting CSB, data up to 16/32 bytes can be written for one tE/W. In page write, the insignificant 4/5 bit of the designated address is incremented internally at every time when data of 1 byte is input and data is written to respective addresses. When data of the maximum bytes or higher is input, address rolls over, and previously input data is overwritten. *1 BR25H010/020/040-WC=16 bytes at maximum BR25H080/160/320-WC=32 bytes at maximum * 2 BR25H010/020/040-WC=Insignificant 4 bits BR25H080/160/320-WC=Insignificant 5 bits www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series 4. Status register write / read command CSB SCK SI SO 0 1 0 2 0 0 3 4 ＊ 0 5 6 0 0 7 1 8 9 10 11 bit7 bit6 bit5 bit4 ＊ ＊ ＊ ＊ 12 13 bit3 14 bit2 15 bit1 bit0 ＊ ＊ BP1 BP0 High-Z ＊=Don't care Fig.39 Status register write command (BR25H010/020/040-WC) CSB SCK SI SO 0 1 0 2 0 0 3 0 4 0 5 6 0 0 7 1 8 9 bit7 bit6 WPEN ＊ 10 bit5 11 12 bit4 ＊ 13 bit3 ＊ 14 bit2 15 bit1 bit0 ＊ ＊ BP1 BP0 High-Z ＊=Don't care Fig.40 Status register write command (BR25H080/160/320-WC) *1 Write status register command can write status register data. The data can be written by this command are 2 bits , that is, BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be set. As for this command, set CSB LOW, and input ope code of write status register, and input data. Then, by making CSB HIGH, EEPROM starts writing. Write time requires time of tE/W as same as write. As for CSB rise, start CSB after taking the last data bit (bit0), and before the next SCK clock starts. At other timing, command is cancelled. Write disable block is determined by BP1 and BP0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array. (Refer to the write disable block setting table.) To the write disabled block, write cannot be made, and only read can be made. *1 3bits including BR25H080/160/320-WC WPEN (bit7) CSB SCK SI SO 0 1 0 0 2 0 3 4 ＊ 0 6 5 1 7 8 9 10 11 12 13 14 15 1 0 High-Z bit7 bit6 bit5 bit4 1 1 1 1 bit3 bit2 bit1 BP1 BP0 bit0 WEN R/B ＊=Don’t care Fig.41 Status register read command (BR25H010/020/040-WC) CSB SCK SI SO 1 0 0 0 2 0 3 0 High-Z 4 0 5 1 7 6 0 8 9 10 11 12 13 14 15 1 bit7 bit6 bit5 bit4 WPEN 0 0 0 bit3 bit2 BP1 BP0 bit1 bit0 WEN R/B Fig.42 Status register read command (BR25H080/160/320-WC) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●At standby ○Current at standby Set CSB “H”, and be sure to set SCK, SI, WPB, HOLDB input “L” or “H”. Do not input intermediate electric potantial. ○Timing As shown in Fig.43, at standby, when SCK is “H”, even if CSB is fallen, SI status is not read at fall edge. SI status is read at SCK rise edge after fall of CSB. At standby and at power ON/OFF, set CSB “H” status. Even if CSB is fallen at SCK=SI=”H”, SI status is not read at that edge. CSB Command start here. SI is read. SCK 0 1 2 SI Fig.43 Operating timing ●WPB cancel valid area WPB is normally fixed to “H” or “L” for use, but when WPB is controlled so as to cancel write status register command and write command, pay attention to the following WPB valid timing. While write or write status register command is executed, by setting WPB = “L” in cancel valid area, command can be cancelled. The area from command ope code before CSB rise at internal automatic write start becomes the cancel valid area. However, once write is started, any input cannot be cancelled. WPB input becomes Don’t Care, and cancellation becomes invalid. SCK 6 7 15 Ope Code 16 tE/W Data write time Data Valid (WEN is reset by WPB=L) Invalid Valid Invalid (BR25H010/020/040-WC) Invalid (BR25H080/160/320-WC) Fig.44 WPB valid timing (WRSR) *1 SCK 6 Ope Code 7 *2 24/32 15/23 8 Data Address Valid (WEN is reset by WPB=L) Invalid Invalid *1 *2 Invalid tE/W Data write time Invalid (BR25H010/020/040-WC) Invalid (BR25H080/160/320-WC) BR25H010/020/040-WC = 15 BR25H080/160/320-WC = 23 BR25H010/020/040-WC = 24 BR25H080/160/320-WC = 32 Fig.45 WPB valid timing (WRITE) ●HOLDB pin By HOLDB pin, command communication can be stopped temporarily (HOLD status). The HOLDB pin carries out command communications normally when it is HIGH. To get in HOLD status, at command communication, when SCK=LOW, set the HOLDB pin LOW. At HOLD status, SCK and SI become Don’t Care, and SO becomes high impedance (High-Z). To release the HOLD status, set the HOLDB pin HIGH when SCK=LOW. After that, communication can be restarted from the point before the HOLD status. For example, when HOLD status is made after A5 address input at read, after release of HOLD status, by starting A4 address input, read can be restarted. When in HOLD status, leave CSB LOW. When it is set CSB=HIGH in HOLD status, the IC is reset, therefore communication after that cannot be restarted. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 11/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●Method to cancel each command ○READ ・Method to cancel : cancel by CSB = “H” Ope code 8 bits Address Data 8 bits/16bits 8 bits Cancel available in all areas of read mode Fig.46 READ cancel valid timing ○RDSR ・Method to cancel : cancel by CSB = “H” Data Ope code 8 bits 8 bits Cancel available in all areas of rdsr mode Fig.47 RDSR cancel valid timing ○WRITE、PAGE WRITE a：Ope code, address input area. Cancellation is available by CSB=”H” b：Data input area (D7~D1 input area) Cancellation is available by CSB=”H” c：Data input area (D0 area) When CSB is started, write starts. After CSB rise, cancellation cannot be made by any means. d：tE/W area. Cancellation is available by CSB = “H”. However, when write starts (CSB is started) in the area c, cancellation cannot be made by any means. And by inputting on SCK clock, cancellation cannot be made. In page write mode, there is write enable area at every 8 clocks. Ope code 8bits Address Data 8bits/16bits 8bits a tE/W b d c SCK SI D7 D6 D5 D4 D3 D2 D1 D0 c b Fig.48 WRITE cancel valid timing Note 1) If VCC is made OFF during write execution, designated address data is not guaranteed, therefore write it once again. Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher. ○WRSR a：From ope code to 15 rise. Cancel by CSB =”H”. b：From 15 clock rise to 16 clock rise (write enable area). When CSB is started, write starts. After CSB rise, cancellation cannot be made by any means. c：After 16 clock rise. Cancel by CSB=”H”. However, when write starts (CSB is started) in the area b, cancellation cannot be made by any means. And, by inputting on SCK clock, cancellation cannot be made. 14 SCK D1 SI 15 b c tE/W Data 8 bits 17 D0 a Ope code 16 8 bits a c b Fig.49 WRSR cancel valid timing Note 1) If VCC is made OFF during write execution, designated address data is not guaranteed, therefore write it once again Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher. ○WREN/WRDI a：From ope code to 7-th clock rise, cancel by CSB = “H”. b：Cancellation is not available when CSB is started after 7-th clock. 7 SCK 8 9 Ope code 8 bits a b Fig.50 WREN/WRDI cancel valid timing www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 12/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●High speed operation In order to realize stable high speed operations, pay attention to the following input / output pin conditions. ○Input pin pull up, pull down resistance When to attach pull up, pull down resistance to EEPROM input pin, select an appropriate value for the microcontroller VOL, IOL from VIL characteristics of this IC. ○Pull up resistance RPU≥ Microcontroller IOLM EEPROM RPU VOLM VOLM≤ VILE “L” output “L” input VCC-VOLM IOLM ･･･① ･･･② VILE Example) When Vcc=5V, VILE=1.5V, VOLM=0.4V, IOLM=2mA, from the equation ①, RPU≥ Fig.51 Pull up resistance ∴RPU≥ 5-0.4 -3 2×10 2.3[kΩ] With the value of Rpu to satisfy the above equation, VOLM becomes 0.4V or lower, and with VILE (=1.5V), the equation ② is also satisfied. ・VILE :EEPROM VIL specifications ・VOLM :Microcontroller VOL specifications ・IOLM :Microcontroller IOL specifications And, in order to prevent malfunction, mistake write at power ON/OFF, be sure to make CSB pull up. ○Pull down resistance Microcontroller VOHM “H” output RPD≥ EEPROM VIHE IOHM RPD VOHM≥ VOHM ･･･③ IOHM ･･･④ VIHE “H” input Fig.52 Pull down resistance Example) When VCC=5V, VOHM=VCC-0.5V, IOHM＝0.4mA, VIHE=VCC×0.7V, from the equation③, RPD≥ 5-0.5 0.4×10 ∴RPU≥ -3 11.3[kΩ] Further, by amplitude VIHE, VILE of signal input to EEPROM, operation speed changes. By inputting signal of amplitude of VCC / GND level to input, more stable high speed operations can be realized. On the contrary, when amplitude of *1 0.8VCC / 0.2VCC is input, operation speed becomes slow. In order to realize more stable high speed operation, it is recommended to make the values of RPU, RPD as large as possible, and make the amplitude of signal input to EEPROM close to the amplitude of VCC / GND level. ж ( 1 At this moment, operating timing guaranteed value is guaranteed.) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 13/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series tPD_VIL characteristics 80 Spec 70 60 tPD[ns] 50 40 30 Vcc=2.5V 20 Ta=25℃ VIH=Vcc CL =100pF 10 0 0 0.2 0.4 0.6 0.8 1 VIL[V] Fig.53 VIL dependency of data output delay time tPD ○SO load capacity condition Load capacity of SO output pin affects upon delay characteristic of SO output. (Data output delay time, time from HOLDB to High-Z) In order to make output delay characteristic into higher speed, make SO load capacity small. In concrete, “Do not connect many devices to SO bus”, “Make the wire between the controller and EEPROM short”, and so forth. tPD-CL characteristics 80 Spec Vcc=2.5V Ta=25℃ VIH/VIL=0.8Vcc/0.2Vcc 70 tPD[ns] 60 EEPROM SO Spec 50 CL 40 30 20 0 20 40 60 80 100 120 CL[pF] Fig.54 SO load dependency of data output delay time tPD ○Other cautions Make the wire length from the microcontroller to EEPROM input signal same length, in order to prevent setup / hold violation to EEPROM, owing to difference of wire length of each input. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 14/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●Equivalent circuit ○Output circuit SO OEint. Fig.55 SO output equivalent circuit ○Input circuit RESETint. CSB Fig.56 CSB input equivalent circuit SCK SI Fig.57 SCK input equivalent circuit Fig.58 SI input equivalent circuit WPB HOLDB Fig.59 HOLDB input equivalent circuit www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Fig.60 WPB input equivalent circuit 15/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●Notes on power ON/OFF ○At power ON/OFF, set CSB “H” (=VCC). When CSB is “L”, this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause malfunction, mistake write or so. To prevent these, at power ON, set CSB “H”. (When CSB is in “H” status, all inputs are canceled.) Vcc Vcc GND Vcc CSB GND Good example Bad example Fig.61 CSB timing at power ON/OFF (Good example) CSB terminal is pulled up to VCC. At power OFF, take 10ms or higher before supply. If power is turned on without observing this condition, the IC internal circuit may not be reset, which please note. (Bad example) CSB terminal is “L” at power ON/OFF. In this case, CSB always becomes “L” (active status), and EEPROM may have malfunction, mistake write owing to noises and the likes. Even when CSB input is High-Z, the status becomes like this case, which please note. ○LVCC circuit LVCC (VCC-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.9V) or below, it prevent data rewrite. ○P.O.R. circuit This IC has a POR (Power On Reset) circuit as mistake write countermeasure. After POR action, it gets in write disable status. The POR circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the recommended conditions of the following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to noises and the likes. Recommended conditions of tR, tOFF, Vbot tR Vcc tOFF Vbot 0 Fig.62 Rise waveform www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 16/19 tR tOFF Vbot 10ms or below 10ms or higher 0.3V or below 100ms or below 10ms or higher 0.2V or below 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●Noise countermeasures ○VCC noise (bypass capacitor) When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a bypass capacitor (0.1μF) between IC VCC and GND. At that moment, attach it as close to IC as possible.And, it is also recommended to attach a bypass capacitor between board VCC and GND. ○SCK noise When the rise time (tR) of SCK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement. To avoid this, a Schmitt trigger circuit is built in SCK input. The hysterisis width of this circuit is set about 0.2V, if noises exist at SCK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR) of SCK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall time as small as possible. ○WPB noise During execution of write status register command, if there exist noises on WPB pin, mistake in recognition may occur and forcible cancellation may result, which please note. To avoid this, a Schmitt trigger circuit is built in WPB input. In the same manner, a Schmitt trigger circuit is built in CSB input, SI input and HOLDB input too. ●Note of use (1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is higher than that of GND terminal. (5) Heat design In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal short circuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of short circuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 17/19 2009.08 - Rev.C Technical Note BR25H□□□-WC series ●Ordering part number B R 2 Rohm type 5 H 0 1 0 Capacity F - W Package type C 2 BUS type Operating 25：SPI temperature 010= 1K F : SOP8 specification H:-40℃～+125℃ 020= 2K FJ : SOP-J8 E2: Embossed tape and reel 040= 4K Double cell E Packaging and forming FVT :TSSOP-B8 080= 8K 160=16K 320=32K SOP-J8 <Tape and Reel information> 4.9±0.2 (MAX 5.25 include BURR) +6° 4° −4° 6 5 0.45MIN 7 3.9±0.2 6.0±0.3 8 1 2 3 Tape Embossed carrier tape Quantity 2500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 4 0.545 0.2±0.1 1.375±0.1 S 0.175 1.27 0.42±0.1 0.1 S 1pin Reel (Unit : mm) Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. SOP8 <Tape and Reel information> 6 5 +6° 4° −4° 0.3MIN 7 4.4±0.2 6.2±0.3 8 1 2 3 0.9±0.15 5.0±0.2 (MAX 5.35 include BURR) Tape Embossed carrier tape Quantity 2500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 4 0.595 1.5±0.1 +0.1 0.17 -0.05 0.11 S 1.27 0.42±0.1 1pin Reel (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 18/19 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.08 - Rev.C Technical Note BR25H□□□-WC series TSSOP-B8 <Tape and Reel information> 3.0 ± 0.1 (MAX 3.35 include BURR) 8 7 6 4±4 3000pcs 3 4 1PIN MARK E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 1.0±0.2 0.5±0.15 6.4±0.2 4.4±0.1 2 0.525 +0.05 0.145 –0.03 S 0.1±0.05 1.2MAX Embossed carrier tape Quantity Direction of feed 1 1.0±0.05 Tape 5 0.08 S +0.05 0.245 –0.04 0.08 M 1pin 0.65 Reel (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 19/19 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.08 - Rev.C Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. R0039A