High Reliability Serial EEPROMs WL-CSP EEPROM family SPI BUS BU9832GUL-W No.10001EAT16 ●Description BU9832GUL-W is a serial EEPROM of SPI BUS interface method. ●Features 1) High speed clock action up to 5MHz (Max.) 2) Wait function by HOLD terminal. 3) Part or whole of memory arrays settable as read only memory area by program. 4) 1.8 ~ 5.5V single power source action most suitable for battery use. 5) Page write mode useful for initial value write at factory shipment. 6) For SPI bus interface (CPOL, CPHA) = (0, 0), (1, 1) 7) Auto erase and auto end function at data rewrite. 8) Low current consumption At write action (5V) : 1.5mA (Typ.) At read action (5V) : 1.0mA (Typ.) At standby action (5V) : 0.1µA (Typ.) 9) Address auto increment function at read action 10) Write mistake prevention function Write prohibition at power on. Write prohibition by command code (WRDI). Write prohibition by WP pin. Write prohibition block setting by status registers (BP1, BP0) Write mistake prevention function at low voltage. 11) Data at shipment Memory array: FFh, status register WPEN, BP1, BP0 : 0 12) Data kept for 40 years. 13) Data rewrite up to 1,000,000times. ●Page write Product number BU9832GUL-W Number of pages 32 Byte ●BU9832GUL-W Type BU9832GUL-W Capacity Bit format Power source voltage Package 8Kbit 1K×8 1.8~5.5V VCSP50L2 ●Absolute maximum ratings (Ta=25℃) Parameter Symbol Ratings Unit Impressed voltage Vcc -0.3~+6.5 V Permissible dissipation Pd 220(VCSP50L2) *1 mW Storage Temperature range Tstg -65~+125 ℃ Operating Temperature range Topr -40~+85 ℃ ― -0.3~Vcc+0.3 V Terminal voltage *1 When using at Ta=25℃ or higher, 220mW to be reduced per 1℃ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/18 2010.10 - Rev.A Technical Note BU9832GUL-W ● Recommended action conditions Parameter Symbol Ratings Power source voltage Vcc 1.8~5.5 Input voltage Vin 0~Vcc Unit V ● Memory cell characteristics (Ta=25℃, Vcc=1.8~5.5V) Limits Parameter Min. Typ. Max Unit Number of data rewrite times *1 1,000,000 – – Times Data hold years *1 40 – – Years *1 : Not 100% TESTED ● Input / output capacity (Ta=25℃, frequency=5MHz) Limits Parameter Symbol Min. Max Unit Conditions Input capacity *1 CIN – 8 pF VIN=GND Output capacity *1 COUT – 8 pF VOUT=GND *1 : Not 100% TESTED ●Electrical characteristics (Unless otherwise specified, Ta=-40~+85℃, Vcc=1.8~5.5V) Limits Symbol Unit Parameter Min. Typ. Max. Conditions “H” input voltage 1 VIH1 0.7xVcc – Vcc+0.3 V 1.8≦Vcc≦5.5V “L” input voltage 1 VIL1 -0.3 – 0.3xVcc V 1.8≦Vcc≦5.5V “L” output voltage 1 VOL1 0 – 0.4 V IOL=2.1mA(Vcc=2.5V~5.5V) “L” output voltage 2 VOL2 0 – 0.2 V IOL=150µA(Vcc=1.8V~2.5V) “H” output voltage 1 VOH1 Vcc-0.5 – Vcc V IOH=-0.4mA(Vcc=2.5V~5.5V) “H” output voltage 2 VOH2 Vcc-0.2 – Vcc V IOH=-100µA(Vcc=1.8V~2.5V) Input leak current ILI -1 – 1 µA VIN=0~Vcc Output leak current ILO -1 – 1 µA VOUT=0~Vcc, CS =Vcc ICC1 – – 1.0 mA ICC2 – – 2.0 mA ICC3 – – 3.0 mA ICC4 – – 1.5 mA ICC5 – – 2.0 mA ISB – – 2 µA Current consumption at write action Current consumption at read action Standby current Vcc=1.8V,fSCK=2MHz, tE/W=5ms Byte write, Page write, Write status register Vcc=2.5V,fSCK=5MHz, tE/W=5ms Byte write, Page write, Write status register Vcc=5.5V,fSCK=5MHz, tE/W=5ms Byte write, Page write, Write status register Vcc=2.5V,fSCK=5MHz Read, Read status register Vcc=5.5V,fSCK=5MHzN Read, Read status register Vcc=5.5V SCK=SI=Vcc or=GND,SO=OPEN ○This product is not designed for protection against radioactive rays. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/18 2010.10 - Rev.A Technical Note BU9832GUL-W ●Operating timing characteristics (Ta=-40~+85℃, unless otherwise specified, load capacity CL1=100pF) 1.8≤Vcc≺2.5V Parameter Symbol Min. Typ. Max. 2.5≤Vcc≺5.5V Min. Typ. Max. Unit SCK frequency fSCK – – 2 – – 5 MHｚ SCK high time tSCKWH 200 – – 85 – – ns SCK low time tSCKWL 200 – – 85 – – ns CS high time tCS 200 – – 85 – – ns CS setup time tCSS 200 – – 90 – – ns CS hold time tCSH 200 – – 85 – – ns SCK setup time tSCKS 200 – – 90 – – ns SCK hold time tSCKH 200 – – 90 – – ns SI setup time tDIS 40 – – 20 – – ns SI hold time tDIH 50 – – 40 – – ns Data output delay time1 tPD1 – – 150 – – 70 ns Data output delay time2 (CL2=30pF) tPD2 – – 145 – – 55 ns Output hold time tOH 0 – – 0 – – ns Output disable time tOZ – – 250 – – 100 ns HOLD setting setup time tHFS 120 – – 60 – – ns HOLD setting hold time tHFH 90 – – 40 – – ns HOLD release setup time tHRS 120 – – 60 – – ns HOLD release hold time tHRH 140 – – 70 – – ns Time from HOLD to output High-Z tHOZ – – 250 – – 100 ns Time from HOLD To output change tHPD – – 150 – – 70 ns SCK rise time *1 tRC – – 1 – – 1 µs SCK fall time *1 tFC – – 1 – – 1 µs Output rise time *1 tRO – – 100 – – 50 ns Output fall time *1 tFO – – 100 – – 50 ns tE/W – – 5 – – 5 ms Write time *1 NOT 100% TESTED ●AC measurement conditions Parameter Symbol Limits Min. Typ. Max. Unit Load capacity 1 CL1 – – 100 pF Load capacity 2 CL2 – – 30 pF Input rise time – – – 50 ns Input fall time – – – 50 ns Input voltage – 0.2Vcc/0.8Vcc V Input / Output judgment voltage – 0.3Vcc/0.7Vcc V www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/18 2010.10 - Rev.A Technical Note BU9832GUL-W ●Sync data input / output timing tCSS tCS "H" CS "L" CS tSCKS tSCKWL tRC tSCKWH tFC tHFS tHFH tHRS tHRH SCK SCK tDIS tDIS tDIH SI n n+1 SI tHOZ SO High-Z SO Dn+1 Dn n-1 tHPD High-Z Dn Dn-1 HOLD Fig.1 Input timing Fig.3 HOLD timing SI is taken into IC inside in sync with data rise edge of SCK. IInput address and data from the most significant bit MSB. tCS tCSH tSCKH CS SCK SI tPD tRO,tFO tOH tOZ High-Z SO Fig.2 Input / Output timing SO is output in sync with data fall edge of SCK. Data is output from the most significant bit MSB. ●Block diagram CS VOLTAGE INSTRUCTION DECODE DETECTION CONTROL CLOCK SCK GENERATION SI WRITE HIGH VOLTAGE INHIBITION GENERATOR INSTRUCTION REGISTER HOLD STATUS REGISTER ADDRESS REGISTER 11bit ADDRESS DECODER 11bit 1～64K EEPROM DATA WPB REGISTER 8bit READ/WRITE AMP 8bit SO Fig.4 Block diagram ●Pin assignment and description Land Terminal No. name Input/ Output A1 WPB Input A2 GND – A3 SI Input Function Write protect input Write status register command is prohibited. All input / output reference voltage, 0V C C1 B B1 A A1 A2 A3 B1 SO 1 2 3 B3 SCK Input Serial clock input C1 CS Input Chip select input C2 Vcc – C3 HOLD Input C2 C3 B3 Start bit, ope code, address, and serial data input INDEX post Fig.5 Pin assignment diagram www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Output Serial data output 4/18 Power source to be connected Hold input Command communication may be suspended temporarily (HOLD status) 2010.10 - Rev.A Technical Note BU9832GUL-W ●Characteristic data (The following characteristic data are Typ. Values.) 6 6 Ta=-40℃ Ta=25℃ Ta=85℃ 5 5 Ta=-40℃ Ta=25℃ Ta=85℃ 0.8 3 VOL[V] 4 SPEC VIL[V] 3 0.6 0.4 SPEC 2 2 1 1 0 0 0 1 2 3 Vcc[V] 4 5 0.2 SPEC 0 0 6 Fig.6 "H" input voltege VIH(CS,SCK,SI,HOLD,WP) 1 2 3 Vcc[V] 4 5 0 6 Fig.7 "L" input voltage VIL(CS,SCK,SI,HOLD,WP) 2 Ta=-40℃ Ta=25℃ Ta=85℃ 0.4 Ta=-40℃ Ta=25℃ Ta=85℃ 1.4 0.4 2 0.2 0.8 1.8 0 1.2 1 2 3 IOL[mA] IOH[mA] Fig.9 "H" output voltage VOH-IOH (Vcc=1.8V) 4 5 6 0 SPEC ICC1,2,3[mA] ILO[μA] ILI[μA] fSK=5MHz DATA=55h 3 1 0.5 1.2 4 SPEC Ta=-40℃ Ta=25℃ Ta=85℃ 0.8 Fig.11 "H" output voltage VOH-IOH (Vcc=2.5V) 1.5 1 0.4 IOH[mA] Fig.10 "L" output voltage VOL-IOL (Vcc=2.5V) 1.5 6 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 0 0 5 2.2 SPEC 1.2 4 2.4 0.6 VOL[V] SPEC 3 2.6 0.8 1.6 2 Fig.8 "L" output voltage VOL-IOL (Vcc=1.8V) 1 1.8 1 IOL[mA] VOH[V] VIH[V] 4 VOH[V] 1 Ta=-40℃ Ta=25℃ Ta=85℃ Ta=-40℃ Ta=25℃ Ta=85℃ 0.5 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 2 SPEC 1 0 0 1 2 3 Vcc[V] 4 5 0 0 6 0 1 Fig.12 Input leak current ILI(CS,SCK,SI,HOLD,WP) 4 5 0 6 2 3 Vcc[V] fSCK[MHz] ISB[μA] Ta=-40℃ Ta=25℃ Ta=85℃ 1.5 1 10 SPEC SPEC Ta=-40℃ Ta=25℃ Ta=85℃ 1 0.5 0.5 0 0 2 3 Vcc[V] 4 5 0 6 1 2 3 4 5 0.1 6 0 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC tSCKWL[ns] 200 150 SPEC 100 150 100 1 2 3 4 5 Vcc[V] Fig.18 tSCK high time tSCKWH www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6 6 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 100 50 0 0 5 150 SPEC 50 50 4 SPEC 200 tCS[ns] Ta=-40℃ Ta=25℃ Ta=85℃ 3 Vcc[V] 250 250 200 2 Fig.17 SCK frequency fSCK Fig.16 Consumption current at standby operation ISB 250 SPEC 1 Vcc[V] Fig.15 Consumption current at READ operation ICC4,5(READ,WRSR,fSK=5MHz) 0 6 2 Ta=-40℃ Ta=25℃ Ta=85℃ 1 5 100 SPEC 1.5 0 4 SPEC SPEC 1 1 Fig.14 Current consumption at WRITE operation ICC1,2,3 (WRITE,PAGE WRITE,WRSR,fSCK=5MHz) 2.5 fSK=5MHz DATA=55h 2 ICC4,5[mA] 3 Vcc[V] Fig.13 Output leak current ILO(SO) 2.5 tSCKWH[ns] 2 0 1 2 3 4 5 Vcc[V] Fig.19 tSCK low time tSCKWL 5/18 6 0 0 1 2 3 4 5 6 Vcc[V] Fig.20 CS high time tCS 2010.10 - Rev.A Technical Note BU9832GUL-W ●Characteristic data (The following characteristic data are Typ. Values.) 250 150 SPEC 200 100 SPEC 50 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 100 -50 0 1 2 3 Vcc[V] 4 5 0 1 2 3 Vcc[V] 4 5 0 6 1 tPD1[ns] 100 SPEC 20 SPEC 150 tPD2[ns] SPEC 40 Ta=-40℃ Ta=25℃ Ta=85℃ 3 Vcc[V] 4 5 6 200 Ta=-40℃ Ta=25℃ Ta=85℃ 150 SPEC 2 Fig.23 SI setup time tDIS 200 SPEC 30 0 Fig.22 CS hold time tCSH 60 50 20 -40 0 6 Ta=-40℃ Ta=25℃ Ta=85℃ -20 Fig.21 CS setup time tCSS tDIH[ns] SPEC 150 50 0 SPEC 40 tDIS[ns] SPEC tCSH[ns] 200 tCSS[ns] 60 250 Ta=-40℃ Ta=25℃ Ta=85℃ Ta=-40℃ Ta=25℃ Ta=85℃ 100 SPEC 50 50 10 0 0 1 2 3 4 5 0 0 6 0 1 2 3 Vcc[V] Vcc[V] 4 5 0 6 SPEC 100 150 SPEC 60 90 SPEC 40 100 5 6 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 120 80 tHFH[ns] 200 tOZ[ns] Ta=-40℃ Ta=25℃ Ta=85℃ 120 tHRH[ns] 250 4 150 140 Ta=-40℃ Ta=25℃ Ta=85℃ 3 Fig.26 Data output delay time tPD2(CL=30pF) 300 SPEC 2 Vcc[V] Fig.25 Data output delay time ｔPD1(CL=100pF) Fig.24 SI hold time tDIH 1 60 SPEC 30 20 50 0 0 -20 0 0 1 2 3 Vcc[V] 4 5 -30 0 6 1 2 3 6 0 Fig.28 HOLD setting hold time tHFH 300 Ta=-40℃ Ta=25℃ Ta=85℃ 120 CS 40 5 6 SPEC 60 CS CS 30 0 50 0 0 -40 1 4 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 90 tRO[ns] SPEC 3 Vcc[V] SPEC 80 tHPD[ns] 150 0 2 120 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 200 100 1 Fig.29 HOLD release hold time tHRH 160 SPEC 250 tHOZ[ns] 5 Vcc[V] Fig.27 Output disable time tOZ 2 3 Vcc[V] 4 5 6 0 Fig.30 Time From HOLD to output High-Z tHOZ 1 2 3 Vcc[V] 4 5 6 Fig.31 Time from HOLD to output change tHPD 0 1 2 3 Vcc[V] 4 5 6 Fig.32 Output rise time tRO 10 120 SPEC tE/W[ms] SPEC 60 Ta=-40℃ Ta=25℃ Ta=85℃ 8 Ta=-40℃ Ta=25℃ Ta=85℃ 90 tFO[ns] 4 30 6 SPEC 4 2 0 0 0 1 2 3 Vcc[V] 4 5 Fig.33 Output fall time tFO www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6 0 1 2 3 4 5 6 Vcc[V] Fig.34 Write cycle time tE/W 6/18 2010.10 - Rev.A Technical Note BU9832GUL-W ●Features ○Status registers This IC has status registers. The status registers are of 8 bits and express the following parameters. BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are valid even when power source is turned off. Rewrite characteristics and data hold time are same as characteristics of the EEPROM. WEN can be set by write enable command and write disable command. WEN becomes write disable status when power ― source is turned off. R/B is for write confirmation, therefore cannot be set externally. The value of status register can be read by read status command. ●Status registers Product number BU9832GUL-W bit Memory location WPEN EEPROM BP1 BP0 WEN ― R/B bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 WPEN 0 0 0 BP1 BP0 WEN R/B Function Contents WP pin enable / disable designation bit WPEN=0=invalid WPEN=1=valid EEPROM EEPROM write disable block designation bit Register Register ― This enables / disables the functions of WP pin. This designates the write disable area of EEPROM. Write designation areas of product numbers are shown below. Write and write status register write enable / disable status confirmation bit WEN=0=prohibited WEN=1=permitted Write cycle status (READY / BUSY) status confirmation bit R / B =0=READY R / B =1=BUSY ●Write disable block setting BP1 BP0 Write disable block 0 0 None 0 1 300h-3FFh 1 0 200h-3FFh 1 1 000h-3FFh ○ WP pin By setting WP =LOW, write command is prohibited. As for BU9832GUL-W when WPEN bit is set “1”, the WP pin functions become valid. And the write command to be disabled at this moment is WRSR. However, when write cycle is in execution, no interruption can be made. Product number BU9832GUL-W WRSR WRITE Prohibition possible but WPEN bit “1” Prohibition impossible ○ HOLD pin By HOLD pin, data transfer can be interrupted. When SCK=”1”, by making HOLD from “1” into”0”, data transfer to EEPROM is interrupted. When SCK = “0”, by making HOLD from “0” into “1”, data transfer is restarted. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 7/18 2010.10 - Rev.A Technical Note BU9832GUL-W ●Command mode Command WREN Write enable WRDI READ Contents Ope code Write enable command 0000 0110 Write disable Write disable command 0000 0100 Read Read command 0000 0011 WRITE Write Write command 0000 0010 RDSR Read status register Status register read command 0000 0101 WRSR Write status register Status register write command 0000 0001 ●Timing chart 1. Write enable (WREN) / disable (WRDI) cycle ・WREN (WRITE ENABLE): Write enable CS ――― CS 0 SCK SI 0 1 0 2 0 3 0 4 0 5 1 6 1 7 0 High-Z SO Fig.35 Write enable command ・WRDI (WRITE DISABLE): Write disable ――― CS CS 0 SCK SI 0 1 0 2 0 3 0 4 0 5 1 6 0 7 0 High-Z SO Fig.36 Write disable ○This IC has write enable status and write disable status. It is set to write enable status by write enable command, and it is set to write disable status by write disable command. As for these commands, set CS LOW, and then input the respective ope codes. The respective commands accept command at the 7-th clock rise. Even with input over 7 clocks, command becomes valid. When to carry out write and write status register command, it is necessary to set write enable status by the write enable command. If write or write status register command is input in the write disable status, commands are cancelled. And even in the write enable status, once write and write status register command is executed once, it gets in the write disable status. After power on, this IC is in write disable status. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/18 2010.10 - Rev.A Technical Note BU9832GUL-W 2. Read command (READ) 4 5 6 7 8 23 0 0 0 1 * 1 * * A9 A0 ～ ～ ～ ～ High-Z A1 D7 D6 ～ ～ ～ ～ ～ ～ 0 ～ ～ 0 ～ ～ SO 0 30 ～ ～ ～ ～ SI 24 ～ ～ 3 ～ 2 ～ ～ 1 ～ ～ 0 ～ ～ SCK ～ ～ CS D2 D1 D0 ＊=Don't Care Fig.37 Read command By read command, data of EEPROM can be read. As for this command, set CS LOW, then input address after read ope code. EEPROM starts data output of the designated address. Data output is started from SCK fall of 15 clock, and from D7 to D0 sequentially. This IC has increment read function. After output of data for 1 byte (8bits), by continuing input of SCK, data of the next address can be read. Increment read can read all the addresses of EEPROM. After reading data of the most significant address, by continuing increment read, data of the most insignificant address is read. 3. Write command (WRITE) 3 4 5 6 7 8 ～ ～ ～ ～ 2 ～ ～ 1 ～ ～ 0 ～ ～ SCK ～ ～ CS 23 24 30 ～ ～ ～ ～ 0 0 1 0 * * * A9 A1 A0 D7 D6 D2 D1 D0 ～ ～ High-Z 0 ～ ～ 0 ～ ～ 0 ～ ～ SO 0 ～ ～ SI 31 ＊=Don't Care Fig.38 Write command By write command, data of EEPROM can be written. As for this command, set CS LOW, then input address and data after write ope code. Then, by making CS HIGH, the EEPROM starts writing. The write time of EEPROM requires time of tE/W (Max 5ms). During tE/W, other than status read command is not accepted. Start CS after taking the last data (D0), and before the next SCK clock starts. At other timing, write command is not executed, and this write command is cancelled. This IC has page write function, and after input of data for 1 byte (8 bits), by continuing data input without starting CS , data up to 16 bytes can be written for one tE/W. In page write, the insignificant 4 bit of the designated address is incremented internally at every time when data of 1 byte is input and data is written to respective addresses. When data of the maximum bytes or higher is input, address rolls over, and previously input data is overwritten. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 9/18 2010.10 - Rev.A Technical Note BU9832GUL-W 4. Status register write / read command CS 0 SCK SI SO 0 1 3 2 0 0 0 4 5 0 6 0 0 7 1 8 9 bit 7 bit 6 WP E N ＊ 10 bit 5 ＊ 11 12 bi t4 bit 3 ＊ BP1 13 14 bit 2 BP0 15 bit 1 bit 0 ＊ ＊ High-Z ＊=Don't care Fig.39 Status register write command *1 Write status register command can write status register data. The data can be written by this command are 2 bits , that is, BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be set. As for this command, set CS LOW, and input ope code of write status register, and input data. Then, by making CS HIGH, EEPROM starts writing. Write time requires time of tE/W as same as write. As for CS rise, start CS after taking the last data bit (bit0), and before the next SCK clock starts. At other timing, command is cancelled. Write disable block is determined by BP1 and BP0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array. (Refer to the write disable block setting table.) To the write disabled block, write cannot be made, and only read can be made. *1 3bits including 1WPEN (bit7) CS SCK SI SO 1 0 0 0 2 0 High-Z 3 0 4 0 5 1 7 6 0 8 9 10 11 12 13 14 15 1 bit7 bit6 bit5 bit4 WPEN 0 0 0 bit3 bit2 BP1 BP0 bit1 bit0 WEN R/B Fig.40 Status register read command www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 10/18 2010.10 - Rev.A Technical Note BU9832GUL-W ●At standby ○Current at standby Set CS “H”, and be sure to set SCK, SI, WP , HOLD input “L” or “H”. Do not input intermediate electric potantial. ○Timing As shown in Fig.41, at standby, when SCK is “H”, even if CS is fallen, SI status is not read at fall edge. SI status is read at SCK rise edge after fall of CS . At standby and at power ON/OFF, set CS “H” status. ――― Even if CS is fallen at SCK=SI=”H”, SI status is not read at that edge. ――― CS Command start here. SI is read. SCK 0 1 2 SI Fig.41 Operating timing ● WP cancel valid area WP is normally fixed to “H” or “L” for use, but when WP is controlled so as to cancel write status register command and write command, pay attention to the following WP valid timing. While write or write status register command is executed, by setting WP = “L” in cancel valid area, command can be cancelled. The area from command ope code before CS rise at internal automatic write start becomes the cancel valid area. However, once write is started, any input cannot be cancelled. WP input becomes Don’t Care, and cancellation becomes invalid. SCK 15 16 CS Ope Code tE/W Data write time Data W P cancel invalid area W P cancel invalid area Fig.42 O pe Code WP valid timing (WRSR) D a ta A d d res s WP cancel invalid area Fig.43 tE /W D a ta wr it e tim e WP cancel invalid area WP valid timing (WRITE) ● HOLD pin By HOLD pin, command communication can be stopped temporarily (HOLD status). The HOLD pin carries out command communications normally when it is HIGH. To get in HOLD status, at command communication, when SCK=LOW, set the HOLD pin LOW. At HOLD status, SCK and SI become Don’t Care, and SO becomes high impedance (High-Z). To release the HOLD status, set the HOLD pin HIGH when SCK=LOW. After that, communication can be restarted from the point before the HOLD status. For example, when HOLD status is made after A5 address input at read, after release of HOLD status, by starting A4 address input, read can be restarted. When in HOLD status, leave CS LOW. When it is set CS =HIGH in HOLD status, the IC is reset, therefore communication after that cannot be restarted. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/18 2010.10 - Rev.A Technical Note BU9832GUL-W ●Method to cancel each command ○READ ・Method to cancel : cancel by CS = “H” Ope code Address Data 8 bits 8 bits 8 bits Cancel available in all areas of read mode Fig.44 READ cancel valid timing ○RDSR ・Method to cancel : cancel by CS = “H” Data Ope code 8 bits 8 bits Cancel available in all areas of rdsr mode Fig.45 RDSR cancel valid timing ○WRITE, PAGE WRITE a: Ope code, address input area. Cancellation is available by CS =”H” b: Data input area (D7~D1 input area) Cancellation is available by CS =”H” c: Data input area (D0 area) When CS is started, write starts. After CS rise, cancellation cannot be made by any means. d: tE/W area. Cancellation is available by CS = “H”. However, when write starts ( CS is started) in the area c, cancellation cannot be made by any means. And by inputting on SCK clock, cancellation cannot be made. In page write mode, there is write enable area at every 8 clocks. Note 1) Note 2) Ope code 8bits Data(n) 8bits 8bits a tE/W b d c Fig.46 WRITE cancel valid timing SCK SI D7 D6 D5 D4 D3 D2 D1 D0 c b If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again. If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,therefore, it is necessary to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher. ○WRSR a: From ope code to 15 rise. Cancel by CS =”H”. b: From 15 clock rise to 16 clock rise (write enable area). When CS is started, write starts. After CS rise, cancellation cannot be made by any means. c: After 16 clock rise. Cancel by CS =”H”. However, when write starts ( CS is started) in the area b, cancellation cannot be made by any means. And, by inputting on SCK clock, cancellation cannot be made. Note 1) Note 2) Address 14 SCK D1 SI 16 b c tE/W Address 8 bits 17 D0 a Ope code 15 8 bits a c b Fig.47 WRSR cancel valid timing If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again If CS is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is necessary to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher. ○WREN/WRDI a: From ope code to clock rise, cancel by CS = “H”. b: Cancellation is not available when CS is started after 7 clock. 7 SCK a 8 9 b Ope code 8 bits a b Fig.48 WREN/WRDI cancel valid timing www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 12/18 2010.10 - Rev.A Technical Note BU9832GUL-W ●High speed operation In order to realize stable high speed operations, pay attention to the following input / output pin conditions. ○Input pin pull up, pull down resistance When to attach pull up, pull down resistance to EEPROM input pin, select an appropriate value for the microcontroller VOL, IOL from VIL characteristics of this IC. ○Pull up resistance VCC-VOLM RPU≥ Microcontroller IOLM VOLM≤ EEPROM RPU VOLM VILE “L” output IOLM VILE ･･･① ･･･② Example) When Vcc=5V, VILM=1.5V, VOLM=0.4V, IOLM=2mA, from the equation ①, “L” input 5-0.4 RPU≥ Fig.49 Pull up resistance -3 2×10 ∴RPU≥ 2.3[kΩ] With the value of RPU to satisfy the above equation, VOLM becomes 0.4V or higher, and with VILE (=1.5V), the equation ② is also satisfied. ・VILM :EEPROM VIH specifications ・VOLM :Microcontroller VOL specifications ・IOLM :Microcontroller IOL specifications And, in order to prevent malfunction, mistake write at power ON/OFF, be sure to make CS pull up. ○Pull down resistance VOHM VOHM RPD≥ EEPROM IOHM ･･･③ VIHE ･･･④ VIHE VOHM≥ IOHM Example) When VCC=5V, VOHM=VCC-0.5V, IOHM=0.4mA, VIHM=VCC×0.7V, from the equation③, Fig.50 Pull down resistance 5-0.5 RPD≥ 0.4×10-3 ∴RPU≥ 11.3[kΩ] Further, by amplitude VIHE, VILE of signal input to EEPROM, operation speed changes. By inputting signal of amplitude of VCC / GND level to input, more stable high speed operations can be realized. On the contrary, when amplitude of 0.8VCC ж1 / 0.2Vcc is input, operation speed becomes slow. In order to realize more stable high speed operation, it is recommended to make the values of RPU, RPD as large as possible, and make the amplitude of signal input to EEPROM close to the amplitude of VCC / GND level. (ж1 At this moment, operating timing guaranteed value is guaranteed.) tPD_VIL characteristics 80 Spec 70 60 tPD[ns] 50 40 30 Vcc=2.5V 20 Ta=25℃ VIH=Vcc CL =100pF 10 0 0 0.2 0.4 0.6 0.8 1 VIL[V] Fig.51 VIL dependency of data output delay time www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/18 2010.10 - Rev.A Technical Note BU9832GUL-W ○SO load capacity condition Load capacity of SO output pin affects upon delay characteristic of SO output. (Data output delay time, time from HOLD to High-Z) In order to make output delay characteristic into higher speed, make SO load capacity small. In concrete, “Do not connect many devices to SO bus”, “Make the wire between the controller and EEPROM short”, and so forth. tPD-CL characteristics 80 Vcc=2.5V Ta=25℃ Spec VIH/VIL=0.8Vcc/0.2Vcc 70 EEPROM tPD[ns] 60 Spec SO 50 CL 40 30 20 0 20 40 60 80 100 120 CL[pF] Fig.52 SO load dependency of data output delay time ○Other cautions Make the wire length from the microcontroller to EEPROM input signal same length, in order to prevent setup / hold violation to EEPROM, owing to difference of wire length of each input. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 14/18 2010.10 - Rev.A Technical Note BU9832GUL-W ●Equivalent circuit ○Output circuit SO OEint. Fig.53 SO output equivalent circuit ○Input circuit RESETint. ――― CS Fig.54 CS input equivalent circuit SCK SI Fig.55 SCK input equivalent circuit Fig.56 SI input equivalent circuit ――― ―――――― HOLD WP Fig.58 WP input equivalent circuit Fig.57 HOLD input equivalent circuit www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 15/18 2010.10 - Rev.A Technical Note BU9832GUL-W ●Notes on power ON/OFF ○At power ON/OFF, set CS “H” (=Vcc). When CS is “L”, this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause malfunction, mistake write or so. To prevent these, at power ON, set CS “H”. (When CS is in “H” status, all inputs are canceled.) Vcc Vcc GND Vcc CS GND Good example Bad example Fig.59 CS timing at power ON/OFF (Good example) (Bad example) CS terminal is pulled up to Vcc. At power OFF, take 10ms or higher before supply. If power is turned on without observing this condition, the IC internal circuit may not be reset, which please note. CS terminal is “L” at power ON/OFF. In this case, CS always becomes “L” (active status), and EEPROM may have malfunction, mistake write owing to noises and the likes. Even when CS input is High-Z, the status becomes like this case, which please note. ○P.O.R. circuit This IC has a P.O.R. (Power On Reset) circuit as mistake write countermeasure. After P.O.R. action, it gets in write disable status. The P.O.R. circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the recommended conditions of the following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to noises and the likes. tR Vcc Recommended conditions of tR, tOFF, Vbot tOFF 0 Vbot tR tOFF Vbot 10ms or below 10ms or higher 0.3V or below 100ms or below 10ms or higher 0.2V or below Fig.60 Rise waveform ●Noise countermeasures ○Vcc noise (bypass capacitor) When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a bypass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND. ○SCK noise When the rise time (tR) of SCK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement. To avoid this, a Schmitt trigger circuit is built in SCK input. The hysterisis width of this circuit is set about 0.2V, if noises exist at SCK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR) of SCK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall time as small as possible. ○ WP noise During execution of write status register command, if there exist noises on WP pin, mistake in recognition may occur and forcible cancellation may result, which please note. To avoid this, a Schmitt trigger circuit is built in WP input. In the same manner, a Schmitt trigger circuit is built in SI input, SI input and HOLD input too. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 16/18 2010.10 - Rev.A Technical Note BU9832GUL-W ●Notes for use (1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is higher than that of GND terminal. (5) Heat design In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal short circuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of short circuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 17/18 2010.10 - Rev.A Technical Note BU9832GUL-W ●Ordering part number B U Part No. 9 8 3 2 Part No. G U L Package GUL : VCSP50L2 - W W-CELL E 2 Packaging and forming specification E2: Embossed tape and reel VCSP50L2(BU9832GUL-W) <Tape and Reel information> 0.08 S 8- φ 0.25±0.05 0.05 A B A (φ0.15)INDEX POST B C B A 1 0.545±0.1 2 0.55MAX S Embossed carrier tape Quantity 3000pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) P=0.5×2 2.09±0.1 Tape 0.425±0.1 0.1±0.05 1.85±0.1 1PIN MARK 3 P=0.5×2 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1pin (Unit : mm) Reel 18/18 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2010.10 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. 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If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. R1010A