Download

PT6392
64-Bit VFD Driver IC
DESCRIPTION
PT6392 is a Vacuum Fluorescent Display (VFD) Driver
utilizing CMOS Technology. It supports 64 High
Voltage Output Ports. It utilizes serial data interface
and the data can be shifted in both directions. It is
housed in CIG (Chip-In-Glass) package.
FEATURES




CMOS technology
Serial data interface
No external resistor needed for driver output
Available in CIG and LQFP package
APPLICATION

Peripheral device
BLOCK DIAGRAM
Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, No. 233-1, Baociao Rd., Sindian Dist., New Taipei City 23145, Taiwan
PT6392
APPLICATION CIRCUITS
SINGLE VFD APPLICATION (ASSUME FR= “LOW-LEVEL”)
Note:
VH=External supply voltage (Maximum voltage=80V)
V1.1
2
June 2014
PT6392
CASCADE VFD APPLICATION (ASSUME FR=“LOW-LEVEL”)
Note:
VH=External supply voltage (Maximum voltage=80V)
V1.1
3
June 2014
PT6392
ORDER INFORMATION
Valid Part Number
PT6392
Package Type
-
Top Code
-
PT6392-LQ
80-Pin, LQFP
PT6392-LQ
PIN CONFIGURATION
80 PINS LQFP
V1.1
4
June 2014
PT6392
CIG
V1.1
5
June 2014
PT6392
PIN DESCRIPTION
Pin Name
I/O
Q1~Q64
O
Driver Output Pins (Push-Pull Output)
PGND
-
Driver Power Ground Pin
VH
-
Driver Power Supply
B
A
I/O
I/O
CLK
I
LGND
FR
I
VDD
-
LAT
I
TEST
I
BK
I
Description
Package
Pin No.
78~80
1~20
22~39
42~64
21, 41
66, 76
16~39
42~59
62~85
67
68
3, 13
40, 61
1, 15
41, 60
4
5
69
6
70
7
71
8
72
9
73
10
74
11
75
12
65, 40, 77
Serial Data Input/Output Pins
Serial Data Input/Output Pins
Shift Register Clock Input Pins
The serial data is latched into shift register at the rising edge of CLK
Logic Power Ground Pin
Shift Register Directional Input Pins
- When this pin is low-level, B pin acts as output pin and A pin as input.
The right shift mode is action:
AQ1Q2…Q63Q64B
- When this pin is high-level or floating, B pin acts as input pin and A pin
as output.
The Left shift mode is action:
BQ64Q63…Q2Q1A
- See “Shift Register Truth Table” for more information
Logic Power Supply
Latch Input Pin
64-bit shift register data is outputted at LAT high level and latched at
falling edge of LAT
Test Pin
When BK pin and this pun are set to low level, all drivers output are set to
high level and all lights are turned on. Under normal conditions, this pin
must be set to “H” or floating.
Blanking Input Pins
- When this pin is set to “H” or floating, the driver pin is set to “L”
- See “Latch and Driver Truth Table” for more information
Chip
Pad No.
Notes:
1. Be sure to use all the VDD, VH, LGND, and PGND pins. Keep the LGND and PGND pins at same voltage level.
2. Supply power to VDD logic input and VH driver power in this order to protect the driver destruction due to latch up. Turn off power in the reserve
order. Power ON. OFF sequences must be observed at all times, even during the transition period.
V1.1
6
June 2014
PT6392
IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.
Princeton Technology Corp.
2F, 233-1, Baociao Road,
Sindian Dist., New Taipei City 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw
V1.1
20
June 2014