NEC UPD16344

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16344
64-BIT AC-PDP DRIVER
DESCRIPTION
The µ PD16344 is a row driver for an AC plasma display panel (PDP) using high breakdown voltage CMOS
process. The µ PD16344 consists of a 64-bit bi-directional shift register, latch circuit and high breakdown voltage
CMOS driver section. The logic section operates on a 5-V power supply so that it can be connected directly to a gate
array and microcomputer (CMOS level input). The driver section provides high breakdown voltage output of 120 V
and +400 mA, −150 mA. Both the logic and driver sections are constructed by CMOS, witch allows operation with
low power consumption.
FEATURES
• High voltage full CMOS process
• High breakdown voltage, high current output (Maximum rating: 120 V, +400 mA, −150 mA)
• 64-bit bi-directional shift register on chip
• Data control by transfer clock (external) and latch
• High-speed data transfer capability (fCLK = 12 MHz MAX.: when cascaded)
• Wider operating ambient temperature (TA = −40°C to 85°C)
ORDERING INFORMATION
Part number
Package
µ PD16344GF-3BA
100-pin plastic QFP(14 x 20)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14575EJ2V0DS00 (2nd edition)
Date Published November 2000 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
1999, 2000
µ PD16344
1. BLOCK DIAGRAM (Shift register: 64-bit)
/OE
/LBLK
HBLK
LE1
VDD2
LE2
A
CLK
A
SR
DA
LE1, LE2
S1
S1
S2
S2
CLR S3
S3
S4
S4
S61
S61
S62
S62
S63
S63
S64
S64
O1
L1
CLK
VSS2
/CLR
DK
B
VDD2
DA
O64
L64
B
VSS2
SR: 64-bit shift register
DK
Remark /xxx indicates active low signal.
2
Data Sheet S14575EJ2V0DS
µ PD16344
2. PIN CONFIGURATION (Top view)
51
DK2
DA2
VSS2
VDD2
LE2
R,/L
VSS1
CLK
LE1
B
VDD1
A
/CLR
/LBLK
HBLK
/OE
VDD2
VSS2
DA1
31
O1
50
DK1
µ PD16344GF-3BA
30
O64
O63
O3
O62
O4
O61
O5
O60
O6
O59
O7
O58
O8
O57
O9
O56
O10
O55
O11
O54
O12
O53
O13
O52
O14
O51
O15
O50
O16
O49
O17
O48
O18
O47
O19
O46
O20
O45
O21
O44
O22
O43
O23
O42
O24
O41
O25
O40
O26
O39
O27
O38
O28
O37
O29
O36
1
O35
O34
O33
DA2
DK2
DA2
VSS2
VDD2
VSUB
VSS1
VSUB
VDD1
VSUB
VSUB
VSS2
VDD2
DA1
DA1
DK1
O32
81
80
O31
O30
100
O2
Caution Be sure to use all of the VDD1, VDD2, VSS1, and VSS2 pins. Use VSS1, VSS2, and VSUB at the
same potential.
Data Sheet S14575EJ2V0DS
3
µ PD16344
3. PIN FUNCTIONS
Pin Symbol
Pin Name
Pin Number
HBLK
High blanking input
45
LE1, LE2
Latch strobe input
35, 39
Description
All output = H, when HBLK = H
L = Through, H = Data preservation
LE1: Latch of odd register
LE2: Latch of even register
A
Left data input
42
When R,/L = L: A: Input
B: Output
B
Right data input
40
When R,/L = H: A: Output
B: Input
CLK
Clock input
38
Shift performed on a rising edge
/OE
Enable input
46
L = All output, high-impedance
/LBLK
Low blanking input
44
All output = L, when /LBLK = L
R,/L
Shift control input
36
/CLR
Register clear
O1 to O64
High withstand voltage output
43
1 to 30, 51 to 82,
L = Left shift mode
A → O1 … O64 → B
H = Right shift mode
B → O64 … O1 → A
L = All shift register data cleared (L level clear)
110 V, +300 mA, −100 mA
99, 100,
4
DA1
Diode source 1
49, 84, 85
DK1
Diode sink 1
DA2
Diode source 2
DK2
Diode sink 2
31, 98
Diode sink pin for O33 to O64
VDD1
Logic section power supply
41, 90
5 V ± 10 %
VDD2
Driver section power supply
34, 47, 87, 94
VSS1
Logic ground
37, 91
Connected to system GND
VSS2
Driver ground
33, 48, 86, 95
Connected to system GND
VSUB
Substrate ground
88, 89, 92, 93
Connected to system GND
50, 83
32, 96, 97
Diode source pin for O1 to O32
Diode sink pin for O1 to O32
Diode source pin for O33 to O64
30 to 110 V
Data Sheet S14575EJ2V0DS
µ PD16344
4. TRUTH TABLE
Shift Register Section
Input
Output
/CLR
R,/L
CLK
A
L
↑
Input
L
H or L
↑
H
H or L
Output
×
×
×
Output
Output
Note1
H
Left shift operation performed
Output
H
Hold
Input
H
Right shift operation performed
H
Hold
L
All registers = L
Note2
H
Shift Register
B
×
Notes 1. On the rising edge of the clock, the data of S63 is shifted to S64, and data is output from B.
2. On the rising edge of the clock, the data of S2 is shifted to S1, and data is output from A.
Latch Section
LE
Operation (Ln)
H
Holds and outputs data immediately before LE becomes H.
L
Outputs shift register data.
Driver Section
A (B)
HBLK
/LBLK
/OE
/CLR
Driver Output State
×
H
H
H
×
All driver output: H
×
×
L
H
×
All driver output: L
×
×
×
L
×
All driver output: High impedance
L
L
H
H
H
H
H
L
H
H
H
L
×
L
H
H
L
H
Note
Note The capacity of the Nch transistor decreases to about 1/4 of the normal state for a certain period of time at the
falling edge of /LBLK. Refer to Switching Characteristics Waveform on 8. ELECTRICAL SPECIFICATIONS.
Remark ×: H or L, H: High level, L: Low level
Data Sheet S14575EJ2V0DS
5
µ PD16344
5. TIMING CHART (R,/L =“L”, when left shift mode)
1
2
3
4
5
6
7
8
CLK
A (B)
/CLR
LE1,2
HBLK
/LBLK
/OE
S1 (S64)
S2 (S63)
S3 (S62)
S4 (S61)
S5 (S60)
S6 (S59)
S63 (S2)
S64 (S1)
B (A)
O1 (O64)
O2 (O63)
O3 (O62)
O4 (O61)
O63 (O2)
O64 (O1)
Remark In the parentheses: when R,/L=H
6
Data Sheet S14575EJ2V0DS
63
64
65
66
67
68
69
70
71
µ PD16344
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Ratings
Unit
Logic section supply voltage
VDD1
−0.5 to +6.0
V
Driver section supply voltage
VDD2
−0.5 to +120
V
Logic section input voltage
VI
−0.5 to VDD1 + 0.5
V
+400, −150
Note
Driver section output current
IO
Diode peak forward current
IFM
±450
mA
Allowed package loss
PD
1000
mW
Operating ambient temperature
TA
−40 to +85
°C
Storage temperature
Tstg
−65 to +150
°C
Note
mA
Simultaneous operation can be performed with up to 4 outputs.
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operation Ranges (TA = −40 to +85°°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
5.0
5.5
V
Logic section supply voltage
VDD1
4.5
Driver section supply voltage
VDD2
30
110
V
High-level input voltage
VIH
0.7 VDD1
VDD1
V
Low-level input voltage
VIL
0
0.2 VDD1
V
Driver output current
IOH
−100
mA
+300
mA
(+75)
mA
IFOH
−400
mA
IFOL
+400
mA
IOL1
IOL2
Diode forward current
Low capacity
Note
Note The period of 560 ns MAX. from the falling edge of /LBLK. The value enclosed in parentheses is a reference
value.
Data Sheet S14575EJ2V0DS
7
µ PD16344
Electrical Characteristics (TA = 25°°C, VDD1 = 4.5 to 5.5 V, VDD2 = 110 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
0.9 VDD1
VDD1
V
0.1 VDD1
V
High-level output voltage
VOH1
Logic, IOH = −1.0 mA
Low-level output voltage
VOL1
Logic, IOL = 1.0 mA
0
High-level output voltage
VOH2
O1 to O64, IOH = −60 mA
90
Low-level output voltage
VOL21
O1 to O64, IOL = 200 mA
VOL22
High-level output voltage
VOHD
Low capacity
Note1
, IOL = 50 mA
O1 to O64, IOH = −400 mA
Note2
,
103
TYP.
100
V
4
8
V
(4)
(8)
V
105
V
DA = 110 V
Low-level output voltage
VOLD
O1 to O64, IOL = 400 mA
Note2
,
5
7
V
±1.0
µA
DK = 0 V
Input leakage current
IIL
High-level input voltage
VIH
Low-level input voltage
VIL
Static current consumption
IDD11
VI = VDD1 or VSS1
0.7 VDD1
V
0.2 VDD1
V
Logic, TA = −40 to +85°C
500
µA
IDD11
Logic, TA = 25°C
300
µA
IDD21
Driver, TA = −40 to +85°C
1000
µA
IDD21
Driver, TA = 25°C
100
µA
Notes 1. The period of 560 ns MAX. from the falling edge of /LBLK. The value enclosed in parentheses is a
reference value.
2. The current characteristic of the diode built into the output section is indicated.
8
Data Sheet S14575EJ2V0DS
µ PD16344
Switching Characteristics (TA = 25°°C, VDD1 = 4.5 to 5.5 V, VDD2 = 110 V, Logic CL = 15 pF, Driver CL = 50 pF)
Parameter
Propagation delay time
Symbol
tPHL1
Conditions
MIN.
TYP.
CLK → A, B
tPLH1
★
Unit
70
ns
70
ns
tPHL2
/CLR → A, B
70
ns
tPHL3
CLK → O1 to O64
160
ns
160
ns
160
ns
160
ns
160
ns
160
ns
200
ns
200
ns
tPLH3
tPHL4
LE → O1 to O64
tPLH4
tPHL5
HBLK → O1 to O64
tPLH5
tPHL6
/LBLK → O1 to O64
tPLH6
tPHZ
/OE → O1 to O64
300
ns
tPZH
RL = 20 kΩ
160
ns
tPZL
160
ns
tPLZ
300
ns
150
ns
100
ns
400
ns
Output rising time
tTLH
O1 to O64
Output falling time
tTHL1
O1 to O64
tTHL2
Output Nch low-driver
MAX.
Low capacity
Note1
Note2
(280)
(560)
Note2
tLA
from the falling edge of /LBLK
ns
fCLK
Data intake, Duty = 50%
15
MHz
Cascade connection, Duty = 50%
12
MHz
15
pF
MAX.
Unit
capability period
Clock frequency
Input capacity
CI
Notes 1. The period of 560 ns MAX. from the falling edge of /LBLK.
2. The value enclosed in parentheses is a reference value.
Timing Requirements (TA = −40 to +85°°C, VDD1 = 4.5 to 5.5 V, VSS1 = VSS2 = 0 V)
Parameter
Clock pulse width
Symbol
Conditions
PWCLK(H),
MIN.
TYP.
30
ns
PWCLK(L)
Latch enable pulse width
PWLE
30
ns
Blank pulse width
PWHBLK
300
ns
PW/LBLK
600
ns
Clear pulse width
PW/CLR
30
ns
Data setup time
tsetup
10
ns
Data hold time
thold
10
ns
Clock latch time
tCLK-LE
30
ns
CLK ↑ → LE ↑
Data Sheet S14575EJ2V0DS
9
µ PD16344
Switching Characteristics Waveform (1/3)
1/fCLK
PWCLK (H)
PWCLK (L)
VDD1
50%
50%
50%
CLK
VSS1
tSETUP
A/B
(input)
tHOLD
VDD1
50%
50%
VSS1
tPHL1
tPLH1
VOH1
B/A
(output)
50%
50%
VOL1
tPHL3
tTHL1
90%
10%
On
tPLH3
tTLH
90%
10%
VOH2
VOL2
VDD1
/CLR
50%
VSS1
tPHL2
VOH1
★
B/A
(output)
50%
VOL1
10
Data Sheet S14575EJ2V0DS
µ PD16344
Switching Characteristics Waveform (2/3)
VDD1
50%
CLK
VSS1
tCLK-LE
PWLE
VDD1
50%
50%
LE
VSS1
tPHL4
VOH2
90%
On
VOL2
tPLH4
VOH2
10%
On
VOL2
PWHBLK
VDD1
HBLK
50%
50%
VSS1
tPLH5
tPHL5
90%
10%
On
VOH2
VOL2
PW/LBLK
VDD1
/LBLK
50%
tPHL6
50%
tTHL2
tPLH6
VOH2
90%
On
tLA
10%
Data Sheet S14575EJ2V0DS
10%
VOL2
11
µ PD16344
Switching Characteristics Waveform (3/3)
VDD1
/OE
50%
50%
VSS1
tPLZ
tPZL
VOH2
90%
On
10%
VOL2
VOH2
90%
10%
On
tPHZ
12
tPZH
Data Sheet S14575EJ2V0DS
VOL2
µ PD16344
8. PACKAGE DRAWING
100 PIN PLASTIC QFP (14x20)
A
B
51
50
80
81
detail of lead end
S
C D
R
Q
31
30
100
1
F
G
H
I
J
M
P
K
M
N
S
NOTE
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
L
S
ITEM
A
MILLIMETERS
23.2±0.2
B
20.0±0.2
C
14.0±0.2
D
17.2±0.2
F
0.8
G
H
0.6
0.32±0.08
I
0.15
J
0.65 (T.P.)
K
L
1.6±0.2
0.8±0.2
M
0.17 +0.08
−0.07
N
0.10
P
Q
R
S
2.7
0.125±0.075
5°±5°
2.825±0.175
S100GF-65-3BA-4
Data Sheet S14575EJ2V0DS
13
µ PD16344
★ 9. SOLDERING CONDITIONS
Solder the product under the following recommended conditions.
For details of the recommended soldering conditions, refer to information Document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and soldering conditions other than those recommended, please contact one of our sales
representatives.
Surface Mount Type
µ PD16344GF-3BA: 100-pin plastic QFP(14 x 20)
Soldering
Soldering Condition
Method
Infrared reflow
Symbol of Recommended
Soldering Condition
Package peak temperature: 235°C, Time: 30 seconds MAX. (210°C MIN.),
IR35-207-3
Number of times: 3 MAX., Max day: 7 days (need 10 hours with 125°C prebeak after limited day)
<Precaution>
Products other than in hear-resistant trays (such as those packaged in a
magazine, taping, or non-thermal-resistant tray) cannot be baked in their
package.
VPS
Package peak temperature: 215°C, Time: 40 seconds MAX. (200°C MIN.),
VP15-207-3
Number of times: 3 MAX., Max day: 7 days (need 10 hours with 125°C prebeak after limited day)
<Precaution>
Products other than in hear-resistant trays (such as those packaged in a
magazine, taping, or non-thermal-resistant tray) cannot be baked in their
package.
Partial heating
Pin temperature: 300°C MAX., Time: 3seconds MAX. (per side of device)
–
Caution Do not use two or more soldering methods in combination (except the partial heating method).
14
Data Sheet S14575EJ2V0DS
µ PD16344
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S14575EJ2V0DS
15
µ PD16344
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades to NEC’s Semiconductor Devices (C11531E)
• The information in this document is current as of November, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4