LM48821 Direct Coupled, Ultra Low Noise, 52mW Differential Input Stereo Headphone Amplifier with I2C Volume Control General Description Key Specifications With its directly-coupled output technology, the LM48821 is a variable gain audio power amplifier capable of delivering 52mWRMS per channel into a 16Ω single-ended load with less than 1% THD+N from a 3V power supply. The I2C volume control has a range of –76dB to 18dB. The LM48821's Tru-GND technology utilizes advanced charge pump technology to generate the LM48821’s negative supply voltage. This eliminates the need for output-coupling capacitors typically used with single-ended loads. Boomer audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. The LM48821 does not require output coupling capacitors or bootstrap capacitors, and therefore is ideally suited for mobile phone and other low voltage applications where minimal power consumption is a primary requirement. The LM48821 incorporates selectable low-power consumption shutdown and channel select modes. The LM48821 contains advanced output transient suppression circuitry that eliminates noises which would otherwise occur during turn-on and turn-off transitions. ■ Improved PSRR at 217Hz 82dB (typ) ■ Stereo Output Power at VDD = 3V, RL = 16Ω, THD+N = 1% 52mW (typ) ■ Mono Output Power at VDD = 3V, RL = 16Ω, THD+N = 1% ■ Shutdown current 93mW (typ) 0.1μA (typ) Features ■ ■ ■ ■ ■ ■ Ground referenced outputs Differential Inputs I2C Volume and mode controls Available in space-saving micro SMD package Ultra low current shutdown mode Advanced output transient suppression circuitry eliminates noises during turn-on and turn-off transitions ■ 2.0V to 4.0V operation (PVDD and SVDD) ■ 1.8 to 4.0V operation (I2CVDD) ■ No output coupling capacitors, snubber networks, bootstrap capacitors, or gain-setting resistors required Applications ■ ■ ■ ■ ■ ■ Notebook PCs Desktop PCs Mobile Phones PDAs Portable Electronic Devices MP3 Players Boomer® is a registered trademark of National Semiconductor Corporation. Tru-GND is a trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 201842 www.national.com LM48821 Direct Coupled, Ultra Low Noise, 52mW Differential Input Stereo Headphone Amplifier with I2C Volume Control June 2007 LM48821 Typical Application 20184211 FIGURE 1. Typical Audio Amplifier Application Circuit www.national.com 2 LM48821 Connection Diagrams micro SMD Package micro SMD Marking 201842d7 Top View Order Number TLA1611A See NS Package Number TLA1611A 201842d8 Top View XY - Date Code TT - Lot Traceability GG3 – LM48821 Pin Descriptions Pin Designator Pin Name Pin Function A1 SVDD Signal power supply input A2 SGND Signal ground A3 IN A+ Left non-inverting input A4 IN A- Left inverting input B1 VOA Left output B2 VOB Right output B3 IN B+ Right non-inverting input B4 IN B- Right inverting input C1 VSS DC to DC converter output C2 SCL I2C serial clock input C3 SDA I2C serial data input C4 I2CVDD I2C supply voltage input D1 CCP- D2 PGND DC to DC converter flying capacitor inverting input D3 CCP+ DC to DC converter flying capacitor non-inverting input D4 PVDD DC to DC converter power supply input Power ground 3 www.national.com LM48821 Thermal Resistance Absolute Maximum Ratings (Notes 1, 2) θJA (typ) - (TLA1611A) (Note 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Storage Temperature Input Voltage Power Dissipation (Note 3) ESD Susceptibility (Note 4) ESD Susceptibility (Note 5) Junction Temperature 105°C/W Operating Ratings Temperature Range 4.5V −65°C to +150°C −0.3V to VDD +0.3V Internally Limited 2000V 200V 150°C TMIN ≤ TA ≤ TMAX Supply Voltage PVDD and SVDD −40°C ≤ TA ≤ +85°C 2.0V ≤ VDD ≤ 4.0V 1.8V ≤ I2CVDD ≤ 4.0V I2CVDD Audio Amplifier Electrical Characteristics VDD = 3V (Notes 1, 2) The following specifications apply for VDD = 3V, RL = 16Ω, AV = 0dB, unless otherwise specified. Limits apply for TA = 25°C. LM48821 Symbol IDD Parameter Quiescent Power Supply Current Conditions Units (Limits) Typical (Note 6) Limits (Notes 7, 8) VIN = 0V, inputs terminated, both channels enabled 3.0 4.5 mA (max) VIN = 0V, inputs terminated, one channel enabled 2.0 3.0 mA 0.1 1.2 µA (max) 2.5 mV (max) ISD Shutdown Current Right and Left Enable bits set to 0 VOS Output Offset Voltage RL = 32Ω 0.5 [B0:B4] = 00000 –76 dB +18 dB ±0.015 dB AV Volume Control Range ΔAV Channel-to-Channel Gain Match AV-MUTE Mute Gain RIN Input Resistance [B0:B4] = 11111 –76 Gain = 18dB 9 Gain = –76dB 81 THD+N = 1% (max); fIN = 1kHz, RL = 16Ω, per channel THD+N = 1% (max); fIN = 1kHz, POUT Output Power RL = 32Ω, per channel THD+N = 1% (max); fIN = 1kHz, RL = 16Ω, single channel driven THD+N = 1% (max); fIN = 1kHz, RL = 32Ω, single channel driven POUT = 50mW, f = 1kHz THD+N Total Harmonic Distortion + Noise RL = 16Ω, single channel POUT = 50mW, f = 1kHz RL = 32Ω, single channel dB 5 15 kΩ (min) kΩ (max) kΩ 52 43 mW (min) 53 45 mW (min) 93 80 mW (min) 79 mW 0.022 % 0.011 % VRIPPLE = 200mVP-P, input referred f = 217Hz f = 1kHz f = 20kHz 82 80 55 Common Mode Rejection Ratio VRIPPLE = 200mVp-p, Input referred f = 2kHz 65 dB SNR Signal-to-Noise-Ratio RL = 32Ω, POUT = 20mW, f = 1kHz, BW = 20Hz to 22kHz 100 dB TWU Charge Pump Wake-Up Time 400 μs PSRR Power Supply Rejection Ratio CMRR www.national.com 4 65 dB (min) dB dB Parameter Conditions Typical (Note 6) Limits (Notes 7, 8) Units (Limits) XTALK Crosstalk RL = 16Ω, POUT = 1.6mW, f = 1kHz, A-weighted filter 82 dB ZOUT Output Impedance Right and Left Enable bits set to 0 41 kΩ Control Interface Electrical Characteristics (Notes 1, 2) The following specifications apply for 1.8V ≤ I2CVDD ≤ 4.0V, unless otherwise specified. Limits apply for TA = 25°C. See Figure 2. LM48821 Symbol Parameter Conditions Typical (Note 6) Limits (Notes 7, 8) Units (Limits) t1 SCL period 2.5 μs (min) t2 SDA Setup Time 100 ns (min) t3 SDA Stable Time 0 ns (min) t4 Start Condition Time 100 ns (min) t5 Stop Condition Time 100 ns (min) I2CV VIH Logic High Input Threshold 0.7 x DD V (min) VIL Logic Low Input Threshold 0.3 x I2CVDD V (max) Note 1: All voltages are measured with respect to the GND pin unless otherwise specified. Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM48821, see power derating currents for more information. Note 4: Human body model, 100pF discharged through a 1.5kΩ resistor. Note 5: Machine Model, 220pF - 240pF discharged through all pins. Note 6: Typicals are measured at +25°C and represent the parametric norm. Note 7: Limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 8: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. 5 www.national.com LM48821 LM48821 Symbol LM48821 Typical Performance Characteristics THD+N vs Frequency VDD = 2V, PO = 6mW, RL = 16Ω, Stereo THD+N vs Frequency VDD = 2V, PO = 10mW, RL = 32Ω, Stereo 20184233 20184232 THD+N vs Frequency VDD = 2V, PO = 16mW, RL = 16Ω, Mono Left THD+N vs Frequency VDD = 2V, PO = 16mW, RL = 16Ω, Mono Right 20184234 20184235 THD+N vs Frequency VDD = 2V, PO = 18mW, RL = 32Ω, Mono Left THD+N vs Frequency VDD = 2V, PO = 18mW, RL = 32Ω, Mono Right 20184236 www.national.com 20184237 6 LM48821 THD+N vs Frequency VDD = 3V, PO = 35mW, RL = 16Ω, Stereo THD+N vs Frequency VDD = 4V, PO = 50mW, RL = 16Ω, Stereo 20184238 20184239 THD+N vs Frequency VDD = 3V, PO = 70mW, RL = 16Ω, Mono Left THD+N vs Frequency VDD = 3V, PO = 70mW, RL = 16Ω, Mono Right 201842b9 201842c0 THD+N vs Frequency VDD = 4V, PO = 160mW, RL = 16Ω, Mono Left THD+N vs Frequency VDD = 4V, PO = 160mW, RL = 16Ω, Mono Right 201842c2 201842c1 7 www.national.com LM48821 THD+N vs Frequency VDD = 3V, PO = 40mW, RL = 32Ω, Stereo THD+N vs Frequency VDD = 3V, PO = 60mW, RL = 32Ω, Mono Left 201842c4 201842c3 THD+N vs Frequency VDD = 3V, PO = 60mW, RL = 32Ω, Mono Right THD+N vs Frequency VDD = 4V, PO = 90mW, RL = 32Ω, Stereo 201842c5 201842c6 THD+N vs Frequency VDD = 4V, PO = 120mW, RL = 32Ω, Mono Left THD+N vs Frequency VDD = 4V, PO = 120mW, RL = 32Ω, Mono Right 201842c8 201842c7 www.national.com 8 LM48821 THD+N vs Output Power VDD = 2V, RL = 16Ω, f = 1kHz, Mono Left THD+N vs Output Power VDD = 2V, RL = 16Ω, f = 1kHz, Mono Right 20184240 20184241 THD+N vs Output Power VDD = 2V, RL = 16Ω, f = 1kHz, Stereo THD+N vs Output Power VDD = 3V, RL = 16Ω, f = 1kHz, Mono Left 20184242 20184243 THD+N vs Output Power VDD = 3V, RL = 16Ω, f = 1kHz, Mono Right THD+N vs Output Power VDD = 3V, RL = 16Ω, f = 1kHz, Stereo 20184244 20184245 9 www.national.com LM48821 THD+N vs Output Power VDD = 4V, RL = 16Ω, f = 1kHz, Mono Left THD+N vs Output Power VDD = 4V, RL = 16Ω, f = 1kHz, Mono Right 20184246 20184247 THD+N vs Output Power VDD = 4V, RL = 16Ω, f = 1kHz, Stereo THD+N vs Output Power VDD = 2V, RL = 32Ω, f = 1kHz, Mono Left 20184248 20184299 THD+N vs Output Power VDD = 2V, RL = 32Ω, f = 1kHz, Mono Right THD+N vs Output Power VDD = 2V, RL = 32Ω, f = 1kHz, Stereo 20184249 www.national.com 20184250 10 LM48821 THD+N vs Output Power VDD = 3V, RL = 32Ω, f = 1kHz, Mono Left THD+N vs Output Power VDD = 3V, RL = 32Ω, f = 1kHz, Mono Right 20184251 20184252 THD+N vs Output Power VDD = 3V, RL = 32Ω, f = 1kHz, Stereo THD+N vs Output Power VDD = 4V, RL = 32Ω, f = 1kHz, Mono Left 20184254 20184253 THD+N vs Output Power VDD = 4V, RL = 32Ω, f = 1kHz, Mono Right THD+N vs Output Power VDD = 4V, RL = 32Ω, f = 1kHz, Stereo 20184255 20184256 11 www.national.com LM48821 CMRR vs Frequency VDD = 3V, RL = 16Ω PSRR vs Frequency VDD = 2V, RL = 16Ω 20184226 201842d9 PSRR vs Frequency VDD = 2V, RL = 32Ω PSRR vs Frequency VDD = 3V, RL = 16Ω 20184227 20184228 PSRR vs Frequency VDD = 3V, RL = 32Ω PSRR vs Frequency VDD = 4V, RL = 16Ω 20184229 www.national.com 20184230 12 LM48821 PSRR vs Frequency VDD = 4V, RL = 32Ω Output Power vs Voltage Supply RL = 16Ω, Mono 20184231 20184212 Output Power vs Voltage Supply RL = 32Ω, Mono Output Power vs Voltage Supply RL = 16Ω, Stereo 20184213 20184216 Output Power vs Voltage Supply RL = 32Ω, Stereo Output Power vs Power Dissipation VDD = 2V, 3V, 4V, RL = 16Ω, Mono 20184217 20184214 13 www.national.com LM48821 Output Power vs Power Dissipation VDD = 2V, 3V, 4V, RL = 32Ω, Mono Output Power vs Power Dissipation VDD = 2V, 3V, 4V, RL = 16Ω, Stereo 20184215 20184218 Output Power vs Power Dissipation VDD = 2V, 3V, 4V, RL = 32Ω, Stereo Supply Current vs Supply Voltage Mono 20184209 20184219 Supply Current vs Supply Voltage Stereo 20184210 www.national.com 14 LM48821 Application Information 20184267 FIGURE 2. I2C Timing Diagram 20184268 FIGURE 3. I2C Bus Format TABLE 1. Chip Address Chip Address D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 1 1 0 0 TABLE 2. Control Registers D7 Volume Control VD4 D6 VD3 D5 VD2 15 D4 VD1 D3 VD0 D2 D1 D0 MUTE LF ENABLE RT ENABLE www.national.com LM48821 I2C VOLUME CONTROL The LM48821 can be configured in 32 different gain steps by forcing I2C volume control bits to a desired gain according to the table below: TABLE 3. Volume Control VD4 VD3 VD2 VD1 VD0 Gain (dB) 0 0 0 0 0 –76 0 0 0 0 1 –62 0 0 0 1 0 –52 0 0 0 1 1 –44 0 0 1 0 0 –38 0 0 1 0 1 –34 0 0 1 1 0 –30 0 0 1 1 1 –27 0 1 0 0 0 –24 0 1 0 0 1 –21 0 1 0 1 0 –18 0 1 0 1 1 –16 0 1 1 0 0 –14 0 1 1 0 1 –12 0 1 1 1 0 –10 0 1 1 1 1 –8 1 0 0 0 0 –6 1 0 0 0 1 –4 1 0 0 1 0 –2 1 0 0 1 1 0 1 0 1 0 0 2 1 0 1 0 1 4 1 0 1 1 0 6 1 0 1 1 1 8 1 1 0 0 0 10 1 1 0 0 1 12 1 1 0 1 0 13 1 1 0 1 1 14 1 1 1 0 0 15 1 1 1 0 1 16 1 1 1 1 0 17 1 1 1 1 1 18 www.national.com 16 ELIMINATING THE OUTPUT COUPLING CAPACITOR The LM48821 features a low noise inverting charge pump that generates an internal negative supply voltage. This allows the LM48821 to reference its amplifier outputs to ground instead of a half-supply voltage, like traditional capacitivel-coupled headphone amplifiers. Because there is no DC bias voltage associated with either stereo output, the large DC blocking capacitors (typically 220μF) are not necessary. The coupling capacitors are replaced by two, small ceramic charge pump capacitors, saving board space and cost. Eliminating the output coupling capacitors also improves low frequency response. In traditional headphone amplifiers, the headphone impedance and the output capacitor form a high pass filter that not only blocks the DC component of the output, but also attenuates low frequencies, impacting the bass response. Because the LM48821 does not require the output coupling capacitors, the low frequency response of the device is not degraded. In addition to eliminating the output coupling capacitors, the ground referenced output nearly doubles the output voltage swing and available dynamic range of the LM48821 when compared to a traditional capacitively-coupled output headphone amplifier operating from the same supply voltage. I2C INTERFACE POWER SUPPLY PIN (I2CVDD) The LM48821’s I2C interface is powered up through the I2CVDD pin. The LM48821’s I2C interface operates at a voltage level set by the I2CVDD pin. This voltage can be independent from the main power supply pin (VDD). This is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system. Since the LM48821 has two power amplifiers in one package, the maximum internal power dissipation point is twice that of the number which results from Equation 1. Even with large internal power dissipation, the LM48821 does not require heat sinking over a large range of ambient temperatures. The maximum power dissipation point obtained must not be greater than the power dissipation that results from Equation 2: OUTPUT TRANSIENT ELIMINATED The LM48821 contains advanced circuitry that virtually eliminates output transients (’clicks' and 'pops’). This circuitry attenuates output transients when the supply voltage is first applied or when the part resumes operation after using the shutdown mode. POWER DISSIPATION Power dissipation is a major concern when using any power amplifier and must be thoroughly understood to ensure a successful design. Equation 1 states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and driving a specified output load. PDMAX = (2VDD)2 / (2π2RL) PDMAX = (TJMAX - TA) / (θJA) POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 3.3V voltage regulator typically use a 10μF in parallel with a 0.1μF filter capacitors to stabilize the regulator’s output, reduce noise on the regulated supply lines, and improve the regulator’s transient response. However, their presence does not eliminate the need for a local 1.0μF tantalum bypass capacitance connected between the LM48821’s supply pins and ground. Keep the length of leads and traces that connect capacitors between the LM48821’s power supply pins and ground as short as possible. (1) (2) For the micro SMD package, θJA = 105°C/W. TJMAX = 150°C for the LM48821. Depending on the ambient temperature, TA, of the system surroundings, Equation 2 can be used to find the maximum internal power dissipation supported by the IC packaging. If the result of Equation 1 is greater than that of Equation 2, then either the supply voltage must be decreased, the load impedance increased or TA reduced. Power dissipation is a function of output power and thus, if typical operation is not around the maximum power dissipation point, the ambient temperature may be increased accordingly. 17 www.national.com LM48821 I2C COMPATIBLE INTERFACE The LM48821 uses a serial data bus that conforms to the I2C protocol. Controlling the chip’s functions is accomplished with two wires: serial clock (SCL) and serial data (SDA). The clock line is uni-directional. The data line is bi-directional (opencollector). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the controlling microcontroller and the slave is the LM48821. The bus format for the I2C interface is shown in Figure 3. The bus format diagram is broken up into six major sections: The Start Signal, the I2C Address, an Acknowledge bit, the I2C data, second Acknowledge bit, and the Stop Signal. The start signal is generated by lowering the data signal while the clock signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own address. The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock. Each address bit must be stable while the clock level is high. After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor). Then the master sends an acknowledge clock pulse. If the LM48821 has received the address correctly, then it holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM48821. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable high. After the data byte is sent, the master must check for another acknowledge to see if the LM48821 received the data. If the master has more data bytes to send to the LM48821, then the master can repeat the previous two steps until all data bytes have been sent. The stop signal ends the transfer. To signal stop , the data signal goes high while the clock signal is high. The data line should be held high when not in use. The LM48821's I2C address is shown in Table 1. The I2C data register and its control bit names are shown in Table 2. The data values for the volume control are shown in Table 3. LM48821 supply voltage, a local 4.7μF power supply bypass capacitor should be connected as physically closed as possible to the PVDD pin. SELECTING EXTERNAL COMPONENTS Optimizing the LM48821’s performance requires properly selecting external components. Though the LM48821 operates well when using external components with wide tolerances, best performance is achieved by optimizing component values. Input Capacitor Value Selection Amplifying the lowest audio frequencies requires high value input coupling capacitors (the 0.47μF capacitors in Figure 1). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little improvement by using high value input and output capacitors. Besides affecting system cost and size, the input coupling capacitor value has an effect on the LM48821’s click and pop performance. The magnitude of the pop is directly proportional to the input capacitor’s size. Thus, pops can be minimized by selecting an input capacitor value that is no higher than necessary to meet the desired -3dB frequency. The LM48821's nominal input resistance at full volume is 10kΩ and a minimum of 5kΩ. This input resistance and the input coupling capacitor value produce a -3dB high pass filter cutoff frequency that is found using Equation 3. Charge Pump Capacitor Selection Use low ESR (equivalent series resistance) (<100mΩ) ceramic capacitors with an X7R dielectric for best performance. Low ESR capacitors keep the charge pump output impedance to a minimum, extending the headroom on the negative supply. Higher ESR capacitors result in reduced output power from the audio amplifiers. Charge pump load regulation and output impedance are affected by the value of the flying capacitor (connected between the CCP- and CCP+ pins). A larger valued C1 (up to 4.7μF) improves load regulation and minimizes charge pump output resistance. Beyond 4.7μF, the switchon-resistance dominates the output impedance. The output ripple is affected by the value and ESR of the output capacitor (connected between the VSS and PGND pins). Larger capacitors reduce output ripple on the negative power supply. Lower ESR capacitors minimize the output ripple and reduce the output impedance of the charge pump. The LM48821 charge pump design is optimized for 4.7μF, low ESR, ceramic, flying, and output capacitors. f-3dB = 1/2πRiCi Power Supply Bypass Capacitor For good THD+N and low noise performance and to ensure correct power-on behavior at the maximum allowed power www.national.com 18 (3) LM48821 Revision History Rev Date Description 1.0 06/06/07 Initial release. 19 www.national.com LM48821 Physical Dimensions inches (millimeters) unless otherwise noted 16-Bump micro SMD Order Number LM48821TL NS Package Number TLA1611A X1 = 1.970± 0.03 X2 = 1.970 ± 0.03 X3 = 0.6 ± 0.075 www.national.com 20 LM48821 Notes 21 www.national.com LM48821 Direct Coupled, Ultra Low Noise, 52mW Differential Input Stereo Headphone Amplifier with I2C Volume Control Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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