S6E2DH/DF/D5/D3 Series, FLASH PROGRAMMING MANUAL

The following document contains information on Cypress products.
S6E2DH/DF/D5/D3 Series
32-BIT MICROCONTROLLER
FM4 Family
FLASH PROGRAMMING MANUAL
Publication Number S6E2DH_MN709-00013
CONFIDENTIAL
Revision 1.0
Issue Date February 2, 2015
F L A S H
2
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P R O G R A M M I N G
M A N U A L
S6E2DH_MN709-00013-1v0-E, February 2, 2015
F L A S H
P R O G R A M M I N G
M A N U A L
Preface
Purpose of this manual and intended readers
This manual explains the functions, operations and serial programming of the flash memory of this series.
This manual is intended for engineers engaged in the actual development of products using this series.
Trademark
 ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
The company names and brand names herein are the trademarks or registered trademarks of their
respective owners.
Organization of this Manual
This manual consists of the following 4 chapters.
CHAPTER 1 MainFlash Memory
This chapter gives an overview of, and explains the structure, operation, and registers of the
MainFlash memory.
CHAPTER 2 VFLASH Memory
This chapter gives an overview of, and explains the structure, operation, and registers of the
VFLASH memory.
CHAPTER 3 Flash Security
The flash security feature provides possibilities to protect the content of the flash memory.
This chapter section describes the overview and operations of the flash security.
CHAPTER 4 Serial Programming Connection
This chapter explains the basic configuration for serial write to flash memory by using the Spansion
Serial Programmer.
Sample programs and development environment
Spansion offers sample programs free of charge for operating the peripheral functions of the FM4 family.
Spansion also makes available descriptions of the development environment required for this series. Feel
free to use them to verify the operational specifications and usage of this Spansion microcontroller.
Microcontroller support information:
http://www.spansion.com/Support/microcontrollers/
Note:
−
Note that the sample programs are subject to change without notice. Since they are offered as a
way to demonstrate standard operations and usage, evaluate them sufficiently before running them
on your system.
Spansion assumes no responsibility for any damage that may occur as a result of using a sample
program.
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F L A S H
P R O G R A M M I N G
M A N U A L
How to Use This Manual
Searching for a function
The following methods can be used to search for the explanation of a desired function in this manual:
 Search from the table of the contents
The table of the contents lists the manual contents in the order of description.
 Search from the register
The address where each register is located is not described in the text. To verify the address of a
register, see A. Register Map of Appendixes in FM4 Family Peripheral Manual.
Terminology
This manual uses the following terminology.
Term
Explanation
Word
Indicates access in units of 32 bits.
Half word
Indicates access in units of 16 bits.
Byte
Indicates access in units of 8 bits.
Notations
 The notations in bit configuration of the register explanation of this manual are written as follows.
− bit:
bit number
− Field:
bit field name
− Attribute:
Attributes for read and write of each bit
−
R:
−
W:
−
RW:
−
-:
− Initial value:
Read only
−
−
−
0:
Initial value is "0"
1:
X:
Initial value is "1"
Initial value is undefined
Write only
Readable/Writable
Undefined
Initial value of the register after reset
 The multiple bits are written as follows in this manual.
Example: bit7:0 indicates the bits from bit7 to bit0
 The values such as for addresses are written as follows in this manual.
− Hexadecimal number :
0x is attached in the beginning of a value as a prefix (example : 0xFFFF)
− Binary number:
0b is attached in the beginning of a value as a prefix (example : 0b1111)
− Decimal number:
Written using numbers only (example : 1000)
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P R O G R A M M I N G
M A N U A L
Table of Contents
CHAPTER 1: MainFlash Memory ................................................................................................................ 9
1. Overview ........................................................................................................................................... 10
2. Configuration..................................................................................................................................... 11
3. Operating Description ....................................................................................................................... 14
3.1. MainFlash Memory Access Modes ....................................................................................... 15
3.2. Automatic Algorithm .............................................................................................................. 16
3.2.1. Command Sequence............................................................................................... 17
3.2.2. Command Operating Explanations.......................................................................... 18
3.2.3. Automatic Algorithm Run States .............................................................................. 20
3.3. Explanation of MainFlash Memory Operation ....................................................................... 25
3.3.1. Read/Reset Operation ............................................................................................. 25
3.3.2. Write Operation ....................................................................................................... 26
3.3.3. Flash Erase Operation ............................................................................................ 27
3.3.4. Sector Erase Operation ........................................................................................... 28
3.3.5. Sector Erase Suspended Operation ........................................................................ 30
3.3.6. Sector Erase Restart Operation .............................................................................. 31
3.4. Writing to MainFlash Memory in Products Equipped with ECC ............................................ 32
3.5. MainFlash Accelerator .......................................................................................................... 33
3.6. Data Buffer ............................................................................................................................ 36
3.7. Cautions When Using MainFlash Memory ............................................................................ 37
4. Registers ........................................................................................................................................... 38
4.1. FASZR (Flash Access Size Register) ................................................................................... 39
4.2. FRWTR (Flash Read Wait Register) ..................................................................................... 40
4.3. FSTR (Flash Status Register) ............................................................................................... 41
4.4. FSYNDN (Flash Sync Down Register).................................................................................. 42
4.5. FBFCR (Flash Buffer Control Register) ................................................................................ 43
4.6. FICR (Flash Interrupt Control Register) ................................................................................ 44
4.7. FISR (Flash Interrupt Status Register) .................................................................................. 45
4.8. FICLR (Flash Interrupt Clear Register) ................................................................................. 46
4.9. CRTRMM (CR Trimming Data Mirror Register) .................................................................... 47
4.10. FGPDM1 (Flash General Purpose Data Mirror Register1) .................................................. 48
4.11. FGPDM2 (Flash General Purpose Data Mirror Register2) .................................................. 49
4.12. FGPDM3 (Flash General Purpose Data Mirror Register3) .................................................. 50
4.13. FGPDM4 (Flash General Purpose Data Mirror Register4) .................................................. 51
4.14. FERRAD (Flash ECC ERR Address Capture Register) ...................................................... 52
CHAPTER 2: VFLASH Memory ................................................................................................................. 53
1. Overview ........................................................................................................................................... 54
2. Configuration..................................................................................................................................... 55
2.1. Correspondence of Capacity and Product Types ................................................................. 56
2.2. Configuration of the memory area......................................................................................... 57
3. Registers ........................................................................................................................................... 58
3.1. Status Register 1 (SR1) ........................................................................................................ 59
4. Command ......................................................................................................................................... 60
4.1. RDSR1 (Read Status Register-1) ......................................................................................... 61
4.2. WREN (Write Enable) ........................................................................................................... 62
4.3. WSR (Write Status Register) ................................................................................................ 63
4.4. PP (Page Program)............................................................................................................... 64
4.5. SE (Sector Erase) ................................................................................................................. 65
4.6. BE (Block Erase)................................................................................................................... 66
4.7. CE (Chip Erase) .................................................................................................................... 67
4.8. FRQIO (First Read Quad I/O) ............................................................................................... 68
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5. Explanation of Operations ................................................................................................................. 70
5.1. Initialization ........................................................................................................................... 71
5.2. CPU Write Mode ................................................................................................................... 73
5.2.1. Erasing the VFLASH Memory ................................................................................. 74
5.2.2. Writing to the VFLASH Memory .............................................................................. 75
5.3. Read Mode ........................................................................................................................... 76
5.3.1. Reading the VFLASH Memory ................................................................................ 77
CHAPTER 3: Flash Security ...................................................................................................................... 79
1. Overview ........................................................................................................................................... 80
2. Operation Explanation ...................................................................................................................... 81
CHAPTER 4: Serial Programming Connection ........................................................................................ 83
1. Serial Programmer ............................................................................................................................ 84
1.1. Basic Configuration ............................................................................................................... 85
1.2. Pins Used ............................................................................................................................. 90
Major Changes ........................................................................................................................................... 91
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Figures
Figure 2-1 Memory map ........................................................................................................................... 12
Figure 2-2 Address of security/CR Trimming data /general purpose data ................................................ 13
Figure 2-3 Bit configuration of the CR Trimming area .............................................................................. 13
Figure 3-1 Bit structure of the hardware sequence flags .......................................................................... 20
Figure 3-2 Example write operation.......................................................................................................... 26
Figure 3-3 Example sector erase procedure ............................................................................................ 29
Figure 3-4 Flash Accelerator operating flow (FRWTR,RWT=0b10) .......................................................... 34
Figure 3-5 Flash Accelerator operating flow (FRWTR,RWT=0b11) .......................................................... 35
Figure 2-1 Memory map of 2 Mbyte of memory area ............................................................................... 57
Figure 4-1 Timing when the RDSR1 command is executed ..................................................................... 61
Figure 4-2 Timing when the WREN command is executed ...................................................................... 62
Figure 4-3 Timing when the WSR command is executed ......................................................................... 63
Figure 4-4 Timing when the PP command is executed ............................................................................ 64
Figure 4-5 Timing when the SE command is executed ............................................................................ 65
Figure 4-6 Timing when the BE command is executed ............................................................................ 66
Figure 4-7 Timing when the CE command is executed ............................................................................ 67
Figure 4-8 Timing when the FRQIO command is executed ...................................................................... 69
Figure 4-9 Timing when the FRQIO command with the sequence number 1 omitted is executed ........... 69
Figure 5-1 Flow chart of Initialization ........................................................................................................ 72
Figure 5-2 Flow chart of erase the VFLASH memory ............................................................................... 74
Figure 5-3 Flow chart of write to the VFLASH memory ............................................................................ 75
Figure 5-4 Flow chart of read the VFLASH memory................................................................................. 77
Figure 1-1 Basic Configuration of SPANSION MCU Programmer ............................................................ 85
Figure 1-2 Connection Example when Crystal Oscillator is Used............................................................. 86
Figure 1-3 Connection Example When Built-in High-speed CR Oscillator is used ................................... 87
Figure 1-4 Basic Configuration of SPANSION USB DIRECT Programmer .............................................. 88
Figure 1-5 Connection example using SPANSION USB DIRECT Programmer ....................................... 89
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M A N U A L
Tables
Table 3-1 Access modes of Flash memory ............................................................................................... 15
Table 3-2 Command sequence chart........................................................................................................ 17
Table 3-3 List of hardware sequence flag status ...................................................................................... 20
Table 2-1 Product type list (TYPE4-M4 products)..................................................................................... 56
Table 3-1 Register list ............................................................................................................................... 58
Table 4-1 Control command list ................................................................................................................ 60
Table 1-1 Address of security code and protection code .......................................................................... 80
Table 2-1 Flash Operation with Security Enabled ..................................................................................... 81
Table 1-1 System Configuration of SPANSION MCU Programmer .......................................................... 85
Table 1-2 Oscillating frequency and communication baud rate available for clock asynchronous serial
communication .................................................................................................................................. 86
Table 1-3 System Configuration of SPANSION USB DIRECT Programmer ............................................. 88
Table 1-4 Pins used for serial write........................................................................................................... 90
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CHAPTER 1: MainFlash Memory
This series is equipped with 384KBytes of MainFlash memory.
This chapter gives an overview of, and explains the structure, operation, and registers of the MainFlash
memory.
1. Overview
2. Configuration
3. Operating Description
4. Registers
Code : S6E2DH_FLASH-E01.0
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CHAPTER 1: MainFlash Memory
1. Overview
F L A S H
1.
P R O G R A M M I N G
M A N U A L
Overview
This series is equipped with 384 KBytes of built-in MainFlash memory.
The built-in MainFlash memory can be erased data of sector-by-sector, all-sector of each macro batch
erased data, and programmed data in units of half words (16 bits) by the Cortex-M4 CPU.
This flash memory also has built-in ECC (Error Correction Code) functionality.
Flash Memory Features
 Usable capacity:
384 Kbytes
Because this series stores ECC codes, it is equipped with additional flash memory of 7 bits for every 4
bytes of memory described above.
 High-speed flash:
Up to 72 MHz
0Wait
Up to 160 MHz Allowing Flash accelerator function (prefetch buffer/trace buffer) will achieve 0 Wait at
high speed operational frequency
 Operating mode:
1. CPU ROM mode
This mode only allows reading of flash memory data. Word access is available. However, in this
*1
mode, it is not possible to activate the automatic algorithm to perform writing or erasing.
2. CPU programming mode
*1
This mode allows reading, writing, and erasing of flash memory (automatic algorithm ). Because
word access is not available, programs that are contained in the flash memory cannot be executed
while operating in this mode. Half-word access is available.
3. ROM writer mode
This mode allows reading, writing, and erasing of flash memory from a ROM writer (automatic
*1
algorithm ).
 Built-in flash security function
(Prevents reading of the content of flash memory by a third party)
See CHAPTER 2 Flash Security for details on the flash security function.
 Equipped with an Error Correction Code (ECC) function that can correct up to 1 bit of errors in each word.
(The device is not equipped with a function to detect 2-bit errors.) Errors are automatically corrected when
memory is read.
Furthermore, ECC codes are automatically added upon writing to flash memory. Because there are no
read cycle penalties as a result of error correction, it is not necessary to consider the error correction
penalties during software development.
Note:
−
This document explains flash memory in the case where it is being used in CPU mode.
For details on accessing the flash memory from a ROM writer, see the instruction manual of the
ROM writer that is being used.
*1: Automatic algorithm = Embedded Algorithm
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CHAPTER 1: MainFlash Memory
2. Configuration
F L A S H
2.
P R O G R A M M I N G
M A N U A L
Configuration
This series consists of 384 KBytes MainFlash memory area, a security code area, a High-Speed CR
trimming data area, a HTM code area, and a general purpose data area.
Figure 2-1 shows the address and sector structure of the MainFlash memory built into this series as well as
the address of security/CR trimming data/ general purpose data.
See "CHAPTER 2: Flash Security" for details on the security.
See Section 0 and CHAPTER 2-3: High-Speed CR Trimming of the FM4 Family Peripheral Manual for
details on the High-Speed CR trimming.
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CHAPTER 1: MainFlash Memory
2. Configuration
F L A S H
P R O G R A M M I N G
M A N U A L
Figure 2-1 Memory Map
0x0040_6000
0x0040_4000
General Purpose data
0x0040_2000
CR trimming data
0x0040_0000
Security code
0x0006_0000
SA13 (64KB)
0x0005_0000
SA12 (64KB)
0x0004_0000
SA11 (64KB)
0x0006_0000
0x0003_0000
SA10 (64KB)
0x0002_0000
SA9 (64KB)
0x0001_0000
SA8 (32KB)
0x0000_8000
Flash memory
384KB
0x0000_6000
SA7 (8KB)
0x0000_4000
SA6 (8KB)
0x0000_2000
SA5 (8KB)
0x0000_0000
SA4 (8KB)
bit31
0x0000_0000
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+3
bit0
+2
+1
+0
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CHAPTER 1: MainFlash Memory
2. Configuration
F L A S H
P R O G R A M M I N G
M A N U A L
Figure 2-2 Address of Security/CR Trimming Data /General Purpose Data
0x0040_6000
0x0040_4010
General purpose data 4 area
0x0040_400C
General purpose data 3 area
0x0040_4008
General purpose data 2 area
0x0040_4004
General purpose data 1 area
0x0040_4000
0x0040_2004
CR trimming area
CR Temperature trimming data
0x0040_2000
CR Frequency trimming data
0x0040_0004
Security code area
0x0040_0000
bit31
bit0
+3
+2
+1
+0
Figure 2-3 Bit Configuration of the CR Trimming Area
bit
Field
31
21 20
16 15
10 9
0
Reserved CR temperature trimming data Reserved
CR Frequency trimming data
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.
P R O G R A M M I N G
M A N U A L
Operating Description
This section explains the MainFlash memory operation.
3.1. MainFlash Memory Access Modes
3.2. Automatic Algorithm
3.3. Explanation of MainFlash Memory Operation
3.4. Writing to MainFlash Memory in Products Equipped with ECC
3.5. MainFlash Accelerator
3.6. Data Buffer
3.7. Cautions When Using MainFlash Memory
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.1
P R O G R A M M I N G
M A N U A L
MainFlash Memory Access Modes
The following two access modes are available for accessing MainFlash memory from the CPU.
− CPU ROM mode
− CPU programming mode
These modes can be selected by the flash access size bits (FASZR: ASZ).
CPU ROM Mode
This mode only allows reading of flash memory data.
This mode is entered by setting the flash access size bits (FASZR: ASZ) to 0b10 (32-bit read), and enables
word access.
However, in this mode, it is not possible to execute commands, to activate the automatic algorithm or to write
or erase data.
The flash memory always enters this mode after reset is released.
CPU Programming Mode
This mode allows reading, writing, and erasing of data.
This mode is entered by setting the flash access size bits (FASZR: ASZ) to 0b01 (16-bit read/write), and
enables flash programming.
Because word access is not possible in this mode, programs that are contained in the flash memory cannot
be executed. The operation while in this mode is as follows.
− During reading
Flash memory is accessed in half-words, with data read out in blocks of 16 bits.
− During writing commands
The automatic algorithm can be activated to write or erase data. See Section 3.2 Automatic
Algorithm for details on the automatic algorithm.
Table 3-1 Access modes of Flash memory
Access Mode
Instruction execution in the
Access Size
Automatic Algorithm
CPU ROM mode
32-bit
disable
enable
CPU programming mode
16-bit
enable
Prohibited
Flash Memory
Note:
−
The flash memory is always set to CPU ROM mode when a reset is released. Therefore, if a reset
occurs after entering CPU programming mode, the flash access size bits (FASZR:ASZ) are set to
0b10 and the flash memory returns to CPU ROM mode.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.2
P R O G R A M M I N G
M A N U A L
Automatic Algorithm
When CPU programming mode is used, writing to and erasing MainFlash memory is performed by activating
the automatic algorithm.
This section explains the automatic algorithm.
3.2.1. Command Sequence
3.2.2. Command Operating Explanations
3.2.3. Automatic Algorithm Run States
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.2.1
P R O G R A M M I N G
M A N U A L
Command Sequence
The automatic algorithm is activated by sequentially writing half-word (16-bit) data to the MainFlash memory
one to six times in a row. This is called a command. Table 3-2 shows the command sequences.
Table 3-2 Command Sequence Chart
No.
Command
of
1st write
2nd write
3rd write
4th write
5th write
6th write
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
1
0xXXX
0xF0
--
--
--
--
--
--
--
--
--
--
Write
4
0xAA8
0xAA
0x554
0x55
0xAA8
0xA0
PA
PD
--
--
--
--
Flash erase
6
0xAA8
0xAA
0x554
0x55
0xAA8
0x80
0xAA8
0xAA
0x554
0x55
0xAA8
0x10
Sector erase
6
0xAA8
0xAA
0x 554
0x55
0xAA8
0x80
0xAA8
0xAA
0x554
0x55
SA
0x30
1
0xXXX
0xB0
--
--
--
--
--
--
--
--
--
--
1
0xXXX
0x30
--
--
--
--
--
--
--
--
--
--
writes
Read/
Reset
Sector erase
suspended
Sector erase
restarting
X: Any value
PA: Write address
SA: Sector address (Specify any address within the address range of the sector to erase)
PD: Write data
Notes:
−
−
−
−
−
−
In Table 3-2, the data notation only shows the lower 8 bits. The upper 8 bits can be set to any value.
Write commands as half-words at any time.
In Table 3-2, the address notation only shows the lower 16 bits. The upper 16 bits should be set to
any address within the address range of the target flash macro. When the address outside the flash
macro of flash address range is specified, the command sequence would not operate correctly since
the flash memory cannot recognize the command.
For the address when setting the flash security code, specify the address of 0x0040_0000.
For the address when setting or erasing the CR trimming data, specify the address of 0x0040_2000.
For the address when setting or erasing the general purpose data, specify the address of
0x0040_4000 to 0x0040_400C. (general purpose data 1: 0x0040_4000, general purpose data 2 :
0x0040_4004, general purpose data 3 : 0x0040_4008, general purpose data 4 : 0x0040_400C)
When any of the general purpose data is erased, all of the general purpose data are erased.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.2.2
P R O G R A M M I N G
M A N U A L
Command Operating Explanations
This section explains the command operating.
Read/Reset Command
The flash memory can be read and reset by sending the read/reset command to the target sector in
sequence.
When a read/reset command is issued, the flash memory maintains the read state until another command is
issued.
When the execution of the automatic algorithm exceeds the time limit, the flash memory is returned to the
read/reset state by issuing the read/reset command.
See Section 3.3.1 Read/Reset Operation for details on the actual operation.
Program (Write) Command
The automatic algorithm can be activated and the data is written to the flash memory by issuing the write
command to the target sector in four consecutive writes. Data writes can be performed in any order of
addresses, and may also cross sector boundaries.
In CPU programming mode, data is written in half-words.
Once the forth command issuance has finished, the automatic algorithm is activated and the automatic write
to the flash memory starts. After executing the automatic write algorithm command sequence, there is no
need to control the flash memory externally.
See Section 3.3.2 Write Operation for details on the actual operation.
Notes:
−
The command is not recognized properly if the fourth write command (write data cycle) is issued to
an odd address. Always issue it to an even address.
−
Only a single half-word of data can be written for each write command sequence.
To write multiple pieces of data, issue one write command sequence for each piece of data.
Flash Erase Command
All of the sectors in flash macro including target sector can be batch-erased by sending the flash erase
command to the target sector in six consecutive writes. Once the sixth sequential write has finished, the
automatic algorithm is activated and the flash erase operation starts.
Sector Erase Command
A single sector of flash memory can be erased by sending the sector erase command to the target sector in
six consecutive writes. Once the sixth sequential write has finished and 35 μs has elapsed (timeout interval),
the automatic algorithm is activated and the sector erase operation begins.
To erase multiple sectors, issue the sector erase code (0x30) which is the sixth write code of the sector
erase command to the address of the sector to erase within 35 μs (timeout interval). If the sector erase code
is not issued within the timeout interval, the sector erase code added after the timeout interval has elapsed
may become inactive.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
P R O G R A M M I N G
M A N U A L
Sector Erase Suspended Command
By issuing the sector erase suspended command during sector erase or during command timeout, sector
erase can be suspended. In the sector erase suspended state, the read operation of memory cells of the
sector not to erase is made possible.
See Section 3.3.5 Sector Erase Suspended Operation for details on the actual operation.
Note:
−
This command is only valid during sector erase. It is ignored even if it is issued during flash erase or
during write.
Sector Erase Restart Command
In order to restart the erase operation in the sector erase suspended state, issue the sector erase restart
command. Issuing the sector erase restart command returns the flash memory to the sector erase state and
restarts the erase operation.
See Section 3.3.6 Sector Erase Restart Operation for details on the actual operation.
Note:
−
This command is only valid during sector erase suspended. It is ignored even if it is issued during
sector erase.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.2.3
P R O G R A M M I N G
M A N U A L
Automatic Algorithm Run States
Because writing and erasing of flash memory is performed by the automatic algorithm, whether or not the
automatic algorithm is currently executing can be checked using the flash ready bit (FSTR: RDY) and the
operating status can be checked using the hardware sequence flags.
Hardware Sequence Flags
These flags indicate the status of the automatic algorithm. When the flash ready bit (FSTR: RDY) is 0, the
operating status can be checked by reading any address in flash memory.
Figure 3-1 shows the bit structure of the hardware sequence flags.
Figure 3-1 Bit Structure of the Hardware Sequence Flags
In the event of half-word access
bit
15
14
13
12
11
10
9
8
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
7
6
5
4
3
2
1
0
DPOL
TOGG
TLOV
Undefined
SETI
TOGG2
Undefined
Undefined
bit
In the event of byte access
bit
7
6
5
4
3
2
1
0
DPOL
TOGG
TLOV
Undefined
SETI
TOGG2
Undefined
Undefined
Notes:
−
These flags cannot be read using word access. When in CPU programming mode, always read
using half-word or byte access.
−
−
In CPU ROM mode, the hardware sequence flags cannot be read no matter which address is read.
Because the correct value might not be read out immediately after issuing a command, ignore the
first value of the hardware sequence flags that is read after issuing a command.
Status of Each Bit and MainFlash Memory
Table 3-3 shows the correspondence between each bit of the hardware sequence flags and the status of the
flash memory.
Table 3-3 List of Hardware Sequence Flag States
State
DPOL
Inverted data
Automatic write operation
(*1)
Flash erase
Sector erase
Running
Time limit
exceeded
TLOV
SETI
TOGG2
Toggle
0
0
0
0
Toggle
0
1
Toggle
timeout interval
0
Toggle
0
0
Toggle
erase
0
Toggle
0
1
Toggle
0
0
0
1
Toggle
Automatic
Read
Erase
(Sector to be erased)
operation
TOGG
Sector erase
Read
Data
Data
Data
Data
Data
suspended
(Sector not to be erased)
(*1)
(*1)
(*1)
(*1)
(*1)
Automatic write operation
Inverted data
(Sector not to be erased)
(*1)
Toggle
0
1
0
Toggle
1
0
0
Toggle
1
1
Toggle
Automatic write operation
Automatic erase
Inverted data
(*1)
0
*1: See Bit Descriptions for the values that can be read.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
P R O G R A M M I N G
M A N U A L
Bit Descriptions
[bit15:8] Undefined bits
[bit7] DPOL: Data polling flag b
When the hardware sequence flags are read, by specifying an arbitrary address, this bit uses a data polling
function to indicate whether or not the automatic algorithm is currently running.
The value that is read out varies depending on the operating state.
 During writing
− While write is in progress:
Reads out the opposite value (inverse data) of bit7 of data written at the last command sequence
(PD).
This does not access the address that was specified for reading the hardware sequence flags.
− After write finishes:
Reads out the value of bit7 of the address specified for reading the hardware sequence flags.
 During sector erase
− While sector erase is executing:
Reads out 0 from all areas of flash memory.
− After sector erase finishes:
Always reads out 1.
 During flash erase
− While flash erase is executing: Always reads out 0.
After flash erase: Always reads out 1.
 During sector erase suspended
− When this bit is read out by specifying an address in the sector specified as sector erase:
Reads out 0.
− When this bit is read out by specifying an address in the sector other than specified as sector erase:
− Reads out the value of bit7 of a specified address.
 While write is in progress:
Reads out the opposite value (inverse data) of bit7 of data written at the last command sequence
(PD).
This does not access the address that was specified for reading the hardware sequence flags.
Note:
−
The data for a specified address cannot be read while the automatic algorithm is running. Confirm
that the automatic algorithm has finished running by using this bit before reading data.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
P R O G R A M M I N G
M A N U A L
[bit6] TOGG: Toggle Flag Bit
When the hardware sequence flags are read by specifying an arbitrary address, this bit indicates whether or
not the automatic algorithm is currently running.
The value that is read out varies depending on the operating state.
 During write, sector erase, or flash erase
− During write, sector erase, or flash erase:
When this bit is read out continuously, it alternatingly returns 1 and 0 (toggles). The address that was
specified for reading the hardware sequence flags is not accessed.
− After write, sector erase, or flash erase has finished:
Reads out the value of bit 6 of the address specified for reading the hardware sequence flags.
 During sector erase suspended
− When this bit is read out by specifying an address in the sector specified as sector erase:
Reads out 0.
− When this bit is read out by specifying an address in the sector other than specified as sector erase:
Reads out the value of bit6 of a specified address.
− While write is in progress:
When this bit is read out continuously, it alternatingly returns 1 and 0 (toggles). The address that was
specified for reading the hardware sequence flags is not accessed
[bit5] TLOV: Timing Limit Exceeded Flag Bit
When the hardware sequence flags are read by specifying an arbitrary address, this bit indicates whether or
not the execution time of the automatic algorithm has exceeded the rated time defined internally within the
flash memory (number of internal pulses).
The value that is read out varies depending on the operating state.
 During write, sector erase, or flash erase
The following values are read out.
0: Within the rated time
1: Rated time exceeded
When this bit is 1, if the DPOL bit and TOGG bit indicate that the automatic algorithm is currently
executing, that means a failure occurred during the write or erase.
For example, because data that has been written to 0 cannot be overwritten to 1 in flash memory, if 1
is written to an address that has been written to 0, the flash memory is locked and the automatic
algorithm does not finish. In this case, the value of the DPOL bit remains invalid, and "1" and "0" are
continuously read out alternatingly from the TOGG bit.
Once the rated time is exceeded while still in this state, this bit changes to 1. If this bit changes to 1,
issue the reset command.
 During sector erase suspended
− When this bit is read out by specifying an address in the sector specified as sector erase:
Reads out 0.
− When this bit is read out by specifying an address in the sector other than specified as sector erase:
Reads out the value of bit5 of a specified address.
− During writing:
The following values are read out.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
P R O G R A M M I N G
M A N U A L
0: Within the rated time
1: Rated time exceeded
When this bit is 1, if the DPOL bit and TOGG bit indicate that the automatic algorithm is currently
executing, that means a failure occurred during the write or erase.
Note:
−
If this bit is 1, it indicates that the flash memory was not used correctly. This is not a malfunction of
the flash memory.
Perform the appropriate processing after issuing the reset command.
[bit4] Undefined bit
[bit3] SETI: Sector Erase Timer Flag Bit
When a sector is erased, a timeout interval of 35 μs is required from when the sector erase command is
issued until the sector erase actually begins.
When the hardware sequence flags are read by specifying an arbitrary address, this bit indicates whether or
not the flash memory is currently in the sector erase command timeout interval.
The value that is read out varies depending on the operating state.
 During sector erase:
When sectors are being erasing, it can be checked whether or not the following sector erase code
can be accepted by checking this bit before inputting the following sector erase code.
The following values are read out without accessing the address specified in order to read the
hardware sequence flags.
0: Within sector erase timeout interval
The following sector erase code (0x30) can be accepted.
1: Sector erase timeout interval exceeded
In this case, if the DPOL bit and TOGG bit indicate that the automatic algorithm is currently
executing, the erase operation has started internally within the flash memory. In this case,
commands other than the sector erase suspended (0xB0) are ignored until the internal flash
memory erase operation has finished.
 During sector erase suspended
− When this bit is read out by specifying an address in the sector specified as sector erase:
Reads out 1.
− When this bit is read out by specifying an address in the sector other than specified as sector erase:
Reads out the value of bit3 of a specified address.
− During writing:
Reads out 1.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
P R O G R A M M I N G
M A N U A L
[bit2] TOGG2: Toggle flag bit
In the sector erase suspended state, a sector which is not the erase target can be read. However, the erase
target sector cannot be read. This toggle bit flag can detect whether the corresponding sector is the erase
target sector during the sector erase suspend by checking the toggle operation of the read data.
 During writing
Reads out 0.
 During sector erase or flash erase
When this bit is read out continuously, 1 and 0 are alternately read (toggle operation).
 During sector erase suspended
− When this bit is read out by specifying an address in the sector specified as sector erase:
When this bit is read out continuously, 1 and 0 are alternately read (toggle operation)
− When this bit is read out by specifying an address in the sector other than specified as sector erase:
Reads out the value of bit2 of a specified address.
− During writing:
Reads out 0.
[bit1:0] Undefined bits
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.3
P R O G R A M M I N G
M A N U A L
Explanation of MainFlash Memory Operation
The operation of the MainFlash memory is explained for each command.
3.3.1. Read/Reset Operation
3.3.2. Write Operation
3.3.3. Flash Erase Operation
3.3.4. Sector Erase Operation
3.3.5. Sector Erase Suspended Operation
3.3.6. Sector Erase Restart Operation
3.3.1
Read/Reset Operation
This section explains the read/reset operation.
To place the flash memory in the read/reset state, send read/reset commands to the target sector
consecutively.
Because the read/reset state is the default state of the flash memory, the flash memory always returns to this
state when the power is turned on or when a command finishes successfully. When the power is turned on,
there is no need to issue a data read command. Furthermore, because data can be read by normal read
access and programs can be accessed by the CPU while in the read/reset state, there is no need to issue
read/reset commands.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.3.2
P R O G R A M M I N G
M A N U A L
Write Operation
This section explains the write operation.
Writes are performed according to the following procedure.
1. The write command is issued to the target sector sequentially
The automatic algorithm activates and the data is written to the flash memory.
After the write command is issued, there is no need to control the flash memory externally.
2. Perform read access on the address that was written
The data that is read is the hardware sequence flags. Therefore, once bit7 (the DPOL bit) of the read
data matches the value that was written, the write to the flash memory has finished. If the write has
not finished, the reverse value (inverted data) of bit7 written at the last command sequence (PD) is
read out.
Figure 3-2 shows an example of a write operation to the flash memory.
Figure 3-2 Example Write Operation
Start of writing
Set the ASZ bit of Flash access size
register (FASZR) to "0b01"
Read Flash access size register (FASZR)
(Dummy)
Write command sequence
1. Addr:000X_XAA8
2. Addr:000X_X554
3. Addr:000X_XAA8
4. Write Address
Data:XXAA
Data:XX55
Data:XXA0
Write Data
Read internal address (Dummy)
Read internal address
Next address
Data
Data polling
(DPOL bit)
Inverted data
0
Timing limit
(TLOV bit)
1
Read internal address
Inverted data
Data polling
(DPOL bit)
Data
Write error
Last address
No
Yes
Set the ASZ bit of Flash access size
register (FASZR) to "0b10"
Read Flash access size register (FASZR)
(Dummy)
End of writing
: Verify with a hardware sequence flag.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
P R O G R A M M I N G
M A N U A L
Notes:
−
−
−
−
−
−
−
−
3.3.3
See Section 3.2 Automatic Algorithm for details on the write command.
Because the value of the DPOL bit of the hardware sequence flags changes at the same time as the
TLOV bit, the value needs to be checked again even if the TLOV bit is 1.
The toggle operation stops at the same time as the TOGG bit and TLOV bit of the hardware
sequence flags change to 1. Therefore, even if the TLOV bit is 1, the TOGG bit needs to be checked
again.
Although the flash memory can be written in any sequence of addresses regardless of crossing
sector boundaries, only a single half-word of data can be written with each write command
sequence. To write multiple pieces of data, issue one write command sequence for each piece of
data.
All commands issued to the flash memory during the write operation are ignored.
If the device is reset while the write is in progress, the data that is written is not guaranteed.
Because ECC bits are added in this series, writes are always required to be performed in units of 32
bits by using two 16-bit writes. See Section 3.4 Writing to MainFlash Memory in Products Equipped
with ECC for details on the procedure.
You cannot rewrite to the address once you wrote to because the ECC (Error Correction Code) has
been changed. To perform rewriting to the same address, erase the address (sector erase or flash
erase) in advance.
Flash Erase Operation
This section explains the flash erase operation.
All sectors in target flash macro can be erased in one batch. Erasing all of the sectors in one batch is called
flash erase.
The automatic algorithm can be activated and all of the sectors in flash macro including target sector can be
erased in one batch by sending the flash erase command sequentially to the target sector.
See Section 3.2 Automatic Algorithm for details on the flash erase command.
1. Issue the flash erase command sequentially to the target sector
The automatic algorithm is activated and the flash erase operation of the flash memory begins.
2. Perform read access to an arbitrary address
The data that is read is the hardware sequence flag. Therefore, if the value of bit7 (the DPOL bit) of
the data that was read is 1, that means t the flash erase has finished.
The time required to erase the flash is sector erase time  total number of sectors + flash write time
(preprogramming).
Once the flash erase operation has finished, the flash memory returns to read/reset mode.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.3.4
P R O G R A M M I N G
M A N U A L
Sector Erase Operation
This section explains the sector erase operation.
Sectors in the flash memory can be selected and the data of only the selected sectors can be erased.
Multiple sectors can be specified at the same time.
Sectors are erased according to the following sequence.
1. Issue the sector erase command sequentially to the target sector
Once 35 μs has elapsed (the timeout interval), the automatic algorithm activates and the sector
erase operation begins.
To erase multiple sectors, issue the erase code (0x30) to an address in the sector to erase within
35 μs (the timeout interval). If the code is issued after the timeout interval has elapsed, the added
sector erase code may be invalid.
2. Perform read access to an arbitrary address
The data that is read is the hardware sequence flags. Therefore, if the value of bit7 (the DPOL bit) of
the data that was read is 1, that means the sector erase has finished.
Furthermore, it can be checked whether or not the sector erase has finished by using the TOGG bit.
Figure 3-3 shows an example of the sector erase procedure for the case of using the TOGG bit for
confirmation.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
P R O G R A M M I N G
M A N U A L
Figure 3-3 Example Sector Erase Procedure
Start of erase
Set the ASZ bit of Flash access size
register (FASZR) to "0b01"
Read Flash access size register
(FASZR) (Dummy)
Sector erase command sequence
1. Addr:000X_XAA8
2. Addr:000X_X554
3. Addr:000X_XAA8
4. Addr:000X_XAA8
5. Addr:000X_X554
Data:XXAA
Data:XX55
Data:XX80
Data:XXAA
Data:XX55
Write erase code (0xXX30) to
sector to be erased
Write erase code (0xXX30) to
sector to be erased
消去コード ()
Yes
No
Internal address read (dummy)
Internal address read (dummy)
Internal address read
0
There is another
sector to be erased
Internal address read 1
SETI bit?
Internal address read 2
1
No erasing specification occurs within
35μs additionally.
Set the flag for starting again from the
remainder and suspend the erasing.
TOGG bit values in
Internal address read 1 and 2
are the same
Yes
No
0
Timing limit is exceeded
(TLOV bit)
1
Internal address read 1
Internal address read 2
No
TOGG bit values in
Internal address read 1 and
2 are the same
Yes
Flag for starting again from the
remainder?
No
Failure of erase
Yes
Set the ASZ bit of Flash access size register
(FASZR) to "0b10"
Read Flash access size register (FASZR)
(Dummy)
: Verify with a hardware sequence flag.
End of erase
The time required to erase a sector is (sector erase time + sector write time (preprogramming)) × number of
sectors.
Once the sector erase operation has finished, the flash memory returns to read/reset mode.
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3. Operating Description
F L A S H
P R O G R A M M I N G
M A N U A L
Notes:
−
−
−
−
3.3.5
See Section 3.2 Automatic Algorithm for details on the sector erase command.
Because the value of the DPOL bit of the hardware sequence flags changes at the same time as the
TLOV bit, the value needs to be checked again even if the TLOV bit is 1.
The toggle operation stops at the same time as the TOGG bit and TLOV bit of the hardware
sequence flags change to 1. Therefore, even if the TLOV bit is 1, the TOGG bit needs to be checked
again.
If a command other than the sector erase command or the erase suspended command is issued
during sector erase, including the timeout interval, it is ignored.
Sector Erase Suspended Operation
This section explains the sector erase suspended operation.
When the sector erase suspended command is sent during sector erase or in the command timeout state,
the flash memory makes a transition to the sector erase suspended state and temporarily suspends the
erase operation.
By sending the erase restart command, the flash memory is returned to the sector erase state and can
restart the suspended erase operation. However, even if the flash memory has changed from the command
timeout state to the sector erase suspended state, when the erase restart command is written properly, the
flash memory does not make a transition to the command timeout state but make a transition to the sector
erase state and restarts the sector erase operation immediately.
Sector Erase Suspended Operation
Sector erase is suspended in the following steps:
1. Write the sector erase suspended command to an arbitrary address within the address range of the flash
memory during the time between the command timeout interval and the sector erase interval.
2. If the sector erase suspended command is issued during the command timeout interval, stop timeout
immediately and suspend the erase operation. If the sector erase suspended command is issued during
sector erase, it takes up to 35 μs until erasing is actually stopped.
Notes:
−
−
See Section 3.2 Automatic Algorithm for details on the sector erase suspended command.
Sector erase can only be suspended during the time between the command timeout interval and the
sector erase interval. Flash erase cannot be suspended. In addition, even if the sector erase
suspended command is issued again during sector erase suspended, it is ignored.
State after Sector Erase Suspended
If a sector to erase is read out after sector erase suspended, the hardware sequence flag is read out. On the
other hand, if a sector not to erase is read out, data of a memory cell is read out.
Note:
−
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New erase command is ignored in the sector erase suspended state.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.3.6
P R O G R A M M I N G
M A N U A L
Sector Erase Restart Operation
This section explains the operation for restarting sector erase during sector erase suspended.
When the sector erase restart command is issued to an arbitrary address while sector erase is suspended,
sector erase can be restarted.
When the sector erase restart command is issued, the sector erase operation during sector erase
suspended is restarted.
See Section 3.2 Automatic Algorithm for details on the sector erase restart command.
Notes:
−
−
The sector erase restart command is only valid during sector erase suspended. Even if the sector
erase restart command is issued during sector erase, it is ignored.
After the sector erase restart command is issued, it takes more than 2 ms until the sector erase
operation is restarted. Therefore, when erase restart and erase stop are repeated at intervals less
than this time, timing limit is exceeded while no erase operation is in progress. If the sector erase
suspended command is to be issued again after the sector erase restart command is issued, leave
an interval more than 2 ms after the sector erase restart command is issued.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.4
P R O G R A M M I N G
M A N U A L
Writing to MainFlash Memory in Products Equipped with ECC
This section explains the writing to MainFlash memory in products equipped with ECC.
Because ECC (Error Correction Codes) are attached to each word in this series, writes need to be
performed in blocks of words. Write the data one word at a time by writing two half-words consecutively
using the following procedure. If this procedure is not followed, the data is written to the flash memory
without calculating the ECC, and the written data will not be read correctly.
1. Set the flash access size setting to 16 bits. (FASZR: ASZ="0b01")
Perform a dummy read, after setting the FASZR register.
2. Issue a write command. Write address = PA, Write data = PD[15:0]
See Section 3.3.2 Write Operation for details on the write command.
3. Read the hardware sequence flags once. Because the correct value might not be read out immediately
after issuing a command, this read value should be ignored.
4. Read the hardware sequence flags until the write has finished.
See Section 3.2.3 Automatic Algorithm Run States for details on reading the hardware sequence flags.
5. Issue a write command. Write address = PA+2, Write data = PD[31:16]
At this time, the hardware automatically calculates the ECC codes together with PD[15:0] from step 2, and
also automatically writes the ECC codes at the same time.
6. Read the hardware sequence flags once. Because the correct value might not be read out immediately
after issuing a command, this read value should be ignored.
7. Read the hardware sequence flags until the write has finished.
8. If there is more write data, return to step 2. Once finished writing all of the data, proceed to step 9.
9. Switch to CPU ROM mode. Set the flash access size setting to 32 bits.
(FASZR: ASZ="0b10")
Perform a dummy read, after setting the FASZR register.
10. Read the value that was written, and check that the correct value can be read. Furthermore, even if the
correct value was read, check the flash error bits (FSTR: ERR) to ensure that there have been no ECC
corrections. If an ECC correction has occurred, erase the flash memory and start again from the
beginning.
PA:
PD[31:0]:
PD[31:16]:
PD[15:0]:
Write address (word-aligned)
Write data
Upper 16 bits of the write data
Lower 16 bits of the write data
Note:
−
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CONFIDENTIAL
You cannot rewrite to the address once you wrote to because the ECC (Error Correction Code) has
been changed. To perform rewriting to the same address, erase the address (sector erase or flash
erase) in advance.
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.5
P R O G R A M M I N G
M A N U A L
MainFlash Accelerator
This section explains the MainFlash accelerator.
This series is equipped with Flash accelerator for instruction code to achieve 0 wait at high speed operation
(MAX: 160 MHz).
The Flash accelerator has the following functions:
1. Prefetch Buffer
Addresses will be prefetched to save the instructions in the prefetch buffer. The prefetch buffer consists of
128 bits × 4. If the address hits in this buffer, the value will be output with 0 Wait.
2. Trace Buffer
16 Kbyte RAM is employed for trace buffer. Values read from the Flash memory will be stored in this buffer
at all times. After instruction fetch, if the value has been stored in the trace buffer, it becomes buffer hit and
output the value with 0 Wait.
Note:
−
Number of bits and columns of the prefetch buffer varies depending on each series of FM4.
Number of CPU cycles is different even if it is the same program depending on each series.
For detail, see Flash Programming manual of each series.
Flash Accelerator operating flow at RWT=”0b10” in FRWTR register and the number of Wait are shown in
Figure 3-4.
− Prefetch buffer access occurs at initial state. If the address do not hit in the prefetch buffer, it becomes
prefetch miss. Then, it waits for one cycle and the access is switched to the trace buffer. However, if
the value is hit in the trace buffer, it becomes buffer hit and outputs the value stored in the trace buffer
with 0 Wait.
− If the address do not hut in the trace buffer and a buffer miss occurs, the access will be switched to
one for prefetch buffer again. In that time, the access to the flash memory occurs and the wait cycle of
4 or 5 cycle wait is generated.
− If the address do not hit in both prefetch buffer and trace buffer, 3 or 4 cycle wait for flash memory
access is generated.
− When the trace buffer function is disabled by register setting (See Section 4.5 FBFCR (Flash Buffer
Control Register)), switch from prefetch buffer to trace buffer does not occur. At the prefetch miss, it
requires 3 or 4 cycle wait cycle for flash memory access.
Flash Accelerator operating flow at RWT=”0b11” in FRWTR register and the number of Wait are shown in
Figure 3-5. The number of Wait is different from RWT=0b10 in FRWTR register.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
P R O G R A M M I N G
M A N U A L
Figure 3-4 Flash Accelerator Operating Flow (FRWTR.RWT=0b10)
Prefetch enable
Prefetch hit
0 cycle.
Prefetch
Buffer
read
Prefetch miss &
buffer hit
1 cycle.
Buffer miss
4 or 5 cycles.
Trace
Buffer
read
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CONFIDENTIAL
Prefetch miss &
buffer miss
3, or 4 cycles.
Buffer hit
0 cycle.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
P R O G R A M M I N G
Figure 3-5
M A N U A L
Flash Accelerator Operating Flow (FRWTR.RWT=0b11)
Prefetch enable
Prefetch hit
0 cyc.
Prefetch
Buffer
read
Prefetch miss &
buffer miss
4 or 5 or 6 cyc.
Prefetch miss &
buffer hit
1 cyc.
Buffer miss
5 or 6 or 7 cyc.
Trace
Buffer
read
Buffer hit
0 cyc.
After a reset, RWT bits in FRWTR register becomes "0b11" to enter flash accelerator mode and operate the
prefetch buffer function but the trace buffer function has still been stopped. In order to activate this function,
1 must be written to BE bit in FBFCR (Flash Buffer Control Register). See "4.5 FBFCR (Flash Buffer Control
Register)" for details.
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CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.6
P R O G R A M M I N G
M A N U A L
Data Buffer
This section explains the data buffer.
This series is equipped with data buffer of 128 bits × 2 in D-Code bus area.
1. D-Code bus data buffer
When the mode is CPU ROM mode (FASZR: ASZ=0b10) and FRWTR register RWT=0b10/0b11,
D-Code bus data buffer is enabled.
Up to 2 sets of data read from D-Code bus in the past is stored in 128-bit units. If the address hits in
this buffer, it becomes buffer hit and the value is output with 0 Wait.
In addition, FASZR register, FRWTR register is rewritten, the data stored in the data buffer is
cleared.
Notes:
−
−
36
CONFIDENTIAL
For data buffer, data is stored in 128-bit units. Any data cannot be stored transcending the address
boundary of 128-bits.
Number of bits and columns of the Data buffer varies depending on each series of FM4. Number of
CPU cycles is different even if it is the same program depending on each series.
For detail, see Flash Programming manual of each series.
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 1: MainFlash Memory
3. Operating Description
F L A S H
3.7
P R O G R A M M I N G
M A N U A L
Cautions When Using MainFlash Memory
This section explains the cautions when using MainFlash memory.
− If this device is reset during the write, the data that is written cannot be guaranteed. Moreover, It is
−
−
−
−
necessary to prevent an unexpected reset like Watchdog Timer from occurring during the writing and
deleting.
If the CPU programming mode is configured (ASZ=0b01) in the ASZ[1:0] bits of the flash access size
register (FASZR), do not execute any programs in the flash memory. The correct values will not be
retrieved and the program will run out of control.
If the CPU programming mode is configured (ASZ=0b01) in the ASZ[1:0] bits of the flash access size
register (FASZR) and the interrupt vector table is in the flash memory, ensure that no interrupt
requests occur. The correct values will not be retrieved and the program will run out of control.
If the CPU programming mode is configured (ASZ=0b01) in the ASZ[1:0] bits of the flash access size
register (FASZR), do not transition to low power consumption mode.
If the CPU ROM mode is configured (ASZ=0b10) in the ASZ[1:0] bits of the flash access size register
(FASZR), do not write to the flash memory.
− If the CPU programming mode is configured (ASZ=0b01) in the ASZ[1:0] bits of the flash access size
register (FASZR), always write to the flash memory in half-words. Do not write in bytes.
− Immediately after issuing the automatic algorithm command to the flash memory, always perform a
dummy read before reading the data that is actually wanted. If data is read immediately after issuing
the automatic algorithm command, the read value cannot be guaranteed.
− If the device is forced to transit to the low power consumption mode, ensure the operations of the flash
memory automatic algorithm is completed.
See CHAPTER Low Power Consumption Mode of the FM4 Family Peripheral Manual for details on the
low power consumption mode.
− Since ECC bits are added in this series, it is necessary to perform data programming in unites of 32
bits by using 2 times for 16bit writes. See Section 3.4 Writing to MainFlash Memory in Products
Equipped with ECC for details on the procedure.
− You cannot rewrite to the address once you wrote to because the ECC (Error Correction Code) has
been changed. To perform rewriting to the same address, erase the address (sector erase or flash
erase) in advance.
February 2, 2015, S6E2DH_MN709-00013-1v0-E
CONFIDENTIAL
37
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
4.
P R O G R A M M I N G
M A N U A L
Registers
This section explains the registers.
List of Registers
Abbreviated
Register Name
38
CONFIDENTIAL
Register Name
Reference
FASZR
Flash Access Size Register
4.1
FRWTR
Flash Read Wait Register
4.2
FSTR
Flash Status Register
4.3
FSYNDN
Flash Sync Down Register
4.4
FBFCR
Flash Buffer Control Register
4.5
FICR
Flash Interrupt Register
4.6
FISR
Flash Interrupt Status Register
4.7
FICLR
Flash Interrupt Clear Register
4.8
CRTRMM
CR Trimming Data Mirror Register
4.9
FGPDM1
Flash General Purpose Data Mirror Register1
4.10
FGPDM2
Flash General Purpose Data Mirror Register2
4.11
FGPDM3
Flash General Purpose Data Mirror Register3
4.12
FGPDM4
Flash General Purpose Data Mirror Register4
4.13
FERRAD
Flash ECC ERR Address Capture Register
4.14
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
4.1
P R O G R A M M I N G
M A N U A L
FASZR (Flash Access Size Register)
This section explains the FASZR.
This register configures the access size for flash memory. After reset is released, ASZ is set to 0b10 (32-bit
read), and the flash memory enters CPU ROM mode. To put the flash memory into CPU programming mode,
set ASZ to 0b01.
bit
7
6
5
Field
4
3
2
1
Reserved
0
ASZ
Attribute
RW
RW
Initial Value
1
0
[bit7:2] Reserved bits
The read values are undefined. Ignored on write.
[bit1:0] ASZ: Access Size
Specifies the access size of the flash memory.
Field
bit
Description
Flash Access Size
00: Setting prohibited
ASZ
1:0
01: 16-bit read/write (CPU programming mode)
10: 32-bit read (CPU ROM mode: Initial value)
11: Setting prohibited
Notes:
−
−
When ASZ is set to 0b01, always perform writes to flash using half-word access (16-bit access).
Do not change this register using an instruction that is contained in the flash memory. Overwrite this
register from a program in any other area except for flash memory.
−
−
Perform a dummy read to register, after changing this register.
When ASZ=0b01, BS bit and BE bit in FBFCR register are both cleared to 0, and the trace buffer
function is set to OFF.
February 2, 2015, S6E2DH_MN709-00013-1v0-E
CONFIDENTIAL
39
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
4.2
P R O G R A M M I N G
M A N U A L
FRWTR (Flash Read Wait Register)
This section explains the FRWTR.
This register is effective when ASZ=0b10 (32-bit read mode).
It configures the access method for flash memory.
bit
7
6
5
Field
4
3
2
1
Reserved
0
RWT
Attribute
RW
RW
Initial Value
1
1
[bit7:2] Reserved bits
The read values are undefined. Ignored on write.
[bit1:0] RWT: Read Wait Cycle
Specifies the access method for flash memory.
Field
bit
Description
Read Wait Cycle
00: 0 cycle wait mode (0 latency)
This setting can be used when HCLK is 72 MHz or less.
01: Setting prohibited
RWT
1:0
10: Flash Accelerator mode 0
This setting can be used when HCLK is 160MHz or less.
This setting must be used when HCLK is over 72 MHz.
11: Flash Accelerator mode 1 (Initial value)
This setting must be used when HCLK is over 160 MHz
In flash accelerator mode, allowing operating Flash Accelerator prefetch buffer function achieves 0 Wait at
high speed operational frequency (up to 160 MHz).
After the Flash Accelerator mode is allowed, allowing operating Flash Accelerator trace buffer function (See
Section 4.5 FBFCR (Flash Buffer Control Register) achieves additional progress of performance.
When HCLK is 72 MHz or less, 0 cycle wait mode (RWT = 0b00) is suitable for CPU operation.
In flash accelerator mode, allowing operating the data buffer function. (See Section 3.6 Data )
Notes:
−
−
−
40
CONFIDENTIAL
Do not set RWT to 0b00 (0 cycle wait mode) if HCLK exceeds 72 MHz.
While RWT setting is 0b00, HCLK must not exceed 72 MHz.
Do not set RWT to 0b10 (flash accelerator mode 0) if HCLK exceeds 160 MHz.
While RWT setting is 0b10, HCLK must not exceed 160 MHz.
Perform a dummy read to register, after changing this register.
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
4.3
P R O G R A M M I N G
M A N U A L
FSTR (Flash Status Register)
This section explains the FSTR.
This is a status register of flash memory.
bit
7
6
2
1
0
ERR
HNG
RDY
Attribute
RW
R
R
Initial Value
0
0
X
Field
5
4
3
Reserved
[bit7:3] Reserved bits
The read values are undefined. Ignored on write.
[bit2] ERR: Flash ECC Error
This bit is set to 1 if ECC error correction occurs.
Field
bit
Description
Flash ECC Error
On read:
0: Correction due to an ECC error has not occurred.
ERR
2
1: Correction due to an ECC error has occurred.
On write:
0: Clears this bit.
1: Ignored.
[bit1] HNG: Flash Hang
Indicates whether the flash memory is in the HANG state. Flash memory enters the HANG state if the timing
is exceeded (See "[bit5] TLOV: Timing Limit Exceeded Flag Bit"). If this bit becomes 1, issue a reset
command. (See Section 3.2.1 Command Sequence)
Because the correct value might not be read out immediately after issuing an automatic algorithm command,
ignore the value of this bit as read out the first time after a command is issued.
Field
bit
Description
Flash Hang
HNG
1
0: The flash memory HANG state has not been detected.
1: The flash memory HANG state has been detected.
[bit0] RDY: Flash Rdy
Indicates whether a flash memory write or erase operation using the automatic algorithm is in progress or
finished. While an operation is in progress, data cannot be written and the flash memory cannot be erased.
Field
bit
Description
Flash Rdy
RDY
0
0: Operation in progress (cannot write or erase)
1: Operation finished (can write or erase)
Because the correct value might not be read immediately after an automatic algorithm command is issued,
ignore the value of this bit as read the first time after a command is issued.
February 2, 2015, S6E2DH_MN709-00013-1v0-E
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41
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
4.4
P R O G R A M M I N G
M A N U A L
FSYNDN (Flash Sync Down Register)
This section explains the FSYNDN.
The wait cycle is inserted in the read access to the flash memory at the CPU ROM mode. Current
consumption can be reduced by decreasing the access clock frequency of the flash memory.
bit
7
6
2
1
Attribute
RW
RW
RW
Initial Value
0
0
0
Field
5
4
3
Reserved
0
SD
[bit7:3] Reserved bits
The read values are undefined. Ignored on write.
[bit2:0] SD: Sync Down
The wait cycle is inserted in the lead access of the flash memory.
Field
bit
Description
000: 0(Initial value)
001: +1 Wait
010: Setting is prohibited.
SD
2:0
011: +3 Wait
100: Setting is prohibited.
101: +5 Wait
110: Setting is prohibited.
111: +7 Wait
The number of wait set by this bit is added to the RWT bits of the flash read wait register (FRWTR).
Example)
RWT=0b00 (0cycle wait and SD=0b011, 0+3=3 wait
Notes:
−
−
42
CONFIDENTIAL
This register is valid only when RWT bits in FRWTR register is set to "00". In Flash Accelerator
mode (RWT=0b10/RWT=0b11), the value of this register is ignored.
Perform a dummy read to register, after changing this register.
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
4.5
P R O G R A M M I N G
M A N U A L
FBFCR (Flash Buffer Control Register)
This section explains the FBFCR.
In flash accelerator mode (RWT = 0b10/RWT = 0b11 in FRWTR register), allowing operating FLASH
Accelerator trace buffer function by this register will further improve the performance.
bit
7
6
Field
5
4
3
Reserved
2
1
0
BS
BE
Attribute
R
RW
Initial value
0
0
[bit7:2] Reserved bits
The read values are undefined. Ignored on write.
[bit1] BS: Buffer Status
Field
bit
Description
Buffer Status
BS
1
0: Trace buffer function is in stop or in initializing.
1: Trace buffer function operation is allowed.
[bit0] BE: Buffer Enable
Field
bit
Description
Buffer Enable
BE
0
0: Trace buffer function will be stopped.
1: Trace buffer function operation is allowed.
After the trace buffer function operation is allowed (after "1" is written to BE bit), trace buffer initialization will
be started. After HCLK × 1025 cycles, the initialization will be completed and the trace buffer enters into
operation. BS bit will be set to 1 at this time.
The prefetch buffer will still be functioning while initializing the trace buffer (BE = 1 and BS = 0), allowing
access to the flash memory. When changed to BS =1 and the trace buffer is in operation, the trace buffer will
automatically start tracing.
February 2, 2015, S6E2DH_MN709-00013-1v0-E
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43
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
4.6
P R O G R A M M I N G
M A N U A L
FICR (Flash Interrupt Control Register)
This section explains FICR.
This register is used to enable the interrupt of Flash memory.
bit
7
6
2
1
0
ERRIE
HNGIE
RDYIE
Attribute
RW
RW
RW
Initial value
0
0
0
Field
5
4
3
Reserved
[bit7:3] Reserved bits
The read values are undefined. Ignored on write.
[bit2] ERRIE : Flash ECC Error Interrupt Enable
This bit enables ECC error correction interrupt. When ERRIF bit of FISR register is 1 and this bit is 1, an
interrupt to CPU is generated.
Field
bit
Description
Flash ECC Error Interrupt Enable
ERRIE
2
0: ECC error correction interrupt is disabled. (Initial value)
1: ECC error correction interrupt is enabled.
[bit1] HNGIE : Flash HANG Interrupt Enable
This bit enables flash HANG interrupt. When HANGIF bit of FISR register is 1 and this bit is 1, an interrupt to
CPU is generated.
Field
bit
Description
Flash HANG Interrupt Enable
HNGIE
1
0: Flash HANG interrupt is disabled. (Initial value)
1: Flash HANG interrupt is enabled.
[bit0] RDYIE : Flash RDY Interrupt Enable
This bit enables Flash RDY interrupt. When RDYIF bit of FISR register is 1 and this bit is 1, an interrupt to
CPU is generated.
Field
bit
Description
Flash RDY Interrupt Enable
RDYIE
0
0: Flash RDY interrupt is disabled. (Initial value)
1: Flash RDY interrupt is enabled.
44
CONFIDENTIAL
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
4.7
P R O G R A M M I N G
M A N U A L
FISR (Flash Interrupt Status Register)
This section explains FISR.
This register indicates the interrupt state of Flash memory.
bit
7
6
2
1
0
ERRIF
HNGIF
RDYIF
Attribute
R
R
R
Initial value
0
0
0
Field
5
4
3
Reserved
[bit7:3] Reserved bits
The read values are undefined. Ignored on write.
[bit2] ERRIF : Flash ECC Error Interrupt Flag
When the generation of ECC error correction of Flash read data is detected, this bit is set to 1. This bit is set
at the rising edge of ERR signal. This bit is cleared by writing 1 to ERRC bit of FICLR register.
Field
bit
Description
Flash ECC Error Interrupt Flag
ERRIF
2
0: The generation of ECC error correction is not detected.
1: The generation of ECC error correction is detected.
[bit1] HNGIF : Flash HANG Interrupt Flag
When the Flash HANG state is detected, this bit is set to 1. This bit is set at the rising edge of HNG signal.
This bit is cleared by writing 1 to HNGC bit of FICLR register.
Field
bit
Description
Flash HANG Interrupt Flag
HNGIF
1
0: Flash HANG state is not detected.
1: Flash HANG state is detected.
[bit0] RDYIF : Flash RDY Interrupt Flag
When Flash RDY state is detected, this bit is set to 1. This bit is set at the rising edge of RDY signal. This bit
is cleared by writing 1 to RDYC bit of FICLR register.
Field
bit
Description
Flash RDY Interrupt Flag
RDYIF
0
0: Flash RDY state is not detected.
1: Flash RDY state is detected.
February 2, 2015, S6E2DH_MN709-00013-1v0-E
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45
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
4.8
P R O G R A M M I N G
M A N U A L
FICLR (Flash Interrupt Clear Register)
This section explains FICLR.
This register is used to clear the interrupt state of Flash memory.
bit
7
6
2
1
0
ERRIC
HNGIC
RDYIC
Attribute
RW
RW
RW
Initial value
0
0
0
Field
5
4
3
Reserved
[bit7:3] Reserved bits
The read values are undefined. Ignored on write.
[bit2] ERRIC : Flash ECC Error Interrupt Clear
This bit clears the ERR interrupt flag. By writing 1 to this bit, ERRIF bit of FISR register is cleared to 0.
Field
bit
Description
Flash ECC Error Interrupt Clear
At write
ERRIC
0: ECC error correction interrupt flag (ERRIF) is not changed.
2
1: ECC error correction interrupt flag (ERRIF) is cleared.
At read
"0" is read out.
[bit1] HNGIC : Flash HANG Interrupt Clear
This bit clears HNG interrupt flag. By writing 1 to this bit, HNGIF bit of FISR register is cleared to 0.
Field
bit
Description
Flash HANG Interrupt Clear
At write
HNGIC
0: Flash HANG interrupt flag (HNGIF) is not changed.
1
1: Flash HANG interrupt flag (HNGIF) is cleared.
At read
"0" is read out.
[bit0] RDYIC : Flash RDY Interrupt Clear
This bit clears RDY interrupt flag. By writing 1 to this bit, RDYIF bit of FISR register is cleared to 0.
Field
bit
Description
Flash RDY Interrupt Clear
At write
RDYIC
0
0: Flash RDY interrupt flag (RDYIF) is not changed.
1: Flash RDY interrupt flag (RDYIF) is cleared.
At read
"0" is read out.
46
CONFIDENTIAL
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
4.9
P R O G R A M M I N G
M A N U A L
CRTRMM (CR Trimming Data Mirror Register)
This section explains the CRTRMM.
This is the mirror register of the CR trimming data.
A value of this register can be used in the user mode and the serial writer mode.
bit
31
20
Field
Reserved
16
TTRMM
9
Reserved
0
TRMM
Attribute
R
R
Initial value
*
*
[bit31:21] Reserved bits
The read values are undefined. Ignored on write.
[bit20:16] TTRMM : Temperature CR Trimming Data Mirror Register
After reset is released, store the bit[4:0] in an address of “0x0040_2002” (temperature trimming data) of the
flash memory area into this register.
See CHAPTER High-Speed CR Trimming of the FM4 Family Peripheral Manual for details on the CR
temperature trimming data.
Field
TTRMM
bit
20:16
Description
*: Reads out bit[4:0] of an address of 0x0040_2002.
[bit15:10] Reserved bits
The read values are undefined. Ignored on write.
[bit9:0] TRMM : CR Trimming Data Mirror Register
After reset is released, store the bit[9:0] in an address of “0x0040_2000” (frequency trimming data) of the
flash memory area into this register.
See CHAPTER High-Speed CR Trimming of the FM4 Family Peripheral Manual for details on the CR
Frequency trimming data.
Field
TRMM
bit
9:0
Description
*: Reads out bit[9:0] of an address of 0x0040_2000.
Note:
−
After the flash memory is lost, as this register is cleared when reset is issued in a chip, the stored
CR trimming data is lost. Therefore, before this register is cleared, save the CR trimming data stored
in the register on the RAM, etc.
February 2, 2015, S6E2DH_MN709-00013-1v0-E
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47
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
P R O G R A M M I N G
M A N U A L
4.10 FGPDM1 (Flash General Purpose Data Mirror Register1)
This section explains the FGPDM1.
This is the mirror register of the general purpose data1.
bit
31
0
Field
GPD1
Attribute
R
Initial value
*
[bit31:0] GPD1 : General Purpose Data1
After reset is released, store the bit[31:0] in an address of 0x0040_4000 (general purpose data1) of the flash
memory area into this register.
Field
GPD1
bit
31:0
Description
*: Reads out bit[31:0] of an address of 0x0040_4000.
Note:
−
48
CONFIDENTIAL
After the flash memory is lost, as this register is cleared when reset is issued in a chip, the stored
general purpose data1 is lost. Therefore, before this register is cleared, save the general purpose
data1 stored in the register on the RAM, etc.
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
P R O G R A M M I N G
M A N U A L
4.11 FGPDM2 (Flash General Purpose Data Mirror Register2)
This section explains the FGPDM2.
This is the mirror register of the general purpose data2.
bit
31
0
Field
GPD2
Attribute
R
Initial value
*
[bit31:0] GPD2 : General Purpose Data2
After reset is released, store the bit[31:0] in an address of 0x0040_4004 (general purpose data2) of the flash
memory area into this register.
Field
GPD2
bit
31:0
Description
*: Reads out bit[31:0] of an address of 0x0040_4004.
Note:
−
After the flash memory is lost, as this register is cleared when reset is issued in a chip, the stored
general purpose data2 is lost. Therefore, before this register is cleared, save the general purpose
data2 stored in the register on the RAM, etc.
February 2, 2015, S6E2DH_MN709-00013-1v0-E
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49
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
P R O G R A M M I N G
M A N U A L
4.12 FGPDM3 (Flash General Purpose Data Mirror Register3)
This section explains the FGPDM3.
This is the mirror register of the general purpose data3.
bit
31
0
Field
GPD3
Attribute
R
Initial value
*
[bit31:0] GPD3 : General Purpose Data3
After reset is released, store the bit[31:0] in an address of 0x0040_4008 (general purpose data3) of the flash
memory area into this register.
Field
GPD3
bit
31:0
Description
*: Reads out bit[31:0] of an address of 0x0040_4008.
Note:
−
50
CONFIDENTIAL
After the flash memory is lost, as this register is cleared when reset is issued in a chip, the stored
general purpose data3 is lost. Therefore, before this register is cleared, save the general purpose
data3 stored in the register on the RAM, etc.
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
P R O G R A M M I N G
M A N U A L
4.13 FGPDM4 (Flash General Purpose Data Mirror Register4)
This section explains the FGPDM4.
This is the mirror register of the general purpose data4.
bit
31
0
Field
GPD4
Attribute
R
Initial value
*
[bit31:0] GPD4 : General Purpose Data4
After reset is released, store the bit[31:0] in an address of 0x0040_400C (general purpose data4) of the flash
memory area into this register.
Field
GPD4
bit
31:0
Description
*: Reads out bit[31:0] of an address of 0x0040_400C.
Note:
−
After the flash memory is lost, as this register is cleared when reset is issued in a chip, the stored
general purpose data4 is lost. Therefore, before this register is cleared, save the general purpose
data4 stored in the register on the RAM, etc.
February 2, 2015, S6E2DH_MN709-00013-1v0-E
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51
CHAPTER 1: MainFlash Memory
4. Registers
F L A S H
P R O G R A M M I N G
M A N U A L
4.14 FERRAD (Flash ECC ERR Address Capture Register)
This section explains FERRAD.
This register saves the address when ECC error correction of read data of Flash memory is generated.
bit
31
22
Field
Reserved
0
ERRAD
Attribute
R
Initial value
0
[bit31:23] Reserved bits
The read values are undefined. Ignored on write.
[bit22:0] ERRAD : Flash ECC ERR Address Capture Register
This register saves the address when ECC error correction of read data of Flash memory is generated.
Field
ERRAD
bit
22:0
Description
Saves the address when ECC error correction is generated.
Note:
−
52
CONFIDENTIAL
An address once stored is retained until ERR bit of FSTR register is set to 1 again. That is to say,
without clearing FSTR: ERR bit, the address stored at first is stored irrespective of the continuous
generation of ERR.
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 2: VFLASH Memory
This chapter explains the function and operation of the VFLASH memory.
1. Overview
2. Configuration
3. Registers
4. Command
5. Explanation of Operations
Administration code:
February 2, 2015, S6E2DH_MN709-00013-1v0-E
CONFIDENTIAL
9BFADCTOP_FM4-J01.0
53
CHAPTER 2:
F L A S H
1.
P R O G R A M M I N G
VFLASH Memory
1. Overview
M A N U A L
Overview
In addition to on-chip flash memory, this series is equipped with the HS_SPI flash memory (VFLASH
memory, hereafter) that consists of 2-Mbyte area for data storage.
The VFLASH memory consists of memory area for data storage and registers for memory status and
memory control.
By controlling the HS_SPI controller from CPU and issuing commands, writing data in page unit (256 bytes)
with Cortex-M4 CPU, erasing data in sector unit (4 Kbytes) or in block unit (64 Kbytes), and erasing entire
data in the VFLASH memory can be performed.
In addition, reading in byte unit, half word unit and word unit by using peripherals, such as Cortex-M4 CPU
and DMA controller, etc., can be performed.
Features of the VFLASH Memory
 Operation mode
− CPU write mode
This mode can perform writing data in page unit (256 bytes) from CPU to VFLASH memory, erasing
data in sector unit (4 Kbytes) or in block unit (64 Kbytes), and erasing entire data by setting the
HS_SPI controller to direct mode.
− Read mode
This mode can perform reading in byte unit, half word unit and word unit from peripherals, such as
CPU and DMA controller, etc., by setting the HS_SPI controller to command sequencer mode.
− ROM writer mode
This mode can perform data reading, data writing and data erasing of flash memory from ROM
writer.
Note:
−
54
CONFIDENTIAL
This manual describes the methods to use the VFLASH memory in CPU write mode and read mode.
For details of the methods to access from ROM writer to the VFLASH memory, refer to the operation
manual for the ROM writer you are using.
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 2: VFLASH Memory
2. Configuration
F L A S H
2.
P R O G R A M M I N G
M A N U A L
Configuration
This section explains the correspondence of the capacity of the VFLASH memory equipped for this series
and product types, and explains the configuration of address, page, sector and block of the main area.
2.1. Correspondence of Capacity and Product Types
2.2. Configuration of the memory area
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CHAPTER 2:
F L A S H
2.1
P R O G R A M M I N G
VFLASH Memory
2. Configuration
M A N U A L
Correspondence of Capacity and Product Types
Table 2-1 Product Type List (TYPE4-M4 Products)
Type Name *
VFLASH Memory Size
2 MByte
S6E2D35GJAMV20
TYPE4-M4
S6E2D55GJAMV20
S6E2DF5GJAMV20
S6E2DH5GJAMV20
*: The product names are used in peripheral manuals to classify the products.
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CHAPTER 2: VFLASH Memory
2. Configuration
F L A S H
2.2
P R O G R A M M I N G
M A N U A L
Configuration of the memory area
This section shows the configuration of address, page, sector and block of the main area.
Figure 2-1 Memory map of 2 Mbyte of memory area
0x1F_FFFF
Sector 511 （4 KB)
Sector 510 （4 KB)
Sector 509 （4 KB)
Sector 508 （4 KB)
Sector 507 （4 KB)
Sector 506 （4 KB)
Sector 505 （4 KB)
Sector 504 （4 KB)
Block 31 （64 KB)
Sector 503 （4 KB)
Sector 502 （4 KB)
Sector 501 （4 KB)
Sector 500 （4 KB)
Sector 499 （4 KB)
Sector 498 （4 KB)
Sector 497 （4 KB)
Sector 496 （4 KB)
…
Block 0 （64 KB)
0x00_0000
Sector 15 （4 KB)
Page 15 （256 B)
Sector 14 （4 KB)
Page 14 （256 B)
Sector 13 （4 KB)
Page 13 （256 B)
Sector 12 （4 KB)
Page 12 （256 B)
Sector 11 （4 KB)
Page 11 （256 B)
Sector 10 （4 KB)
Page 10 （256 B)
Sector 9 （4 KB)
Page 9 （256 B)
Sector 8 （4 KB)
Page 8 （256 B)
Sector 7 （4 KB)
Page 7 （256 B)
Sector 6 （4 KB)
Page 6 （256 B)
Sector 5 （4 KB)
page 5 （256 B)
Sector 4 （4 KB)
Page 4 （256 B)
Sector 3 （4 KB)
Page 3 （256 B)
Sector 2 （4 KB)
Page 2 （256 B)
Sector 1 （4 KB)
Page 1 （256 B)
Sector 0 （4 KB)
Page 0 （256 B)
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CHAPTER 2:
F L A S H
3.
P R O G R A M M I N G
VFLASH Memory
3. Registers
M A N U A L
Registers
This section explains the registers of the VFLASH memory.
Table 3-1 Register List
Abbreviated Register
Register Name
Name
SR1
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Status Register 1
Reference
3.1
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 2:
3. Registers
VFLASH Memory
F L A S H
3.1
P R O G R A M M I N G
M A N U A L
Status Register 1 (SR1)
The SR1 register indicates the operating status of the VFLASH memory.
bit
7
6
5
4
3
2
1
0
Field
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WEL
BUSY
Attribute
-
-
-
-
-
-
R/W
R
0
0
0
0
0
0
0
0
Initial
value
[bit7:2] Reserved bits
Specify the initial value when writing.
[bit1] WEL:Write Enable Latch
Indicates the permission state for writing to the register and VFLASH memory.
By issuing the WREN (0x06) command and setting WEL=1, writing to registers, writing to memory and
erase command are enabled.
When writing or erase command is completed, WEL=0 is set.
bit
Description
0
Writing to register, programming and deleting the memory area are disabled.
1
Writing to register, programming and deleting the memory area are enabled.
[bit0] BUSY:
Embedded Operation Status
Indicates the operation state of the VFLASH memory.
When writing to the register, writing to the memory area and issuing erase command are performed,
BUSY=1 is set, then BUSY=0 is set when those operations are completed.
bit
Description
0
Writing to the register, writing to the memory area or erasing operation is not in progress.
1
Writing to the register, writing to the memory area or erasing operation is in progress.
Note:
−
In order to set WEL to 1, send the WREN (0x06) command to the VFLASH memory.
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CHAPTER 2:
F L A S H
4.
P R O G R A M M I N G
VFLASH Memory
4. Command
M A N U A L
Command
This section explains the control commands of the VFLASH memory.
A command consists of independent control command or control command followed by parameters, such as
address, data, etc.
Table 4-1 Control Command List
Control
Command
Control Command
Control Content of VFLASH Memory
Refer to
Name
RDSR1
0x05
Reads status register 1.
4.1
WREN
0x06
Sets the WEL bit of the status register 1 to 1.
4.2
WSR
0x01
Writes status register 1.
4.3
PP
0x02
Performs page writing the memory area.
4.4
SE
0x20
Performs erasing of the memory area in sectors.
4.5
BE
0xD8
Performs erasing of the memory area in blocks.
4.6
CE
0xC7
Performs erasing of the entire memory area.
4.7
FRQIO
0xEB
Performs reading of the memory area.
4.8
Indications
 This manual describes the bit configuration figures for register description with the following indications.
− Number:
Sequence number
− Command:
Bit field name
− Transmission/reception direction: Read/write attribute of commands for the HS_SPI controller
−
−
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CONFIDENTIAL
R:
Reading from the HS_SPI controller
W:
Writing to the HS_SPI controller
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CHAPTER 2:
4. Command
VFLASH Memory
F L A S H
4.1
P R O G R A M M I N G
M A N U A L
RDSR1 (Read Status Register-1)
The RDSR1 command reads the content of the status register 1.
 Command transmission/reception sequence
Number
1
2
Command
0x05
SR1
W
R
Transmission/reception
direction
Sequence number 1
Writes the command (0x05) for reading the status register 1 into transmission FIFO (TX_FIFO) of the
HS_SPI controller.
Sequence number 2
The content of the status register 1 output from the VFLASH memory will be automatically stored in
reception FIFO (RX_FIFO) of the HS_SPI controller.
Read FIFO to acquire the content of the status register 1.
 Timing diagram
Figure 4-1 Timing when the RDSR1 Command is Executed
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CHAPTER 2:
F L A S H
4.2
P R O G R A M M I N G
VFLASH Memory
4. Command
M A N U A L
WREN (Write Enable)
The WREN command sets the WEL bit of the status register 1 to 1.
 Command transmission/reception sequence
Number
1
Command
0x06
Transmission/reception
direction
W
Sequence number 1
Writes the command (0x06) for setting WEL of the status register 1 to 1 into transmission FIFO (TX_FIFO)
of the HS_SPI controller.
 Timing diagram
Figure 4-2 Timing when the WREN Command is Executed
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CHAPTER 2:
4. Command
VFLASH Memory
F L A S H
4.3
P R O G R A M M I N G
M A N U A L
WSR (Write Status Register)
The WSR command performs initialization of the status register 1 (SR1)
 Command transmission/reception sequence
Number
1
2
3
4
Command
0x01
0x00
0x06
0x76
W
W
W
W
Transmission/reception
direction
Sequence number 1
Writes the command (0x01) for initializing the status register 1 (SR1) into transmission FIFO (TX_FIFO) of
the HS_SPI controller.
Sequence number 2/3/4
Writes 0x00, 0x06, and 0x76 into the transmission FIFO (TX_FIFO) of the HS_SPI controller.
 Timing diagram
Figure 4-3 Timing when the WSR Command is Executed
Note:
−
When issuing a WSR command, set the WEL bit of the status register 1 to 1.
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CHAPTER 2:
F L A S H
4.4
P R O G R A M M I N G
VFLASH Memory
4. Command
M A N U A L
PP (Page Program)
The PP command performs writing of the specified 256 byte data from the page address of the specified
24-bit memory area.
 Command transmission/reception sequence
Number
1
Command
0x02
Transmission/reception
direction
W
2
3
4
5 to 260
WA
WA
WA
WD0 to
[7:0]
[15:8]
[23:16]
WD255
W
W
W
W
Sequence number 1
Writes the command (0x02) for writing data specified with WD0 to WD255 into memory area from the
page address specified with the sequence number 2/3/4 into transmission FIFO (TX_FIFO) of the HS_SPI
controller.
Sequence number 2/3/4
Writes the page address of memory area where writing will be performed into the transmission FIFO
(TX_FIFO) of the HS_SPI controller.
Page address of 24 bits will be written by 8 bits in order from the lower.
Sequence number 5 to 260
Writes the data for writing to memory area into transmission FIFO (TX_FIFO) of the HS_SPI controller.
 Timing diagram
Figure 4-4 Timing when the PP Command is Executed
Notes:
−
−
−
−
−
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CONFIDENTIAL
When issuing a PP command, set the WEL bit of the status register 1 to 1.
WD0 to WD255 cannot be omitted because writing to memory area is performed in page (256 bytes)
unit.
Specify 0 to the lower 8 bits of the memory area page address.
At the beginning of execution of the PP command, the BUSY bit of the status register 1 becomes 1,
and it will be 0 when the command is completed.
When the BUSY bit is 1, the following commands cannot be transmitted.
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CHAPTER 2:
4. Command
VFLASH Memory
F L A S H
4.5
P R O G R A M M I N G
M A N U A L
SE (Sector Erase)
The SE command performs erasing of the area of 1 sector (4 Kbyte) from the sector address of the specified
24-bit memory area.
 Command transmission/reception sequence
Number
1
Command
0x20
Transmission/reception
direction
W
2
3
4
WA
WA
WA
[7:0]
[15:8]
[23:16]
W
W
W
Sequence number 1
Writes the command (0x20) for erasing area of 1 sector (4 Kbytes) into transmission FIFO (TX_FIFO) of
the HS_SPI controller.
Sequence number 2/3/4
Writes the sector address of memory area where erasing will be performed into the transmission FIFO
(TX_FIFO) of the HS_SPI controller.
Sector address of 24 bits will be written by 8 bits in order from the lower.
 Timing diagram
Figure 4-5 Timing when the SE Command is Executed
Notes:
−
−
−
−
When issuing an SE command, set the WEL bit of the status register 1 to 1.
Specify 0 to the lower 12 bits of the memory area sector address.
At the beginning of execution of the SE command, the BUSY bit of the status register 1 becomes 1,
and it will be 0 when the command is completed.
When the BUSY bit is 1, the following commands cannot be transmitted.
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CHAPTER 2:
F L A S H
4.6
P R O G R A M M I N G
VFLASH Memory
4. Command
M A N U A L
BE (Block Erase)
The BE command performs erasing of the area of 1 block (64 Kbyte) from the block address of the specified
24-bit memory area.
 Command transmission/reception sequence
Number
1
Command
0xD8
Transmission/reception
direction
W
2
3
4
WA
WA
WA
[7:0]
[15:8]
[23:16]
W
W
W
Sequence number 1
Writes the command (0xD8) for erasing area of 1 block (64 bytes) into transmission FIFO (TX_FIFO) of
the HS_SPI controller.
Sequence number 2/3/4
Writes the block address of memory area where erasing will be performed into the transmission FIFO
(TX_FIFO) of the HS_SPI controller.
Block address of 24 bits will be written by 8 bits in order from the lower.
 Timing diagram
Figure 4-6 Timing when the BE Command is Executed
Notes:
−
−
−
−
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CONFIDENTIAL
When issuing a BE command, set the WEL bit of the status register 1 to 1.
Specify 0 to the lower 16 bits of the memory area sector address.
At the beginning of execution of the BE command, the BUSY bit of the status register 1 becomes 1,
and it will be 0 when the command is completed.
When the BUSY bit is 1, the following commands cannot be transmitted.
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 2:
4. Command
VFLASH Memory
F L A S H
4.7
P R O G R A M M I N G
M A N U A L
CE (Chip Erase)
The CE command performs erasing of entire memory area.
 Command transmission/reception sequence
Number
1
Command
0xC7
Transmission/reception
direction
2
3
4
5
6
7
8
W
Sequence number 1
Writes the command (0xC7) for erasing entire memory area into transmission FIFO (TX_FIFO) of the
HS_SPI controller.
 Timing diagram
Figure 4-7 Timing when the CE Command is Executed
Notes:
−
−
When issuing a CE command, set the WEL bit of the status register 1 to 1.
At the beginning of execution of the CE command, the BUSY bit of the status register 1 becomes 1,
and it will be 0 when the command is completed.
−
When the BUSY bit is 1, the following commands cannot be transmitted.
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67
CHAPTER 2:
F L A S H
4.8
P R O G R A M M I N G
VFLASH Memory
4. Command
M A N U A L
FRQIO (First Read Quad I/O)
The FRQIO command performs reading of memory area.
 Command transmission/reception sequence
Number
1
Command
0xEB
Transmission/reception
direction
W
2
3
4
RA
RA
RA
[7:0]
[15:8]
[23:16]
W
W
W
5
6
7
0xA0
Dummy
Dummy
W
R
R
8 or
later
RD0 or
more
R
Sequence Number 1
Writes the command (0xEB) for reading memory area into transmission FIFO (TX_FIFO) of the HS_SPI
controller.
When consecutively executing the FRQIO commands, the sequence number 1 for the second execution
or later can be omitted.
Sequence Number 2/3/4
Writes the address of memory area where reading will be performed into the transmission FIFO
(TX_FIFO) of the HS_SPI controller.
Address of 24 bits will be written by 8 bits in order from the lower.
Sequence Number 5
Writes 0xA0 into the transmission FIFO (TX_FIFO) of the HS_SPI controller.
Sequence Number 6/7
Performs the Dummy reading from the reception FIFO (RX_FIFO) of the HS_SPI controller.
The read data will be invalid.
Sequence Number 8 or Later
The data recorded in memory area output from the VFLASH memory will be stored in reception FIFO
(RX_FIFO) of the HS_SPI controller.
Read FIFO to acquire the data recorded in memory area.
Because 1 is automatically added to the address within the VFLASH memory, data can be acquired by
consecutively reading FIFO to acquire the next address in memory area.
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CHAPTER 2:
4. Command
VFLASH Memory
F L A S H
P R O G R A M M I N G
M A N U A L
 Timing diagram
Figure 4-8 Timing when the FRQIO Command is Executed
Figure 4-9 Timing when the FRQIO Command with the Sequence Number 1 Omitted is Executed
Note:
−
When executing the FRQIO command after another command has been executed, the sequence
number 1 cannot be omitted.
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CHAPTER 2: VFLASH Memory
5. Explanation of Operations
F L A S H
5.
P R O G R A M M I N G
M A N U A L
Explanation of Operations
This section explains the operations of the HS_SPI controller and the VFLASH memory.
5.1. Initialization
5.2. CPU Write
5.3. Read
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CHAPTER 2: VFLASH Memory
5. Explanation of Operations
F L A S H
5.1
P R O G R A M M I N G
M A N U A L
Initialization
This section explains how to initialize the I/O port, the HS_SPI controller and the VFLASH memory.
Initialization of I/O Port
Set the I/O port to connect the HS_SPI controller to the VFLASH memory.
Perform the following setting for each register of PFR7/PDOR7/DDR7/EPFR26.
−
−
−
−
PFR7: 0x003F
PDOR7: bit6=0, bit10=0
DDR7: bit6=1, bit10=1
EPFR26: 0x00015555
Initialization of the HS_SPI Controller
In order to initialize the HS_SPI controller, perform the following settings for the HS_SPI peripheral
communication set registers (HSSPIn_PCC0 to 3), set 1 to the CSEN bit of the HS_SPI control register, and
set the HS_SPI controller to direct mode.
−
−
−
−
−
Clock division ratio setting bit (CDRS): 1 or more (set 1 or more depending on the operation clock)
Endian set bit (SENDIAN): 1
Serial data transmission/reception timing set bit (ACES): 0
Serial clock polarity set bit (CPOL): 0
Clock phase set bit (CPHA): 0
Initialization of the VFLASH Memory
After executing the WREN command, execute the WSR command. Monitor the status register 1 with the
RDSR command, then initialization is completed when the BUSY bit becomes 0.
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CHAPTER 2: VFLASH Memory
5. Explanation of Operations
F L A S H
P R O G R A M M I N G
M A N U A L
Figure 5-1 Flow Chart of Initialization
Initialization
Initialization of I/O port
Initialization of the HS_SPI
Execute WREN command to set
SR1.WEL=1
Execute WSR command
Execute RDSR1 command to read
SR1
SR1.BUSY=1？
Yes
No
Initialization completed
Note:
−
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CONFIDENTIAL
For details of the setting for the I/O port and the HS_SPI controller, refer to Peripheral Manual.
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 2: VFLASH Memory
5. Explanation of Operations
F L A S H
5.2
P R O G R A M M I N G
M A N U A L
CPU Write Mode
This section explains the CPU write mode setting and how to erase/write data for VFLASH performed in this
mode.
HS_SPI Controller Setting
At the time when the initialization of the HS_SPI controller and VFLASH memory has been completed, no
additional setting is required because the HS_SPI controller is set to direct mode.
In order to set to CPU write mode after using read mode, follow the procedure in 5.1Initialization to initialize
the HS_SPI controller.
Note:
−
For details of the setting for the HS_SPI controller, refer to Peripheral Manual.
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CHAPTER 2: VFLASH Memory
5. Explanation of Operations
F L A S H
5.2.1
P R O G R A M M I N G
M A N U A L
Erasing the VFLASH Memory
This section explains how to erase the VFLASH memory.
Figure 5-2 Flow Chart of Erase the VFLASH Memory
1.
2.
3.
4.
5.
6.
Set to the CPU write mode before starting erasing.
Execute the WREN command to set the WEL bit of the status register 1 to 1.
Execute command depending on the unit (sector/block/entire area) to perform erasing.
Execute the RDSR1 command to read the content of the status register 1.
Return to step 4 to repeat the procedure until the BUSY bit of the status register 1 becomes 0.
In order to perform erasing another area, return to step 2 to repeat the procedure.
Note:
−
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CONFIDENTIAL
Because the WEL bit of the status register 1 returns to 0 when an erase command is executed.
execute the WREN command each time an erase command is executed.
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CHAPTER 2: VFLASH Memory
5. Explanation of Operations
F L A S H
5.2.2
P R O G R A M M I N G
M A N U A L
Writing to the VFLASH Memory
This section explains how to write to the VFLASH memory.
Figure 5-3 Flow Chart of Write to the VFLASH Memory
Writing to VFLASH memory
Currently set to
CPU write mode?
Yes
No
Set to CPU write mode
Execute WREN command to set
SR1.WEL=1
Execute PP command
Execute RDSR1 command to read SR1
SR1.BUSY=1？
Yes
No
Perform writing
operation for
another area?
Yes
No
Writing completed
1.
2.
3.
4.
5.
6.
Transition to the CPU write mode before starting writing.
Execute the WREN command to set the WEL bit of the status register 1 to 1.
Execute the PP command.
Execute the RDSR1 command to read the content of the status register 1.
Return to step 4 to repeat the procedure until the BUSY bit of the status register 1 becomes 0.
In order to perform writing to another area, return to step 2 to repeat the procedure.
Note:
−
Because the WEL bit of the status register 1 returns to 0 when a PP command is executed. execute
the WREN command each time a PP command is executed.
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CHAPTER 2: VFLASH Memory
5. Explanation of Operations
F L A S H
5.3
P R O G R A M M I N G
M A N U A L
Read Mode
This section explains the read mode setting and how to read data for VFLASH performed in this mode.
HS_SPI Controller Setting
In order to set the HS_SPI controller to read mode, perform the following settings for the HS_SPI peripheral
communication set registers (HSSPIn_PCC0 to 3), set 0 to the CSEN bit of the HS_SPI control register, and
set the HS_SPI controller to command sequencer mode.
−
−
−
−
−
Clock division ratio setting bit (CDRS): 1 or more (set 1 or more depending on the operation clock)
Endian set bit (SENDIAN): 1
Serial data transmission/reception timing set bit (ACES): 1
Serial clock polarity set bit (CPOL): 0
Clock phase set bit (CPHA): 0
Then, perform settings of the HS_SPI command sequencer set register (HSSPIn_RDCSDC0 to 7) in
accordance of command transmission/reception sequence
of the FRQIO command.
Note:
−
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CONFIDENTIAL
For details of the setting for the HS_SPI controller, refer to Peripheral Manual.
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 2: VFLASH Memory
5. Explanation of Operations
F L A S H
5.3.1
P R O G R A M M I N G
M A N U A L
Reading the VFLASH Memory
This section explains how to read the VFLASH memory.
Figure 5-4 Flow Chart of Read the VFLASH Memory
Reading VFLASH memory
Currently set to
read mode?
Yes
No
Set to read mode
Perform read access to the address
where the VFLASH memory is allocated
Perform reading
operation for
another area?
Yes
No
Reading completed
1. Set to the read mode before starting reading.
2. To the address where the VFLASH memory is allocated, perform read access from peripherals, such as
CPU and DMA controller.
3. In order to perform reading another area, return to step 2 to repeat the procedure.
Note:
−
For details of the address where the VFLASH memory is allocated, refer to the data sheet.
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CHAPTER 2: VFLASH Memory
5. Explanation of Operations
F L A S H
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P R O G R A M M I N G
M A N U A L
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 3: Flash Security
The flash security function protects contents of the MainFlash memory.
This section describes the overview and operations of the flash security.
1. Overview
2. Operation Explanation
Code: S6E2DH_SECURITY-E01.0
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CHAPTER 3: Flash Security
1. Overview
F L A S H
1.
P R O G R A M M I N G
M A N U A L
Overview
This section explains the overview of the flash security.
If the protection code of 0x0001 is written in the security code area of MainFlash memory, access to the
MainFlash memory is restricted. Once the flash memory is protected, performing the flash erase operation
only can unlock the function otherwise read/write access to the MainFlash memory from any external pins is
not possible.
This function is suitable for applications requiring security of self-containing program and data stored in the
flash memory.
Table 1-1 shows the address and the protection code of the security code.
Table 1-1 Address of Security Code and Protection Code
80
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Address
Protection Code
0x0040_0000
0x0001
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 3: Flash Security
2. Operation Explanation
F L A S H
2.
P R O G R A M M I N G
M A N U A L
Operation Explanation
This section explains the operation of the flash security.
Setting Security
Write the protection code 0x0001 in address of the security code. The security is enabled and set after all
the reset factors are generated or after turning on the power again.
Releasing Security
1. Issue the flash erase command to the Flash Macro.
2. The security is released by all the reset factors or power-on after the execution of flash erase.
Operation with Security Enabled
The operations with security enabled vary depending on each mode.
Table 2-1 shows the security operations in each mode.
Table 2-1 Flash Operation with Security Enabled
Mode
Access to flash
Mode pin
Access from
MD[1:0]
Flash Erase
Other Commands
Read
JTAG Pins
User mode
00
Enabled
Enabled
Valid data
Disabled
Serial writer mode
01
Enabled
Disabled
Invalid data
Disabled
Notes:
−
−
Writing the protection code is generally recommended to take place at the end of the flash
programming.
This is to avoid unnecessary protection during the programming.
In user mode, there is no limit to flash memory even during security is enabled. However, JTAG pins
are fixed not to access internally from these pins during security is enabled. To release security,
perform the flash erase operation using a serial writer because the security cannot be released
through JTAG pins.
−
−
When security enabled, the obstruction analysis of the flash memory cannot be performed.
VFLASH memory is not a security feature.
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CHAPTER 3: Flash Security
2. Operation Explanation
F L A S H
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P R O G R A M M I N G
M A N U A L
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 4: Serial Programming Connection
This series supports serial onboard write (Spansion standard) to flash memory. This chapter explains the
basic configuration for serial write to flash memory by using the Spansion Serial Programmer.
1. Serial Programmer
Code : S6E2DH_FSP-E01.0
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CHAPTER 4: Serial Programming Connection
1. Serial Programmer
F L A S H
1.
P R O G R A M M I N G
M A N U A L
Serial Programmer
Spansion Serial Programmer (software) is an onboard programming tool for all microcontrollers with built-in
flash memory.
Two types of Serial Programmer are available according to the PC interface (RS-232C or USB) used.
Choose the type according to your environment.
Onboard write is possible with the product which USB function is installed by connecting the PC and
microcontroller directly without performing USB-serial conversion.
1.1. Basic Configuration
1.2. Pins Used
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CHAPTER 4: Serial Programming Connection
1. Serial Programmer
F L A S H
1.1
P R O G R A M M I N G
M A N U A L
Basic Configuration
This section explains the basic configuration.
Basic Configuration of Spansion MCU Programmer (Clock Asynchronous Serial Write)
Spansion MCU Programmer writes data, through clock asynchronous serial communication, to built-in flash
memory of a microcontroller installed in the user system when the PC and the user system are connected
through RS-232C cable.
In these series, serial programming (UART communication mode) is possible by any clock, crystal
oscillator or external clock or built-in High-speed CR oscillator.
Figure 1-1 shows the basic configuration of Spansion MCU Programmer, and Table 1-1 lists the system
configuration.
Figure 1-1 Basic Configuration of Spansion MCU Programmer
*
User system
RS-232C
* : RS-232C driver IC is required separately
Table 1-1 System Configuration of Spansion MCU Programmer
Name
Software
MCU Programmer
(In case you request the data, contact to Spansion sales representatives.)
RS-232C cable
Sold on the market.
February 2, 2015, S6E2DH_MN709-00013-1v0-E
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Specifications
Spansion
85
CHAPTER 4: Serial Programming Connection
1. Serial Programmer
F L A S H
P R O G R A M M I N G
M A N U A L
Connection Example of Spansion MCU Programmer
The following shows a connection example of Spansion MCU Programmer.
 When Crystal oscillator is used as the source oscillation clock
Figure 1-2 shows a connection example of Spansion MCU Programmer when a crystal oscillator is used as
a source oscillation clock and Table 1-2 available frequencies and communication baud rates.
Figure 1-2 Connection Example when Crystal Oscillator is Used
User system
Source
oscillation
clock
VCC
MD1
Serial write: 0
10 kΩ
Serial write: 1
●
●
X0
●
X1
●
MD0
●
Device
INITX
10kΩ
10 kΩ
RS-232C
driver
Serial write at UART
communication mode: 0
10 kΩ
DNU0
●
●
●
●
P60
DNU1
*1
10 kΩ
●
P22/SIN0_0
P23/SOT0_0
RS-232C
VSS
Note: The pull-up resistance values shown are for example. Select the most appropriate resistance values for each system.
*1: The correspondence becomes VFLASH memory Products with only.
Table 1-2 Oscillating Frequency and Communication Baud Rate Available for Clock Asynchronous Serial
Communication
Source Oscillating Frequency
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Communication Baud Rate
4 MHz
9600 bps
8 MHz
19200 bps
16 MHz
38400 bps
S6E2DH_MN709-00013-1v0-E, February 2, 2015
CHAPTER 4: Serial Programming Connection
1. Serial Programmer
F L A S H
P R O G R A M M I N G
M A N U A L
 When built-in high-speed CR oscillator is used as a source oscillation clock
Figure 1-3 shows a connection example of Spansion MCU Programmer when a built-in high-speed CR
oscillator is used as a source oscillation clock.
When neither crystal oscillator nor external clock is connected to X0/X1 pins, the built-in high-speed CR
oscillator is connected for communication.
The communication baud rate is 9600[bps] when built-in high-speed CR oscillator is used
The following are the restrictions when built-in high-speed CR oscillator is used
− Because the oscillation frequency of the built-in high-speed CR oscillator would fluctuate due to
temperature and voltage change, the allowable baud rate error range might be exceeded.
− For using the built-in high-speed CR oscillator, see "Built-in CR Oscillation Specifications" in data
sheet of the product used.
Figure 1-3 Connection Example When Built-in High-speed CR Oscillator is Used
User system
VCC
MD1
Serial write: 0
10 kΩ
Serial write: 1
●
●
MD0
●
Device
INITX
10kΩ
10 kΩ
Serial write at UART
RS-232C
driver
communication mode: 0
10 kΩ
DNU0
●
●
●
P60
DNU1
●
*1
10 kΩ
●
P22/SIN0_0
P23/SOT0_0
RS-232C
VSS
Note: The pull-up resistance values shown are for example. Select the most appropriate resistance values for each system.
*1: The correspondence becomes VFLASH memory Products ith only.
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CHAPTER 4: Serial Programming Connection
1. Serial Programmer
F L A S H
P R O G R A M M I N G
M A N U A L
Basic Configuration of Spansion USB DIRECT Programmer (USB Serial Write)
Spansion USB DIRECT Programmer writes data, through USB communication mode, to built-in flash
memory of a microcontroller when the PC and the user system are connected through a USB cable.
Figure 1-4 shows the basic configuration of Spansion USB DIRECT Programmer, and Table 1-3 lists the
system configuration.
Figure 1-4 Basic Configuration of Spansion USB DIRECT Programmer
USB serial communication
USB
User system
Table 1-3 System Configuration of Spansion USB DIRECT Programmer
Name
Specifications
Spansion USB DIRECT
Software
Programmer
(In case you request the data, contact to Spansion sales representatives.)
USB cable
Sold on the market.
For connection examples, see the manual (help section) of Spansion USB DIRECT Programmer.
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CHAPTER 4: Serial Programming Connection
1. Serial Programmer
F L A S H
P R O G R A M M I N G
M A N U A L
Figure 1-5 Connection Example Using Spansion USB DIRECT Programmer
User system
VCC
4MHz
MD1
Serial write: 0
10 kΩ
●
Serial write: 1
●
X0
●
X1
●
MD0
●
Device
Serial write: “0”
P23/SOT0_0
●
●
10 kΩ
USB
connector
INITX
10kΩ
Level
Vbus
Shifter
D27 Ω
DNU0
51kΩ
DNU1
*1
UDM0
3.3 V
100 kΩ
●
P61/UHCONX
10 Ω
1.5 kΩ
D+
●
P60
●
UDP0
●
27 Ω
GND
●
VSS
Note: It is a connection example when VCC=3.3 V. Insert a level shifter for each system. The pull-up and pull-down resistance
values shown are for example. Select the most appropriate resistance values for each system.
*1: The correspondence becomes VFLASH memory Products only.
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CHAPTER 4: Serial Programming Connection
1. Serial Programmer
F L A S H
1.2
P R O G R A M M I N G
M A N U A L
Pins Used
This section explains the used pins.
Table 1-4 Pins Used for Serial Write
Pins
Function
Supplement
Performing an external reset or turning on the power after setting MD0=H and MD1=L
MD0, MD1
Mode pin
enters the serial write mode.
When attaching a pull-up or pull-down resistor, avoid long wiring.
See the data sheet for the source oscillation clock (main clock) frequencies that can
X0, X1
Oscillation pin
be used in serial write mode.
(Restrictions apply to clock asynchronous communication. For details, see Table 1-2.)
P23/SOT0_0
UART serial data output pin/
USB select pin
When the communication mode is set to UART, this pin becomes a serial data output
pin when communication begins after the serial write mode is activated.
Setting this pin to L enables the USB communication mode .
Setting the input level of this pin to H until the start of communication enables the
P22/SIN0_0
Clock synchronous/
clock asynchronous communication mode, and setting it to L enables the clock
asynchronous select pin/UART
synchronous communication mode. When the communication mode is set to UART,
serial data input pin
this pin can be used as a serial data input pin when communication begins after the
serial write mode is activated.
The communication mode is determined by the input level of this pin at reset to shift to
P60
Communication mode select
the serial write mode.
pin
Setting this pin to H enables the USB communication mode, and setting it to L
enables the UART communication mode.
This pin controls the pull-up of USB side (D+) when the communication mode is USB.
P61/UHCONX
Pull-up control pin for UDP0
UHCONX=L: Connect the pull-up resistor
UHCONX=H: Disconnect the pull-up resistor
UDP0
USB I/O pin
UDM0
USB I/O pin
INITX
Reset pin
VCC
Power supply pin
VSS
GND pin
DNU0,1
-
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This pin becomes an input/output pin of USB side (D+) when the communication
mode is set to USB.
This pin becomes an input/output pin of USB side (D-) when the communication
mode is set to USB.
For writing, supply power to the microcontroller from the user system.
-
DNU0,1 please go to pull up on the order of shorted 10 KΩ.
The correspondence becomes VFLASH memory Products ith only.
S6E2DH_MN709-00013-1v0-E, February 2, 2015
F L A S H
P R O G R A M M I N G
M A N U A L
Major Changes
Page
Section
Changes
Revision 1.0
-
-
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Initial release
91
F L A S H
92
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P R O G R A M M I N G
M A N U A L
S6E2DH_MN709-00013-1v0-E, February 2, 2015
F L A S H
P R O G R A M M I N G
M A N U A L
MN709-00013-1v0-E
Spansion・Controller Manual
S6E2DH/DF/D5/D3 Series
32-BIT MICROCONTROLLER
FM4 Family
FLASH PROGRAMMING MANUAL
February 2015 Rev. 1.0
Published : Spansion Inc.
Edited
: Communications Dept.
February 2, 2015, S6E2DH_MN709-00013-1v0-E
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93
F L A S H
P R O G R A M M I N G
M A N U A L
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control,
mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where
chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions. If any products described in this document
represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law
of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the
respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion
product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without
notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,
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warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of
the information in this document.
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Copyright © 2015 Spansion All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit Eclipse ,
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LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks
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