SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 D D D D D D D D D D Meets IEEE Standard 488-1978 (GPIB) 8-Channel Bidirectional Transceiver Power-Up/Power-Down Protection (Glitch Free) High-Speed, Low-Power Schottky Circuitry Low Power Dissipation . . . 72 mW Max Per Channel Fast Propagation Times . . . 22 ns Max High-Impedance pnp Inputs Receiver Hysteresis . . . 650 mV Typ Open-Collector Driver Output Option No Loading of Bus When Device Is Powered Down (VCC = 0) DW OR N PACKAGE (TOP VIEW) GPIB I/O Ports TE B1 B2 B3 B4 B5 B6 B7 B8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC D1 D2 D3 D4 D5 D6 D7 D8 PE Terminal I/O Ports description The SN75160B 8-channel general-purpose interface bus (GPIB) transceiver is a monolithic, high-speed, low-power Schottky device designed for two-way data communications over single-ended transmission lines. It is designed to meet the requirements of IEEE Standard 488-1978. The transceiver features driver outputs that can be operated in either the passive-pullup or 3-state mode. If talk enable (TE) is high, these ports have the characteristics of passive-pullup outputs when pullup enable (PE) is low and of 3-state outputs when PE is high. Taking TE low places these ports in the high-impedance state. The driver outputs are designed to handle loads up to 48 mA of sink current. Output glitches during power up and power down are eliminated by an internal circuit that disables both the bus and receiver outputs. The outputs do not load the bus when VCC = 0. When combined with the SN75161B or SN75162B management bus transceivers, the pair provides the complete 16-wire interface for the IEEE-488 bus. The SN75160B is characterized for operation from 0°C to 70°C. Function Tables EACH DRIVER INPUTS EACH RECEIVER OUTPUT D TE PE B H H H L H X H X X L INPUTS OUTPUT B TE PE D H L L X L H L X H L L Z† X H X Z X Z† H = high level, L = low level, X = irrelevant, Z = high impedance † This is the high-impedance state of a normal 3-state output modified by the internal resistors to VCC and GND. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 logic symbol† PE TE 11 1 logic diagram (positive logic) PE M1[3S] M2[0C] TE D3 D4 D5 D6 D7 D8 D1 19 19 3(1 4 D2 1 EN3[XMT] EN4[RCV] D1 11 /2 ) 2 2 B1 1 18 3 17 4 16 5 15 6 14 7 13 8 12 9 D2 B2 18 B3 3 B4 B5 D3 B6 B2 17 B7 4 B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Designates 3-state outputs Designates passive-pullup outputs D4 5 GPIB I/O Ports • DALLAS, TEXAS 75265 B7 12 9 POST OFFICE BOX 655303 B6 13 8 D8 B5 14 7 D7 B4 15 6 D6 B3 16 Terminal I/O Ports D5 2 B1 B8 SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 schematics of inputs and outputs EQUIVALENT OF ALL CONTROL INPUTS VCC EQUIVALENT OF ALL INPUT/OUTPUT PORTS R(eq) 9 kΩ NOM 1.7 kΩ NOM 10 kΩ NOM Input 4 kΩ NOM 4 kΩ NOM GND Input /Output Port Driver output R(eq) = 30 Ω NOM Receiver output R(eq) = 110 Ω NOM Circuit inside dashed lines is on the driver outputs only. R(eq) = equivalent resistor absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Low-level driver output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to network ground terminal. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING DW 1125 mW 9.0 mW/°C 720 mW N 1150 mW 9.2 mW/°C 736 mW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 recommended operating conditions Supply voltage, VCC High-level input voltage, VIH MIN NOM MAX UNIT 4.75 5 5.25 V 2 V Low-level input voltage, VIL High level output current, High-level current IOH Low level output current, Low-level current IOL 0.8 V Bus ports with pullups active – 5.2 mA Terminal ports – 800 µA Bus ports 48 Terminal ports 16 Operating free-air temperature, TA 0 70 mA °C electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIK Input clamp voltage Vhys Hysteresis voltage (VIT + – VIT –) VOH High level output voltage High-level VOL Low level output voltage Low-level II TEST CONDITIONS II = – 18 mA Bus See Figure 8 Terminal IOH = – 800 µA, IOH = – 5.2 mA, IOL = 16 mA, IOL = 48 mA, TE at 0.8 V Bus Input current at maximum input voltage Terminal IIH IIL High-level input current Terminal Low-level input current Terminal VI/O(b I/O(bus)) Voltage at bus port Bus Terminal Current into bus port V TE at 0.8 V 2.7 3.5 PE and TE at 2 V 2.5 3.3 V V 0.3 0.5 0.5 VI = 5 5.5 5V 02 0.2 100 µA VI = 2.7 V VI = 0.5 V 0.1 20 µA – 10 – 100 µA Driver disabled TE at 2 V II(bus) = 0 II(bus) = – 12 mA VCC = 0, 2.5 3.0 3.7 – 1.5 0 2.5 VI(b 2.5 5 V to 3 3.7 7V I(bus)) = 2 – 3.2 0 2.5 0.7 2.5 – 35 – 75 Bus – 25 – 50 – 125 Supply current No load CI/O(bus) I/O(b ) Bus port capacitance Bus-port VCC = 0 to 5 V, f = 1 MHz Receivers low and enabled 70 90 Drivers low and enabled 85 110 VI/O = 0 to 2 V, 16 † All typical values are at VCC = 5 V, TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA – 40 – 15 ICC V – 3.2 VI(bus) = 0 to 2.5 V Short circuit output current Short-circuit V – 1.3 Terminal IOS 4 UNIT – 1.5 0.65 VI(bus) = 3.7 V to 5 V VI(bus) = 5 V to 5.5 V Power off MAX – 0.8 0.35 Driver disabled Power on TYP† 0.4 VI(bus) = – 1.5 V to 0.4 V VI(bus) = 0.4 V to 2.5 V II/O(bus) ( ) MIN mA mA pF SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C (unless otherwise noted) PARAMETER tPLH Propation delay time, low- to high-level output tPHL Propagation delay time, high- to low-level output tPLH Propagation delay time, low- to high-level output tPHL FROM (INPUT) TO (OUTPUT) TEST CONDITIONS Terminal Bus CL = 30 pF, See Figure 1 Bus Terminal Propagation delay time, high- to low-level output CL = 30 pF, See Figure 2 MIN TYP MAX 14 20 14 20 10 20 15 22 ns ns tPZH tPHZ Output enable time to high level 25 35 Output disable time from high level 13 22 tPZL tPLZ Output enable time to low level 22 35 Output disable time from low level 22 32 tPZH tPHZ Output enable time to high level 20 30 Output disable time from high level 12 20 tPZL tPLZ Output enable time to low level 23 32 Output disable time from low level 19 30 ten tdis Output pullup enable time 15 22 13 20 Output pullup disable time TE TE PE POST OFFICE BOX 655303 BUS Terminal Bus See Figure 3 See Figure 4 See Figure 5 • DALLAS, TEXAS 75265 UNIT ns ns ns 5 SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 PARAMETER MEASUREMENT INFORMATION 5V 3V PE 200 Ω Output 3V D Input Generator (see Note A) D 1.5 V 1.5 V B 0V 480 Ω 50 Ω CL = 30 pF (see Note B) tPLH B Output tPHL VOH 2.2 V 1.0 V VOH TE VOLTAGE WAVEFORMS 3V TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 1. Terminal-to-Bus Test Circuit and Voltage Waveforms TE 4.3 V Output 240 Ω Generator (see Note A) B 3V B Input D 1.5 V 1.5 V 0V tPLH tPHL VOH 50 Ω CL = 30 pF (see Note B) 3 kΩ D Output 1.5 V 1.5 V VOH VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 PARAMETER MEASUREMENT INFORMATION 5V 3V 3V 200 Ω Output PE S1 D TE Input S2 B CL = 30 pF (see Note B) Generator (see Note A) 1.5 V 90% TE 50 Ω VOH 2V 0.8 V tPLZ tPZL B Output S1 to GND S2 Closed 0V tPHZ tPZH B Output S1 to 3 V S2 Open 480 Ω 1.5 V 3.5 V 1.0 V 0.5 V VOL VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms 4.3 V TE Generator (see Note A) S2 Output 240 Ω 50 Ω D 3V S1 3 kΩ CL = 15 pF (see Note B) B TEST CIRCUIT 3V TE Input 1.5 V 1.5 V 0V tPHZ tPZH D Output S1 TO 3 V S2 Open 90% 0V tPLZ tPZL D Output S1 TO GND S2 Closed VOH 1.5 V 4V 1.0 V 0.7 V VOL VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 4. TE-to-Terminal Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 PARAMETER MEASUREMENT INFORMATION Generator (see Note A) 50 Ω PE Output D 3V PE Input B 1.5 V 1.5 V 0V RL = 480 Ω CL = 15 pF (see Note B) ten B Output tdis 90% VOH 2V VOL = 0.8 V 3V VOLTAGE WAVEFORMS TE TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 5. PE-to-Bus Pullup Test Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 TYPICAL CHARACTERISTICS TERMINAL I/O PORTS TERMINAL I/O PORTS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 4 0.6 3.5 3 2.5 2 1.5 1 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VCC = 5 V TA = 25°C VOL VOL – Low-Level Output Voltage – V VCC = 5 V TA = 25°C 0.5 0.4 0.3 0.2 0.1 0.5 0 0 0 –5 – 10 – 15 – 20 – 25 – 30 – 35 0 – 40 10 20 30 40 50 60 IOL – Low-Level Output Current – mA IOH – High-Level Output Current – mA Figure 6 Figure 7 TERMINAL I/O PORTS OUTPUT VOLTAGE vs BUS INPUT VOLTAGE ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 4 VCC = 5 V No Load TA = 25°C 3.5 VO VO – Output Voltage – V VOH – High-Level Output Voltage – V VOH LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3 2.5 2 VIT– VIT+ 1.5 1 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VI – Bus Input Voltage – V Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004B – OCTOBER 1985 – REVISED MAY 1995 TYPICAL CHARACTERISTICS GPIB I/O PORTS GPIB I/O PORTS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT V VOH OH – High-Level Output Voltage – V VCC = 5 V TA = 25°C 3 2 1 0.6 VOL – Low-Level Output Voltage – V VOL ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0 0 0 – 10 – 20 – 40 – 30 – 50 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VCC = 5 V TA = 25°C 0.5 0.4 0.3 0.2 0.1 0 – 60 0 10 IOH – High-Level Output Current – mA 20 Figure 9 40 60 GPIB I/O PORTS GPIB I/O PORTS OUTPUT VOLTAGE vs THERMAL INPUT VOLTAGE CURRENT vs VOLTAGE ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ VCC = 5 V No Load TA = 25°C 2 1 ÎÎÎÎ ÎÎÎÎ 70 80 90 100 VCC = 5 V TA = 25°C I I/O – Current – mA 3 2 1 0 –1 –2 –3 –4 –5 0 0.9 –7 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 ÎÎÎÎÎÎÎÎ ÁÁÁÁÁÁÁÁ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁÁÁ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁÁÁ ÎÎÎÎÎÎÎÎ ÁÁÁÁÁÁÁÁ ÎÎÎÎÎÎÎÎ The Unshaded Area Conforms to Paragraph 3.5.3 of IEEE Standard 488-1978 –6 –2 –1 0 1 2 Figure 11 Figure 12 POST OFFICE BOX 655303 3 VI/O – Voltage – V VI – Thermal Input Voltage – V 10 50 Figure 10 4 V VO O – Output Voltage – V 30 IOL – Low-Level Output Current – mA • DALLAS, TEXAS 75265 4 5 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated