APL5536

APL5536
Dual Channel 300mA Low Dropout Linear Regulator
Features
General Description
•
Dual Regulator Outputs
•
Low Dropout Voltage: Typical 270mV at 300mA
The APL5536 is a dual channel low dropout linear
regulator, which operates from 2.5V to 5.5V input voltage
•
Wide Input Voltage Range: 2.5V to 5.5V
•
Low Quiescent Current: Typical 68µA
•
High PSRR: 70dB at 1kHz
•
Low Shutdown Current: <1µA
•
Shutdown Function
•
Output Current-Limit Protection
•
Short-Circuit Current-Limit Protection
current-limit protection to ensure specified output current.
The APL5536 is available in SOT-23-6, TSOT-23-6A, and
•
Over-Temperature Protection
TDFN1.6x1.6-6 packages.
•
Lead Free and Green Devices Available
and delivers up to 300mA output current at each channel.
Typical dropout voltage is only 270mV at 300mA.
The APL5536 with low quiescent current, high PSRR, and
low noise is ideal for battery powered system appliances.
Other features include logic-controlled shutdown mode,
over-temperature protection, short-circuit current-limit, and
Pin Configuration
(RoHS Compliant)
Applications
EN1 1
VIN 2
•
Mobile Phone
•
NB Cam
•
Blue Tooth Headset
EN2 3
6 VOUT1 VOUT1 1
5 GND
GND 2
4 VOUT2 VOUT2 3
SOT-23-6/TSOT-23-6A
(Top View)
6 EN1
5 VIN
4 EN2
TDFN1.6x1.6-6
(Top View)
Ordering and Marking Information
APL5536
VOUT1/VOUT2 Voltage Code
See Available Voltage Version
Package Code
C : SOT-23-6 CT : TSOT-23-6A QB : TDFN1.6x1.6-6
Operating Ambient Temperature Range
I : -40 to 85oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Assembly Material
Handling Code
Temperature Range
Package Code
VOUT2 Voltage Code
VOUT1 Voltage Code
APL5536 C/CT:
6VVX
VV - Voltage Code
X - Date Code
APL5536 QB:
6VV
X
VV - Voltage Code
X - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2010
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APL5536
Available Voltage Version
Code
5
7
9
A
C
b
D
E
F
J
K
Voltage
1.20
1.30
1.50
1.60
1.80
1.85
1.90
2.00
2.10
2.50
2.60
Code
c
L
M
d
N
O
P
e
Q
R
Voltage
2.65
2.70
2.80
2.85
2.90
3.00
3.10
3.15
3.20
3.30
Absolute Maximum Ratings
Symbol
VIN
VEN1, VEN2
TJ
TSTG
TSDR
(Note 1)
Parameter
Rating
Unit
VIN Input Voltage (VIN to GND)
-0.3 ~ 7
V
EN1, EN2 to GND Voltage
-0.3 ~ 7
Maximum Junction Temperature
Storage Temperature
Maximum Lead Soldering Temperature, 10 Seconds
V
150
o
-65 ~ 150
o
260
o
C
C
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
θJA
Parameter
Junction-to-Ambient Resistance in Free Air
Typical Value
Unit
(Note 2)
SOT-23-6/TSOT-23-6A
TDFN1.6x1.6-6
o
C/W
220
165
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions
Symbol
VIN
VEN1, VEN2
(Note 3)
Parameter
VIN Input Voltage (VIN to GND)
EN1, EN2 to GND Voltage
Range
Unit
2.5 ~ 5.5
V
0 ~ 5.5
V
mA
IOUT
VOUT Output Current
0 ~ 300
TA
Ambient Temperature
-40 ~ 85
o
-40 ~ 125
o
TJ
Junction Temperature
C
C
Note 3: Refer to the typical application circuit.
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=VOUT+1V, VEN1= VEN2=5V and TA= -40 to 85 oC. Typical values are at
TA=25oC.
Symbol
Parameter
APL5536
Test Conditions
Min.
Unit
Typ.
Max.
1.9
2.2
2.45
V
-
0.1
-
V
UNDER-VOLTAGE LOCKOUT (UVLO) AND SUPPLY CURRENT
VIN UVLO Threshold Voltage
VIN rising, TA= -40 to 85 oC
VIN UVLO Hysteresis
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APL5536
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VIN=VOUT+1V, VEN1= VEN2=5V and TA= -40 to 85 oC. Typical values are
at TA=25oC.
Symbol
Parameter
APL5536
Test Conditions
Unit
Min.
Typ.
Max.
No load, VEN1=VEN2=5V
-
68
100
µA
No load, VEN1=VEN2=0V
-
-
1
µA
UNDER-VOLTAGE LOCKOUT (UVLO) AND SUPPLY CURRENT (CONT.)
IQ
VIN Supply Current
OUTPUT VOLTAGE (REGULATOR1 AND REGULATOR2)
VDROP
PSRR
Output Voltage Accuracy
IOUT=1mA to 300mA, TA=-40oC to 85oC
-3.5
-
+3.5
%
Line Regulation
IOUT=1mA, VIN=VOUT+0.3V to 5.5V, or
VIN=2.5V to 5.5V
-
-
0.2
%/V
Dropout Voltage (Note 4)
IOUT=300mA
-
270
350
mV
f=100Hz
-
70
-
f=1kHz
-
70
-
f=10kHz
-
60
-
f=100kHz
-
35
-
100
-
µVRMS
Power Supply Rejection Ratio
IOUT=50mA, COUT=2.2µF
dB
Output Noise
IOUT=1mA, BW=10 to 100kHz, COUT=10µF
-
VOUT Discharge Resistance
VEN1=VEN2=0V
-
1
-
kΩ
ENABLE/DISABLE (EN1 AND EN2)
VIH
EN Input Logic HIGH
VIN=2.5V to 5.5V
1.5
-
-
V
VIL
EN Input Logic LOW
VIN=2.5V to 5.5V
-
-
0.4
V
EN Input Current
VEN1=VEN2=5V
-
10
-
µA
330
450
750
mA
-
mA
PROTECTIONS (REGULATOR1 AND REGULATOR2)
ILIMIT
Current-Limit Threshold
ISHORT
Short-Circuit Output Current
-
50
Over-Temperature Threshold
-
160
-
°C
Over-Temperature Hysteresis
-
40
-
°C
Soft-Start Time
-
60
-
µs
Note 4: The dropout voltage is defined as VIN - VOUT, when VOUT is 100mV below the value of VOUT for VIN = VOUT + 1V.
Copyright  ANPEC Electronics Corp.
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APL5536
Typical Operating Characteristics
Ch1 Output Voltage vs.Temperature
Ch2 Output Voltage vs.Temperature
1.505
2.81
2.8
Output Voltage (V)
Output Voltage (V)
1.5
1.495
1.49
2.79
2.78
2.77
1.485
2.76
1.48
-40 -20
0
20
40
60
80 100 120 140
-40 -20
Junction Temperature ( oC)
Dropout Voltage vs. Output Current
PSRR vs. Frequency
0.00
350
TJ=125oC
300
-10.00
-20.00
250
TJ=25oC
PSRR (dB)
Dropout Voltage (mV)
0 20 40 60 80 100 120 140
Junction Temperature ( oC)
200
150
-30.00
-40.00
CH2
-50.00
TJ=-40oC
100
-60.00
50
CH1
-70.00
-80.00
100
0
0
50
100
150
200
250
300
1K
10K
100K
1M
Frequency (Hz)
Output Current (mA)
Noise
150
100
Noise (µV)
50
0
-50
-100
-150
-200
0
20m
40m
60m
80m
100m
Time (sec)
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APL5536
Operating Waveforms
Refer to the typical application circuit. The test condition is TA= 25oC unless otherwise specified.
Power On
Power Off
V IN
VIN
1
1
V OUT1
2
2
VOUT1
ENB
VOUT2
VOUT2
3
3
APL5536CC, VIN=4V, IOUT1=IOUT2=10mA,
CIN=COUT1=COUT2=1µF/MLCC, EN1/EN2 tied to VIN
CH1: VIN, 2V/Div, DC
CH2: VOUT1, 1V/Div, DC
CH3: VOUT2, 1V/Div, DC
TIME: 20ms/Div
APL5536CC, VIN=4V, IOUT1=IOUT2=10mA,
CIN=COUT1=COUT2=1µF/MLCC, EN1/EN2 tied to VIN
CH1: VIN, 2V/Div, DC
CH2: VOUT1, 1V/Div, DC
CH3: VOUT2, 1V/Div, DC
TIME: 100µs/Div
Enable Response
Disable Response
V E N 1/VEN2
VE N 1/V E N 2
1
2
1
VOUT1
VOUT2
VOUT1
2
VOUT2
3
3
APL5536CC, VIN=4V, IOUT1=IOUT2=10mA,
CIN=COUT1=COUT2=1µF/MLCC
CH1: VEN1/VEN2, 2V/Div, DC
CH2: VOUT1, 1V/Div, DC
CH3: VOUT2, 1V/Div, DC
TIME: 50µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2010
APL5536CC, VIN=4V, IOUT1=IOUT2=10mA,
CIN=COUT1=COUT2=1µF/MLCC
CH1: VEN1/VEN2, 2V/Div, DC
CH2: VOUT1, 1V/Div, DC
CH3: VOUT2, 1V/Div, DC
TIME: 50µs/Div
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APL5536
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is TA= 25oC unless otherwise specified.
Channel 1 Load Transient Response
Channel 2 Load Transient Response
VOUT
VOUT
1
1
IOUT
IOUT
2
2
APL5536CC, VIN=4V, ILOAD=10-300-10mA, rising/
falling=0.4µs, CIN=COUT=1µF/MLCC
APL5536CC, VIN=4V, ILOAD=10-300-10mA, rising/
falling=0.4µs, CIN =COUT=1µF/MLCC
CH1: VOUT, 100mV/Div, offset=1.8V
CH2: IOUT, 200mA/Div, DC
CH1: VOUT, 100mV/Div, offset=1.8V
CH2: IOUT, 200mA/Div, DC
TIME: 20µs/Div
TIME: 20µs/Div
Line Transient Response-1
Line Transient Response-2
VIN
V IN
1
1
VOUT1
V OUT1
2
2
VOUT2
V OUT2
3
3
APL5536CC, VIN=3.8V to 4.8V to 3.8V (rising/falling
time=4µs), ILOAD=10mA, CIN=COUT=1µF/MLCC
CH1: VIN, 500mV/Div, offset=3.8V
CH2: VOUT1, 20mV/Div, offset=1.8V
CH3: VOUT2, 20mV/Div, offset=1.8V
APL5536CC, VIN=3.8V to 4.8V to 3.8V(rising/falling
time=4µs), ILOAD=100mA, CIN=COUT=1µF/MLCC
CH1: VIN, 500mV/Div, offset=3.8V
CH2: VOUT1, 20mV/Div, offset=1.8V
CH3: VOUT2, 20mV/Div, offset=1.8V
TIME: 100µs/Div
TIME: 100µs/Div
Copyright  ANPEC Electronics Corp.
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APL5536
Pin Description
PIN
NO.
FUNCTION
NAME
SOT-23-6/
TSOT-23-6A
TDFN1.6x1.6-6
1
6
EN1
Enable Input. Pulling the VEN1 above 1.5V enables the respective regulator output;
pulling VEN1 below 0.4V disables the respective regulator output.
2
5
VIN
Input Supply Pin. VIN can range from 2.5V to 5.5V and should be bypassed with at
least a 1µF capacitor.
3
4
EN2
Enable Input. Pulling the VEN2 above 1.5V enables the respective regulator output;
pulling VEN2 below 0.4V disables the respective regulator output.
4
3
VOUT2
Regulator Outputs. Sources up to 300mA. Bypass with at least a 1µF capacitor to the
GND respectively.
5
2
GND
6
1
VOUT1
Ground.
Regulator Outputs. Sources up to 300mA. Bypass with at least a 1µF capacitor to the
GND respectively.
Typical Application Circuit
VIN
2.5V to 5.5V
VIN
VOUT1
VOUT1
COUT1
CIN
1µF
1.2V to 3.6V/300mA
1µF
APL5536
ON
EN1
VOUT2
VOUT2
COUT2
OFF
EN2
1.2V to 3.6V/300mA
1µF
GND
Copyright  ANPEC Electronics Corp.
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APL5536
Block Diagram
VIN
CurrentLimit1
EN1
UVLO and
Shutdown
Control1
VREF1
OverTemperature
Protection
VOUT1
Short-Circuit
Current-Limit1
GND
EN2
CurrentLimit2
UVLO and
Shutdown
Control2
VREF2
OverTemperature
Protection
VOUT2
Short-Circuit
Current-Limit2
Copyright  ANPEC Electronics Corp.
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APL5536
Function Description
VIN Under-Voltage Lockout (UVLO)
Over-Temperature Protection
The APL5536 has a built-in under-voltage lockout circuit
An over-temperature protection circuitry limits the junc-
to keep the outputs shuting off until internal circuitry is
operating properly. The UVLO circuit has a hysteresis
tion temperature of APL5536. When the junction temperature exceeds +160 oC, the over-temperature protection
and a de-glitch feature so that it will typically ignore undershoot transients on the input.
circuitry disables the LDO outputs, allowing the device to
cool down. The LDO outputs are enabled again after the
Soft-Start (For Each Channel)
junction temperature cools down by 40oC, resulting in a
pulsed output during continuous thermal overload
The APL5536 provides an internal soft-start circuitry to
control rise rate of the output voltage and limit the current
conditions. Over-temperature protection is designed to
protect the IC in the event of over temperature conditions.
surge during start-up. The output voltage starts the softstart at approximate 60µs after the VIN is over the UVLO
For reliable operation, the junction temperature cannot
exceed TJ=+125oC
threshold. The typical soft-start interval is about 60µs.
Current-Limit Protection (For Each Channel)
The APL5536 provides a current-limit protection function.
During current-limit, the device limits output current at
current-limit threshold. For reliable operation, the device
should not be operated in current-limit for extended period.
Short-Circuit Current-Limit Protection (For Each
Channel)
When the output voltage drops below 0.8V, which is
caused by the over load or short circuit, the device limits
the output current down to a safe level. The short circuit
current limit is used to reduce the power dissipation during short circuit conditions. If the junction temperature is
over the over-temperature threshold, the device will enter
the thermal shutdown.
Enable/Disable (For Each Channel)
Pulling the VEN1/2 above 1.5V enables the respective LDO
output, and pulling VEN1/2 below 0.4V disables the respective LDO output. EN1/2 pins are internally pulled low by
resistors. If shutdown function is not used, connect EN1/
2 to VIN for normal operation. The enable inputs are compatible with both TTL and CMOS logic levels.
Copyright  ANPEC Electronics Corp.
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APL5536
Application Information
where (TJ - TA) is the temperature difference between the
junction and ambient air. θJA is the thermal resistance
Input Capacitor
The APL5536 requires proper input capacitors to supply
surge current during stepping load transients to prevent
between Junction and ambient air. Assuming the TA=25oC
and maximum TJ=160oC (typical thermal limit threshold),
the input rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to
the maximum power dissipation is calculated as:
PD(max) = (150-25)/220 = 0.568(W)
the VIN limit the slew rate of the surge current, place the
Input capacitors near VIN as close as possible. Input
For normal operation, do not exceed the maximum junction temperature rating of TJ=125oC. The calculated power
capacitors should be larger than 1µF and a minimum
ceramic capacitor of 1µF is necessary.
dissipation should be less than:
PD = (125-25)/220 = 0.454(W)
Output Capacitor
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal resis-
The APL5536 needs a proper output capacitor to maintain circuit stability and improve transient response over-
tance θJA. For SOT-23-6 package, the Figure 2 of derating
curves allows the designer to see the effect of rising
temperature and current. In order to insure the circuit
stability, the proper output capacitor value should be larger
ambient temperature on the maximum power allowed.
The GND provides an electrical connection to the ground
than 1µF. With X5R and X7R dielectrics, 1µF is sufficient
at all operating temperatures. Large output capacitor
and channels heat away. Connect the GND to the ground
by using a large pad or a ground plane.
value can reduce noise and improve load-transient response and PSRR, Figure 1 shows the curves of allow-
0.6
able ESR range as the function of load current for various
output capacitor values.
Power Dissipation (W)
Single Layer PCB
Region of Stable COUT ESR vs. Output Current
Region of Stable COUT ESR (Ω)
10
APL5536-OC
VIN=4V
CIN=COUT=1µF/X7R
1
Unstable Range
0.5
0.4
0.3
0.2
0.1
0
0.1
0
Stable Range
25
50
75
100
125
Ambient Temperature ( oC)
Figure 2. Derating Curves for SOT-23-6 Package
0.01
Layout Consideration
Simulation Verify
0.001
0
50
100
150
200
250
Figure 3 illustrates the layout. Below is a checklist for
300
your layout:
1. Please place the input capacitors close to the VIN.
Output Current (mA)
Figure1. Stable COUT ESR Range
2. Ceramic capacitors for load must be placed near the
load as close as possible.
Operation Region and Power Dissipation
3. To place APL5536 and output capacitors near the load
is good for performance.
The APL5536 maximum power dissipation depends on
the thermal resistance and temperature difference between the die junction and ambient air. The SOT-23-6
4. Large current paths, the bold lines in Figure 3, must
have wide tracks.
package power dissipation PD across the device is:
PD = (TJ - TA) / θJA
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2010
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APL5536
Application Information (Cont.)
Layout Consideration (Cont.)
VIN
VOUT1
VIN
VOUT1
CIN
COUT1
APL5536
ON
EN1
VOUT2
VOUT2
COUT2
OFF
EN2
GND
Figure3. Large Current Paths
Copyright  ANPEC Electronics Corp.
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APL5536
Package Information
SOT-23-6
-T-
D
SEATING PLANE < 4 mils
e
E
E1
SEE VIEW A
b
c
0.25
A
L
0
GAUGE PLANE
SEATING PLANE
A1
A2
e1
VIEW A
S
Y
M
B
O
L
SOT-23-6
MILLIMETERS
MIN.
INCHES
MAX.
A
MAX.
MIN.
0.057
1.45
A1
0.00
0.15
0.000
0.006
A2
0.90
1.30
0.035
0.051
b
0.30
0.50
0.012
0.020
c
0.08
0.22
0.003
0.009
D
2.70
3.10
0.106
0.122
E
2.60
3.00
0.102
0.118
E1
1.40
1.80
0.055
e
0.95 BSC
e1
L
0
0.071
0.037 BSC
1.90 BSC
0.075 BSC
0.30
0.60
0.012
0°
8°
0°
0.024
8°
Note : 1. Follow JEDEC TO-178 AB.
2. Dimension D and E1 do not include mold flash, protrusions or
gate burrs. Mold flash, protrusion or gate burrs shall not exceed
10 mil per side.
Copyright  ANPEC Electronics Corp.
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APL5536
Package Information
TSOT-23-6A
-T-
D
SEATING PLANE < 4mils
e
E
E1
SEE VIEW A
b
c
A
A2
0.25
e1
GAUGE PLANE
SEATING PLANE
A1
L
VIEW A
S
Y
M
B
O
L
TSOT-23-6A
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
1.00
0.028
0.039
A1
0.01
0.10
0.000
0.004
A2
0.70
0.90
0.028
0.035
b
0.30
0.50
0.012
0.020
c
0.08
0.20
0.003
0.008
D
2.70
3.10
0.106
0.122
E
2.60
3.00
0.102
0.118
E1
1.40
1.80
0.055
0.071
e
0.95 BSC
e1
L
0
0.037 BSC
1.90 BSC
0.075 BSC
0.30
0.60
0°
8°
0.012
0.024
0°
8°
Note : Dimension D and E1 do not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil
per side.
Copyright  ANPEC Electronics Corp.
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APL5536
Package Information
TDFN1.6x1.6-6
D
E
A
b
Pin 1
A1
D2
E2
A3
L
K
Pin 1 Corner
e
S
Y
M
B
O
L
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
0.00
0.05
0.000
0.002
0.012
0.065
A1
TDFN1.6x1.6-6
MILLIMETERS
A3
INCHES
0.20 REF
0.008 REF
b
0.20
0.30
0.008
D
1.55
1.65
0.061
D2
0.95
1.05
0.037
0.041
E
1.55
1.65
0.061
0.065
E2
0.55
0.65
0.022
e
0.50 BSC
0.026
0.020 BSC
K
0.20
-
0.008
-
L
0.19
0.29
0.007
0.011
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APL5536
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
SOT-23-6
Application
TSOT-23-6A
Application
TDFN1.6x1.6-6
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.0 MIN.
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.50±0.20
4.0±0.10
4.0±0.10
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.0 MIN.
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.50±0.20
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
1.70±0.20
1.70±0.20
0.90±0.20
4.0±0.10
4.0±0.10
(mm)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2010
15
www.anpec.com.tw
APL5536
Devices Per Unit
Package Type
Unit
Quantity
SOT-23-6
Tape & Reel
3000
TSOT-23-6A
Tape & Reel
3000
TDFN1.6x-1.6
Tape & Reel
3000
Taping Direction Information
SOT-23-6/TSOT-23-6A
USER DIRECTION OF FEED
AAAX
AAAX
AAAX
AAAX
AAAX
AAAX
AAAX
TDFN1.6x1.6-6
USER DIRECTION OF FEED
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2010
16
www.anpec.com.tw
APL5536
Classification Profile
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2010
17
www.anpec.com.tw
APL5536
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Aug., 2010
18
www.anpec.com.tw