IDT71128 CMOS Static RAM 1 Meg (256K x 4-Bit) Revolutionary Pinout Features Description ◆ The IDT71128 is a 1,048,576-bit high-speed static RAM organized as 256K x 4. It is fabricated using IDT’s high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The JEDEC centerpower/GND pinout reduces noise generation and improves system performance. The IDT71128 has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns available. All bidirectional inputs and outputs of the IDT71128 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. The IDT71128 is packaged in a 32-pin 400 mil Plastic SOJ. ◆ ◆ ◆ ◆ ◆ ◆ 256K x 4 advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/GND) for reduced noise. Equal access and cycle times — Commercial and Industrial: 12/15/20ns One Chip Select plus one Output Enable pin Bidirectional inputs and outputs directly TTL-compatible Low power consumption via chip deselect Available in a 32-pin 400 mil Plastic SOJ. Functional Block Diagram A0 1,048,576-BIT ADDRESS MEMORY DECODER ARRAY . A17 I/O0 - I/O3 CS WE OE 4 4 I/O CONTROL CONTROL LOGIC 3483 drw 01 FEBRUARY 2001 1 ©2000 Integrated Device Technology, Inc. DSC-3483/09 IDT71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Pin Configuration NC A0 A1 A2 A3 CS I/O0 VCC GND I/O1 WE A4 A5 A6 A7 NC 1 32 2 31 3 30 4 29 5 28 6 SO32-3 27 7 26 8 25 24 9 23 10 22 11 21 12 13 20 14 19 15 18 16 17 SOJ Top View Symbol A17 A16 A15 A14 A13 OE I/O3 GND VCC I/O2 A12 A11 A10 A9 A8 NC VTERM Rating (2) Value Terminal Voltage with Respect to GND -0.5 to +7.0 Operating Temperature TA Unit (2) V 0 to +70 o C TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -55 to +125 o PT Power Dissipation 1.25 W IOUT DC Output Current 50 mA C C 3483 tbl 02 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5V. 3483 drw 02 Capacitance (TA = +25°C, f = 1.0MHz, SOJ package) Truth Table(1,2) CS OE WE I/O L L H DATAOUT Read Data L X L DATAIN Write Data L H H High-Z Output Disabled H X X High-Z Deselected - Standby (I SB) VHC(3) X X High-Z Deselected - Standby (I SB1) NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs ≥VHC or ≤VLC. Parameter(1) Symbol Function CIN Input Capacitance CI/O I/O Capacitance Conditions Max. Unit VIN = 3dV 8 pF VOUT = 3dV 8 pF 3483 tbl 03 NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested. Recommended Operating Temperature and Supply Voltage 3483 tbl 01 Grade Temperature GND VCC Commercial 0°C to +70°C 0V 5.0V ± 10% Industrial –40°C to +85°C 0V 5.0V ± 10% 3483 tbl 04 Recommended DC Operating Conditions Symbol Parameter VCC Supply Voltage GND Ground VIH VIL Input High Voltage Input Low Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 ____ VCC +0.5 V ____ 0.8 (1) -0.5 NOTE: 1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle. 6.42 2 V 3483 tbl 05 IDT 71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges DC Electrical Characteristics (VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges) Symbol Parameter Test Conditions Min. Max. Unit 5 µA |ILI| Input Leakage Current VCC = Max., VIN = GND to VCC ___ |I LO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to VCC ___ 5 µA VOL Output Low Voltage IOL = 8mA, VCC = Min. ___ 0.4 V 2.4 ___ V Output High Voltage VOH IOH = -4mA, VCC = Min. 3483 tbl 06 DC Electrical Characteristics(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V) 71128S12 Symbol Parameter 71128S15 71128S20 Com'l. Ind. Com'l. Ind. Com'l. Ind. Unit ICC Dynamic Operating Current CS < VIL, Outputs Open, VCC = Max., f = fMAX(2) 155 155 150 150 145 145 mA ISB Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open, VCC = Max., f = fMAX(2) 40 40 40 40 40 40 mA ISB1 Full Standby Power Supply Current (CMOS Level) CS > VHC, Outputs Open, VCC = Max., f = 0(2) VIN < VLC or VIN > VHC 10 10 10 10 10 10 mA 3483 tbl 07 NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. AC Test Conditions GND to 3.0V Input Pulse Levels Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V See Figure 1 and 2 AC Test Load 3483 tbl 08 AC Test Loads 5V 5V 480Ω 480Ω DATA OUT DATA OUT 30pF 5pF* 255Ω 255Ω 3483 drw 04 3483 drw 03 *Including jig and scope capacitance. Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 6.42 3 IDT71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges) 71128S12 Symbol Parameter 71128S15 71128S20 Min. Max. Min. Max. Min. Max. Unit Read Cycle Time 12 ____ 15 ____ 20 ____ ns Address Access Time ____ 12 ____ 15 ____ 20 ns Chip Select Access Time ____ 12 ____ 15 ____ 20 ns 3 ____ 3 ____ 3 ____ ns 0 READ CYCLE tRC tAA tACS tCLZ (1) Chip Select to Output in Low-Z tCHZ(1) Chip Deselect to Output in High-Z tOE 0 7 0 8 ns 6 ____ 7 ____ 8 ns Output Enable to Output in Low-Z 0 ____ 0 ____ 0 ____ ns Output Disable to Output in High-Z 0 5 0 5 0 7 ns 4 ____ 4 ____ 4 ____ ns 0 ____ 0 ____ 0 ____ ns Chip Deselect to Power-Down Time ____ 12 ____ 15 ____ 20 ns Write Cycle Time 12 ____ 15 ____ 20 ____ ns 10 ____ 12 ____ 15 ____ ns 10 ____ 12 ____ 15 ____ ns 0 ____ 0 ____ 0 ____ ns 10 ____ 12 ____ 15 ____ ns 0 ____ 0 ____ 0 ____ ns 7 ____ 8 ____ 9 ____ ns 0 ____ 0 ____ 0 ____ ns 3 ____ 4 ____ ns 0 5 0 8 ns Output Enable to Output Valid tOLZ (1) tOHZ (1) tOH tPU 6 ____ Output Hold from Address Change (1) tPD(1) Chip Select to Power-Up Time WRITE CYCLE tWC Address Valid to End of Write tAW Chip Select to End of Write tCW Address Set-up Time tAS Write Pulse Width tWP Write Recovery Time tWR Data Valid to End-of-Write tDW Data Hold Time tDH (1) tOW Output active from End-of-Write 3 ____ tWHZ(1) Write Enable to Output in High-Z 0 5 NOTE: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 6.42 4 3483 tbl 09 IDT 71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tAA OE tOE CS tOLZ tCLZ DATAOUT VCC SUPPLY ICC CURRENT ISB (5) (5) tACS (3) tCHZ HIGH IMPEDANCE (5) tOHZ (5) DATAOUT VALID tPD tPU 3483 drw 05 Timing Waveform of Read Cycle No. 2 (1, 2, 4) tRC ADDRESS tAA tOH DATAOUT tOH DATAOUT VALID PREVIOUS DATAOUT VALID 3483 drw 06 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 6.42 5 IDT71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1, 2, 4) tWC ADDRESS tAW CS tWP (2) tAS tWR WE tWHZ DATAOUT (5) tOW tCHZ (5) HIGH IMPEDANCE (3) tDW DATAIN (5) (3) tDH DATAIN VALID 3483 drw 07 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4) tWC ADDRESS tAW CS tAS tWR tCW WE tDW DATAIN tDH DATAIN VALID 3483 drw 08 NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period. 5. Transition is measured ±200mV from steady state. 6.42 6 IDT 71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges Ordering Information IDT 71128 S XX Device Type Power Speed X Package X Process/ Temperature Range Blank I Commercial (0°C to +70°C) Industrial (–40°C to +85°C) Y 400-mil SOJ (SO32-3) 12 15 20 Speed in nanoseconds 3483 drw 09 6.42 7 IDT71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges Datasheet Document History 8/5/99 8/13/99 9/30/99 2/18/00 3/14/00 8/09/00 02/01/01 Pg. 3 Pg. 4 Pg. 6 Pg. 8 Pg. 1, 3, 4, 7 Pg. 3 Pg. 3 Updated to new format Removed military entries from DC table Removed Note 1, renumbered notes and footnotes Removed Note 1, renumbered notes and footnotes Added Datasheet Document History Added 12ns, 15ns, and 20ns industrial temperature speed grade offerings Revise ISB for Industrial Temperature offerings to meet commerical specifications Revised ISB to accomidate speed functionality Not recommended for new designs Removed "Not recommended for new designs" CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 8 for Tech Support: [email protected] 800-544-7726, x4033