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TDC-GPX
TDC-GPX
Ultra-high Performance 8 Channel
Time-to-Digital Converter
Datasheet
J AN 18 , 2007
TH
acam - solutions in time
Precision Time Interval Measurement
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TDC-GPX
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TDC-GPX
LVPECL inputs
1. Introduction
DStart
DStop1
LVTTL inputs
TStart
DStop2
TStop1
1.1 System overview
TStop2
TStop3
TStop4
TStop5
TStop6
TStop7
TStop8
StartDis
StopDis
Input Logic
Measurement Core
40 MHz
ref
PLL
Hit FIFOs
0
TQFP100
1
2
3
4
5
Phase
6
7
8
TFBGA120
I-Mode
8 channels with typ. 81 ps resolution
9 LVTTL inputs, optional 3 LVPECL
IntFlag
inputs
5.5 ns pulse-pair resolution with
ErrFlag
32-fold multi-hit capability = 182 MHz
peak rate
Trigger to rising or falling edge
Measurement range 9,8 µs, endless
measurement range by internal
retrigger of START
10 MHz continuous rate per channel
40 MHz continuous rate per chip
AluTrigger/
Reset
Start
Logic
MTimer
Post-processing
Master
reset
Partial
reset
Power-on
reset
Int and Error
flags
Interface FIFO1
Configuration
registers
Read/Write logic
WRN
RDN
CSN
ADR
Interface FIFO2
Data multiplexer
OEN/
Reset
Data bus 28 or 2 x 16
EF1
EF2
LF1
LF2
G-Mode
2 channels with 40 ps resolution
Differential LVPECL inputs, optional LVTTL
Measurement range 0 ns to 65 µs
5.5 ns pulse-pair resolution between edges of
equal slope with 32-fold multi-hit = 182 MHz peak
rate
Minimum pulse width 1.5 ns
Trigger to rising and falling edge
Optional Quiet Mode (no ALU operation and Dataoutput during measurements)
20 MHz continuous rate per channel
40 MHz continuous rate per chip
M-Mode
2 channels with 10 ps resolution
(70 ps peak-peak)
Differential LVPECL inputs
Measurement range 0 ns up to 10 µs
Single hit per Start and channel
Trigger to rising or falling edge
Quiet Mode (no ALU operation and Data-output
during measurements)
Max. 500 kHz continuous rate per channel
Max. 1 MHz continuous rate per chip
General
R-Mode
Start retrigger option (besides M-Mode)
Packages: TQFP100, TFBGA120
IO voltage 3.0 V – 3.6 V
Core voltage 2.3 V – 3.6 V regulated by resolution
adjust unit
Data bus: 28 Bit or 2 x 16 Bit asynchronous with
Chipselect, Readstrobe, Writestrobe
40 MHz continuous rate per chip
Address range: 4 Bit
2 channels with 27 ps resolution
Differential LVPECL inputs, optional LVTTL
Measurement range 0 µs up to 40 µs
5.5 ns pulse-pair resolution with 32-fold multi-hit
capability = 182 MHz peak rate
Trigger to rising or falling edge
Optional Quiet Mode (no ALU operation and Dataoutput during measurements)
40 MHz continuous rate per channel
40 MHz continuous rate per chip
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1.2 Index
1. Introduction
3
1.1 System overview ......................................................................................................................................3
1.2 Index.......................................................................................................................................................4
1.3 Electrical Characteristics..........................................................................................................................6
1.3.1 Bus Timings ..................................................................................................................................7
1.3.2 16 Bit Mode .........................................................................................................................................8
1.3.3 Disable Timings .....................................................................................................................................9
1.3.4 Reset Timings .......................................................................................................................................9
1.3.5 General Timings & Resolution ................................................................................................................10
1.4 Pin Description ......................................................................................................................................11
1.5 Package Drawings ..................................................................................................................................14
1.6 Power supply .........................................................................................................................................15
1.6.1 Resolution adjust ........................................................................................................................15
1.6.2 Supply voltages...........................................................................................................................16
1.6.3 Design Rules...............................................................................................................................16
1.7 Register settings...................................................................................................................................17
1.7.1 Write Registers ..........................................................................................................................17
1.7.2 Read registers............................................................................................................................19
1.7.3 Read/Write registers...................................................................................................................20
2 I-Mode
22
2.1 Block diagram I-Mode..............................................................................................................................22
2.2 Input circuitry I-Mode .............................................................................................................................23
2.3 I-Mode Basics ........................................................................................................................................24
2.4 Data structure ......................................................................................................................................26
2.5 Reset ...................................................................................................................................................26
2.6 MTimer .................................................................................................................................................26
2.7 Interrupt Flag .......................................................................................................................................26
2.8 Error Flag..............................................................................................................................................26
2.9 Differential Inputs...................................................................................................................................27
2.10 I-Mode Timing & Resolution....................................................................................................................27
2.11 Measurement Flow ...............................................................................................................................28
2.11.1 Single measurement ..................................................................................................................28
2.11.2 Continous Measurement ............................................................................................................29
3 G-Mode
30
3.1 Block diagram G-Mode ............................................................................................................................30
3.3 G-Mode Basics.......................................................................................................................................32
3.4 Data structure and readout ....................................................................................................................33
3.5 Reset ...................................................................................................................................................34
3.6 MTimer .................................................................................................................................................34
3.7 Interrupt Flag .......................................................................................................................................34
3.8 Error Flag..............................................................................................................................................34
3.9 Testinputs.............................................................................................................................................34
3.10 RaSpeed & Delx....................................................................................................................................34
3.11 G-Mode Timing & Resolution ..................................................................................................................35
3.12 Measurement Flow ...............................................................................................................................36
4 R-Mode
37
4.1 Block diagram R-Mode ............................................................................................................................37
4.2 Input Circuitry R-Mode............................................................................................................................38
4.3 R-Mode Basics.......................................................................................................................................39
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4.4 Data structure and readout ....................................................................................................................41
4.5 Reset ...................................................................................................................................................41
4.6 MTimer .................................................................................................................................................41
4.7 Interrupt Flag .......................................................................................................................................41
4.8 Error Flag..............................................................................................................................................41
4.9 Testinputs.............................................................................................................................................41
4.10 RaSpeed & Delx....................................................................................................................................41
4.11 R-Mode Timing & Resolution ..................................................................................................................42
4.12 Measurement Flow ...............................................................................................................................43
5 M-Mode
45
5.1 Block diagram M-Mode............................................................................................................................45
5.2 Input Circuitry M-Mode ...........................................................................................................................46
5.3 M-Mode Basics ......................................................................................................................................47
5.4 Data structure and readout ....................................................................................................................48
5.5 Reset ...................................................................................................................................................48
5.6 MTimer .................................................................................................................................................49
5.7 Interrupt Flag .......................................................................................................................................49
5.8 Error Flag..............................................................................................................................................49
5.9 Testinputs.............................................................................................................................................49
5.10 M-Mode Timing & Resolution..................................................................................................................49
5.11 Measurement Flow ...............................................................................................................................50
6 Bug Report
51
6.1 Data Bus: 16 Bit Mode ...........................................................................................................................51
Contact
52
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1.3 Electrical Characteristics
Absolute Maximum Ratings (Vss = 0V, Tj = 25°C)
Parameter
Symbol
Supply voltage
I/O
Vddo
Core
Vddc
Hardmacro
Vddc-h
Oscillator
Vddc-o
Diff. inputs
Vdde
Input voltage
5V Tolerant
Vi
Buffers
Output current
1 mA Buffer
Io
4 mA Buffer
Storage
Tstg
temperature
Junction
Tj
temperature
Thermal
junction-ambient
R thj-a
resistance
Terminal Capacitance
Terminal
Input
Output
Bidirectional
Condition
Vdcc < Vddo + 0.6V
Vdcc < Vddo + 0.6V
Vdcc < Vddo + 0.6V
Vddo = +0.3~3.6V
-
TQFP100
TFBGA120
Symbol
Condition
Ci
Co
Cio
measured @Vdd = Vi = Vo = Vss, f =
1 MHz, Ta = 25°C
DC Characteristics (Vddo = 3.3 V ± 0.3 V, Vss = 0 V, Tj = -40 to +85°C)
Parameter
Symbol
Condition
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Supply current
Vih
Vil
Voh
Vol
TTL 5V tolerant input
TTL 5V tolerant input
Vddo
Vddc
Vddc-h
Vddc-o
Vdde
I/O
Core
Hardmacro
Oscillator
Diff. inputs
LVPECL inputs:
DC Parameters (VDD = 3.3 V±5 %, Tj = 0°C to 125°C)
Parameter
Val
VinOS
Vdde-1.53V < VinOS < Vdde-0.89V
VinDF
0.2V < VinDF < 2.1V
Rated Value
-0.3 to +3.6
-0.3 to +3.6
-0.3 to +3.6
-0.3 to +3.6
-0.3 to +3.6
-0.3 to 6.0
Unit
V
-5 to +5
-9 to +9
-65 to 150
mA
-40 to 125
°C
96
105
K/W
Rated Value
Min
Typ
Max
6
9
10
-
Unit
Rated Value
Min
Typ
Max
2.0
5.5
0.0
0.8
2.4
0.4
Typ
1.4 + Bus
20
7
4
19
Unit
V
°C
pF
V
mA
Condition
-
VinOS = Input offset voltage, (Via+Vian)/2
VinDF = Input differential voltage,
Via = Input voltage of A
Vian = Input voltage of AN
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1.3.1 Bus Timings
(Vddo = Vddc = 3.3 V, Ta = +25°C)
Write operations
ADR
valid
tS-AD
WRN
tS-CSN
CSN
tPW-WL
tPW-WH
tH-CSN
tH-DW
tS-DW
DATA
valid
tH-AD
valid
valid
Figure 1
Spec
tS-AD
t H- A D
t PW-WL
t PW-WH
t S - DW
t H- DW
t S - CS N
t H- CS N
Description
Address Setup Time
Address Hold Time
Write LOW Time
Write HIGH Time
Write Data Setup Time
Write Data Hold Time
Chip Select Setup Time
Chip Select Hold Time
Min (ns)
2
0
6
6
5
4
0
0
Max (ns)
-
Read Operations
ADR
It is not
allowed to
read from
an empty
FIFO !
valid
tS-AD
RDN
valid
tH-AD
tS-CSN
tPW-RL
tPW-RH
tH-CSN
tS-EF
CSN
DATA
tV-DR
High-Z
tH-DR
valid
valid
High-Z
Last data
EF
Figure 2
Spec
tS-AD
t H- A D
t P W - RL
t P W - RH
t V- DR
t H- DR
t S - CS N
t H- CS N
t S - EF
Description
Address Setup Time
Address Hold Time
Read LOW Time
Read HIGH Time
Read Data Valid Time
Read Data Hold Time
Chip Select Setup Time
Chip Select Hold Time
Empty Flag Set Time
Min (ns)
2
0
6
6
5
4
0
0
-
Max (ns)
11.8*
8.5**
11.8*
* @ 87ps res. & 40pF load.
This value depends on the
capacitive load and has to be
confirmed by evaluation. This
value also depends on the
adjusted resolution (e.g)
** Can be prolonged infinitely
with OEN = 0 (driving the bus
permanently) and stable address.
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OEN operations – Driving the bus permanently
DATA
valid
High-Z
High-Z
OEN
min.
max.
tOE-F
tOE-R
min.
max.
Figure 3
Spec
tOE-F
tOE-R
Description
OEN Rise to Data Valid
OEN Fall to Data Valid
Min (ns)
1.5
1
Max (ns)
9
8.5
Note: With OEN = Low the output buffers are driving allthe time, with OEN = High they are driving only during a
read strobe. While writing to the TDC-GPX OEN has to be High.
Fake Reads for speeding up data readout
The maximum data readout rate is limited by the empty flag set time as it is not allowed to read from an empty
FIFO. This can be overcome by a second fake read strobe which is delayed to the read strobe at the TDC-GPX.
ADR
RDN
Data
EF
RD*
Data takeover
Figure 4
1.3.2 16 Bit Mode
The TDC-GPX data bus can be switched from 28 Bit to 16 Bit. This is done writing a 0x0000010 to address 14.
After that all read / write commands have to be done in pairs. When reading the last data from an interface FIFO
the empty flag disappears already with the first read command. Nonetheless it is mandatory to read a second
time.
The first read/write command always refers to the LSW, the second one to the MSW. The highest 4 Bit of the
MSW are not relevant (write) or shall be ignored (read).
ADR
8
9
RDN
Data
LSW1
MSW1
LSW2
MSW2
EF1
EF2
Figure 5
Note: See Bug-Report 01 at the end of the datasheet
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1.3.3 Disable Timings
Disable inputs (Vddo = Vddc = 3.3 V, Ta = +25°C)
Spec
Description
t S 1 - DH
t S 2 - DH
t S 1 - DL
t S 2 - DL
Disable Setup Time
Disable Setup Time
Disable Hold Time
Disable Hold Time
Min
(ns)
-
STOP
Max
(ns)
6
1
0
2
tS2-DH
STOP
tS1-DL
tS2-DL
tS1-DH
StopDis
pass
not allowed
no pass
no pass
undefined
Figure 6
StopDisStart (Bit 21, register 5) @ 87 ps resolution
Spec
Description
Dead Time Rising(Start) to Rising(Stop)
t S 1 - DH
Dead Time Falling(Start) to Rising(Stop)
t S 2 - DH
Dead
Time Rising(Start) to Falling(Stop)
t S 1 - DL
Dead Time Falling (Start) to Falling (Stop)
t S 2 - DL
Min (ns)
-
Max (ns)
6.3
6.1
5.2
7.4
1.3.4 Reset Timings
Power-up Reset: ( V d d o = V d d c = 3 . 3 V , T a = + 2 5 ° C )
Spec
t ph
Description
Reset pulse width
Min (ns)
200
Max (ns)
-
Master Reset: ( V d d o = V d d c = 3 . 3 V , T a = + 2 5 ° C )
Spec
t ph
t r fs
trrs
Description
Reset pulse width
Time after rising edge of reset pulse
before hits are accepted
Time after falling edge of reset pulse
before hits are accepted
Min (ns)
10
27
13
tph
Master Reset
(at pin)
Start/Stop
trfs
trrs
not acc.
accept
accept
Figure 7
Partial Reset: ( V d d o = V d d c = 3 . 3 V , T a = + 2 5 ° C )
Spec
t ph
t r fs
trrs
trs
Description
Reset pulse width
Time after rising edge of reset pulse
before hits are accepted
Time after falling edge of reset pulse
before hits are accepted
Time berfore rising edge of reset pulse
where hits will be lost
Min (ns)
10
60
13
tph
Partial Reset
(at pin)
trfs
trrs
not acc.
trs
-
Start/Stop
accept
accept
Figure 8
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pass
TDC-GPX
1.3.5 General Timings & Resolution
Without resolution adjust, the intrinsic resolution varies slightly from chip to chip. The distribution over the
production lots is of gaussian type.
# of chips
The TDC-GPX time measurement is based on internal
propagation delays. Those delays depend on temperature and voltage. They also vary over the production
lots. The resolution adjust mode (see) uses the voltage
dependency to compensate for temperature and production variations and sets the circuits to a fixed and
programmable resolution.
Figure 9 shows the dependency of all timings from the
core voltage, referred to the 3.3V timings. The resolution at 3.3V can be varied by factors 0.93 at 3.6V to
1.4 at 2.3V.
-3σ
-2σ
Best
(0.74)
Delay Variation Dependency on Power Supply Voltage
1,50
1,40
1,40
60ps
1,33
1,27
1,30
0
Typical
(1.0)
1σ
2σ
81ps
(@Vddc = 3.3V, Tamb = 25°C)
3σ
Worst
(1.31)
104ps
Figure 11
1,22
1,17
1,20
-1σ
δt
1,13
1,10
1,10
1,07
1,05
1,02
1,00
1,00
0,98
0,95
Within a single production lot the distribution is narrower. Figure 12 shows a typical distribution of the
intrinsic resolution at 3.3 V core voltage and 25°C
ambient temperature within a single production lot.
0,93
0,90
0,80
2,3
2,5
2,7
2,9
3,1
3,3
3,5
# of chips
Vddc
Figure 9
Figure 10 shows the dependency of all timings on the
temperature, referred to 25°C junction temperature. If
the temperature increases from 25°C to 70°C, the
intrinsic resolution goes down by a factor 1.077. In
resolution adjust mode this is compensated by increasing the core voltage from 3.3V to 3.6V.
81ps
70ps
92ps
(@Vddc = 3.3V, Tamb = 25°C)
Figure 12
Delay Variation Dependency on Temperature
Example:
1,200
1,170
Taking the distribution from Figure 12 and assuming
an operating temperature range of 0°C to 40°C as
well as 1 Mhz data rate. The junction temperature will
be about 57°C max. The slowest chips will have 92ps
* 1.043 = 97ps resolution at 3.3V Vddc. Increasing
the core voltage to 3.6V will speed them up to 90.2ps.
Setting the resolution adjust mode to a resolution of
95ps will guarantee that the PLLs of all chips will lock
at one and the same resolution over the whole operating temperature range.
1,128
1,102
1,100
1,077
1,043
1,000
dt
1,000
0,957
0,889
0,923
0,900
0,800
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140
Tj(°C)
Figure 10
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100 Vsso
99 TStop1
98 Vdde
97 DStop1
96 DStop1N
95 Vsse
94 Vdde
93 DStart
92 DStartN
91 Vdde
90 Vssc-h
89 Vssc-o
88 Vddc-o
87 Vddc-h
86 Vdde
85 Vsse
84 DStop2
83 DStop2N
82 Vdde
81 Vdde
80 TStart
79 Vddc
78 Vssc
77 Vddo
76 Tstop5
1.4 Pin Description
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Alutrigger
Adr0
Adr1
Adr2
Adr3
TStop6
Vddc
Vssc
PuResn
TStop7
Vsso
Test
OEN
Vssc
TStop8
ErrFlag
IrFlag
LF2
LF1
RefClk
Vsso
Vddo
EF2
EF1
D27
D7
D8
D9
D10
D11
Vsso
D12
D13
D14
D15
D16
D17
Vssc
Vddc
Vddo
D18
D19
D20
D21
D22
D23
Vsso
D24
D25
D26
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
48
50
Vddc 1
Vddo 2
TStop2 3
StartDis 4
StopDis1 5
StopDis2 6
TStop3 7
StopDis3 8
StopDis4 9
Vddc 10
TStop4 11
Vssc 12
WRN 13
CSN 14
RDN 15
Phase 16
Vddo 17
Vsso 18
D0 19
D1 20
D2 21
D3 22
D4 23
D5 24
D6 25
Figure 13
PIN No
PIN Name
TQFP TFBGA
100
120
001
002
003
004
005
A1
B1
C1
C2
D1
Vddc
Vddo
Tstop2
StartDis
StopDis1
006
C3
StopDis2
007
008
009
010
011
012
013
014
015
016
D2
E1
D3
F1
E3
F2
G1
F3
G2
H1
TStop3
StopDis3
StopDis4
Vddc
TStop4
Vssc
WRN
CSN
RDN
Phase
Description
Core supply voltage
I/O supply voltage
TTL input ‘Stop2’
Disable input ‘DStart’ or ‘TStart’
Disable input ‘DStop1’ or inputs ‘TStop1 ‘ and
‘TStop2’
Disable input ‘DStop2’ or inputs ‘TStop3 ‘ and
‘TStop4’
TTL input Stop3
Disable inputs ‘TStop5 ‘ and ‘TStop6’
Disable or inputs ‘TStop7 ‘ and ‘TStop8’
Core supply voltage
TTL input ‘Stop4’
Core GND
Write (LOW active)
Chip select (LOW active)
Read (LOW active)
Phase output PLL
Type
Terminal
() = if not used
TTL input
TTL input
TTL input
Vddc
Vddo
(10kΩ to GND)
(GND)
(GND)
TTL input
(GND)
TTL input
TTL input
TTL input
(10kΩ to GND)
(GND)
(GND)
Vddc
(10kΩ to GND)
GND
TTL input
TTL input
TTL input
TTL input
(GND)
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∗
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
G3
H2
J1
J2
K1
K2
L1
L2
M1
N2
M2
N3
M3
N4
M4
N5
L3
M5
N6
M6
N7
L5
M7
L6
M8
N9
L7
M9
L8
M10
L9
M11
N12
L10
M13
N13
L13
L12
L11
K13
K12
Vddo
Vsso
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
Vsso
D12
D13
D14
D15
D16
D17
Vssc
Vddc
Vddo
D18
D19
D20
D21
D22
D23
Vsso
D24
D25
D26
D27
EF1
EF2
Vddo
Vsso
RefClk
LF1
I/O supply voltage
I/O GND
Data 0
‘
‘
‘
‘
‘
‘
‘
‘
‘
‘
Data 11
I/O GND
Data 12
‘
‘
‘
‘
Data 17
Core GND
Core supply voltage
I/O supply voltage
Data 18
‘
‘
‘
‘
Data 23
I/O GND
Data 24
‘
‘
Data 27
Interface FIFO 1 empty flag, active HIGH
Interface FIFO 2 empty flag, active HIGH
I/O supply voltage
I/O GND
Input reference clock
058
K11
LF2
059
060
061
062
063
J13
J12
H13
H12
H11
IrFlag
ErrFlag
Tstop8
Vssc
OEN
Interrupt flag, active HIGH
Error flag, active HIGH
TTL input ‚Stop8’
Core GND
Output enable, active LOW
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
4mA
4mA
4mA
4mA
4mA
4mA
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
4mA
4mA
4mA
4mA
4mA
4mA
Bidirectional 4mA
Bidirectional 4mA
Bidirectional 4mA
Bidirectional 4mA
Output 4mA
Output 4mA
Vddo
GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
GND
Vddc
Vddo
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ to GND
10kΩ
10kΩ
10kΩ
10kΩ
to
to
to
to
Vddo
GND
Interface FIFO 1 load flag, active HIGH
∗
TTL input
Output 1mA
Interface FIFO 2 load flag, active HIGH
∗
Output 1mA
Output 1mA
Output 1mA
TTL input
TTL input
(10kΩ to GND)
GND
(10kΩ to Vddo)
Valid only whileF13 it is not read
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GND
GND
GND
GND
TDC-GPX
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
091
092
093
094
095
096
097
098
099
100
G11
F13
F12
F11
E13
E12
D12
D13
E11
C13
C12
D11
C11
A11
C10
B10
C9
B9
A9
B8
A8
C7
B7
A7
C6
B6
A6
C5
B5
A5
C4
B4
A4
B3
A3
B2
A2
Test
Vsso
Tstop7
PuResN
Vssc
Vddc
Tstop6
Adr3
Adr2
Adr1
Adr0
AluTrigger
Tstop5
Vddo
Vssc
Vddc
Tstart
Vdde
Vdde
DStop2N
DStop2
Vsse
Vdde
Vddc-h
Vddc-o
Vssc-o
Vssc-h
Vdde
DStartN
DStart
Vdde
Vsse
Dstop1N
Dstop1
Vdde
TStop1
Vsso
acam test input, connect it to GND !
I/O GND
TTL input ‚Stop7’
Power-up reset, low active
Core GND
Core supply voltage
TTL input ‘Stop6’
Address 3
Address 2
Address 1
Address 0
External ALU trigger
TTL input ‘Stop5’
I/O supply voltage
Core GND
Core supply voltage
TTL input ‘Start’
LVPECL supply voltage
LVPECL supply voltage
Differential input ‘Stop2’ , neg
Differential input ‘Stop2’ , pos
LVPECL GND
LVPECL supply voltage
Hardmacro supply voltage
Hardmacro supply voltage
Hardmacro GND
Hardmacro GND
LVPECL supply voltage
Differential input ‘Start’ , neg
Differential input ‘Start’ , pos
LVPECL supply voltage
LVPECL GND
Differential input ‘Stop1’ , neg
Differential input ‘Stop1’ , pos
LVPECL supply voltage
TTL input ‘Stop1’
I/O GND
TTL input
TTL input
TTL input
TTL
TTL
TTL
TTL
TTL
TTL
TTL
input
input
input
input
input
input
input
TTL input
Differential input
Differential input
Differential input
Differential input
Differential input
Differential input
TTL input
GND
GND
(10kΩ to GND)
GND
Vddc
(10kΩ to GND)
(10kΩ to GND)
(10kΩ to GND)
Vddo
GND
Vddc
(10kΩ to GND)
Vdde
Vdde
(10kΩ to GND)
(10kΩ to GND)
GND
Vdde
Vddc-h
Vddc-o
GND
GND
Vdde
(10kΩ to GND)
(10kΩ to GND)
Vdde
GND
(10kΩ to GND)
(10kΩ to GND)
Vdde
(10kΩ to GND)
GND
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TDC-GPX
1.5 Package Drawings
TQFP100:
Figure 14
Sockets: E.g. Yamaichi
IC149-100-025
TFBGA:
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TDC-GPX
1.6 Power supply
Tref = 25ns (40 MHz reference clock)
RefClkDiv, HSDiv → Register 7
1.6.1 Resolution adjust
In principle the high resolution of the TDC-GPX is derived from the internal gate propagation times. The
gate propagation time depends upon voltage, temperature and the manufacturing process. Due to this dependency the resolution normally is not known and
must be calculated via calibration measurements. In
addition, the resolution is not stable, it sways with
voltage and temperature. This does not apply using the
resolution adjust mode for the TDC-GPX. In this mode
the resolution of the TDC-GPX is adjusted quartzaccurately and absolutely temperature stable via
Phase Locked Loop The phase locked loop (PLL) regulates the core voltage of the TDC-GPX so that the resolution is set exactly to the programmed value.
The adjustment range of the resolution can reach
values from –40 % up to +9 % of the normal resolution at 3.3 V and 25 °C. If environmental conditions
lead to very large adjustments the locked-state can be
lost. Then the PLL changes to floating resolution until
the conditions allow the PLL to lock again.
Figure 15 shows the recommended external circuit for
the regulation loop.
Note: See also application note AN013.
Example:
RefClkDiv = 7 and HSDiv
ing resolution:
I-Mode
80.9553
G-Mode
40.4776
R-Mode
26.9851
The BIN size is calculated as follows:
T × 2refclkdiv
BINI −Mode = ref
216 × hsdiv
1
BING −Mode = BINI −Mode ×
2
1
BINR −Mode = BINI − Mode ×
3
1
BINM − Mode = BINR − Mode ×
MSet + 1
= 183 give the followps BIN
ps BIN
ps BIN
40 MHz reference
3.3 V
Schottky (BAT47)
5*47 µF
electrolytic, e.g.
tantalum
close to the regulator
5*47 µF
5*47 µF
Vddo
Vddo
Vddo
Vddo
Vddo
Vdde
Vdde
Vdde
Vdde
Vdde
Vdde
Vddc Vddc
Vsso
Vddc Vddc Vddc
100 µF
>= 50 mil
RefClk
Vddc-h
Vddc-o
5.0 V
10 µF
2*47 µF
1K3
TDC-GPX
Vo
Vi
LM1117
adj.
Phase
2K2
Vssc
Vssc-h
Vssc-o
Vsse
10 µF
10R
1K8
Figure 15
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TDC-GPX
Power consumption
The current consumption is about 45 mA in R- and Gmode and 39mA in I-mode idle plus 5 mA per million
events. At 1 million continuous events per second the
junction temperature will increase to 17 °C above
ambient.
The thermal resistance Rth j-a is 96K/W (still air) for
the TQFP package and 105K/W for the TFBGA package. With available heatsinks it can be reduced to
35k/W (still air), due to a very small Rthj-c of the
package.
The maximum junction temperature is
Tj max = 125 °C.
1.6.2 Supply voltages
Although the TDC-GPX is a fully digital circuit, some
analog measures affect the circuit. The reason is that
the TDC is based on the internal analog measure
'propagation delay time' which is influenced by temperature and supply voltage. A good layout of the supply voltage is essential for good measurement results.
It should be high capacitive and of low inductance.
There are several connections for power supply provided at the TDC-GPX:
Vddo
Vddc
Vddc-h
Vddc-o
Vdde
Vsso
Vssc
Vssc-h
Vssc-o
-
I/O supply voltage
Core supply voltage
Supply for the Hamac
Supply for the ring oscillator
Supply of LVPECL inputs
I/O GND
Core GND
Hamac GND
Ring oscillator GND
1.6.3 Design Rules
As shown in Figure 15 the supply voltage of the measuring unit, Vddc-o/h, is provided by an adjustable linear regulator. It is strongly recommended to use only
LM317 or LM1117 regulators, because only for these
regulators the circuit is tested and approved. Do not
use low drop regulators because these regulators’
reference refers to the output voltage and the regulation might be in conflict with the PLL regulation. The
input voltage of the regulator should be ≥ 5 V so that
the maximum output voltage of the PLL regulation
circuit is not limited by the voltage regulator’s voltage
drop of 1.2 V to 1.3 V.
For a good stabilization we recommend the use of
5 * 47 µF, one for each Vddc pin.
1 * 47 µF for Vddc-h.
1 * 47 µF for Vddc-o.
5 * 47 µF, total for Vddo and Vdde.
Recommended capacitors:
Taiyo-Yuden LMK325BJ476MM, 47µF, 1210
Also for the other supply voltages, Vddc, Vddo & Vdde,
linear regulators are recommended. Switched mode
regulators will introduce a lot of noise to the measurement.
The supply voltage for the core should not be higher
than the supply voltage of the I/O plus 0.6 V. Otherwise the signal flow could be disturbed.
All ground pins should be connected to a ground plane
on the printed circuit board.
Vddc, Vddc-h and Vddc-o are floating and are supplied
from the resolution adjust voltage regulator.
Vddo should be provided by a fixed voltage regulator to
avoid disturbances caused by the inputs supply.
The width of the strip line between the regulator’s
output and the TDC-GPX power supply pins should be
at least 50 mil.
For more detailed information concerning the PLL
regulation circuit please refer to application note no.
13 at the end of this document.
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TDC-GPX
1.7 Register settings
In depends on the operating mode whether bits are relevant or not. Especially the read data structure depends on
the operating mode.
1.7.1 Write Registers
Service bits are for acam testing and security purposes only, Please use the recommended values.
These registers can also be read back.
Register 0: Adr = 0
0
ROsc
1
RiseEn0
2
FallEn0
3
RiseEn1
4
FallEn1
5
RiseEn2
6
FallEn2
7–9
HQSel
10 – 18 TRiseEn
19 – 27
TFallEn
Register 1: Adr = 1
0–3
Adj0
4–7
Adj1
8 – 11
Adj2
12 – 15 Adj3
16 – 19 Adj4
20 – 23 Adj5
24 – 27 Adj6
I
x
‘1’ = start ring oscillator
‘1’ enable rising edge sensitivity on DStart input
‘1’ enable falling edge sensitivity on DStart input
‘1’ enable rising edge sensitivity on DStop1 input
‘1’ enable falling edge sensitivity on DStop1 input
‘1’ enable rising edge sensitivity on DStop2 input
‘1’ enable falling edge sensitivity on DStop2 input
Service bits, must be set to ‘001’
‘1’ enables rising edges for the TTL inputs
Bit 10 = TStart, Bit 11 = TStop1 … Bit 18 = TStop8
‘1’ enables falling edges for the TTL inputs
Bit 19 = TStart, Bit 20 = TStop1 … Bit 27 = TStop8
Channel
Channel
Channel
Channel
Channel
Channel
Channel
adjustment
adjustment
adjustment
adjustment
adjustment
adjustment
adjustment
bits
bits
bits
bits
bits
bits
bits
channel
channel
channel
channel
channel
channel
channel
0
1
2
3
4
5
6
(Start)
(R-Mode
(R-Mode
(R-Mode
(R-Mode
(R-Mode
(R-Mode
=
=
=
=
=
=
2,
6,
0,
2,
6,
0,
G-Mode
G-Mode
G-Mode
G-Mode
G-Mode
G-Mode
G
x
x
x
x
x
x
x
x
R
x
x
x
x
x
x
x
x
M
x
x
x
x
x
x
x
x
I
G
x
x
x
x
x
x
x
R
x
x
x
x
x
x
x
M
x
x
x
x
x
x
x
I
G
x
R
M
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
=
=
=
=
=
=
0)
5)
0)
5)
0)
5)
Adjustment bits recommendation:
R-Mode: Adj1 = Adj4 = Adj7 = 2, Adj 2 = Adj 8 = 6, Adj5 = 6
G-Mode: Adj2 = Adj4 = Adj6 = Adj8 = 5.
Register 2: Adr = 2
0
G-Mode
1
I-Mode
2
R-Mode
3 – 11
Disable
12
16
20
22
24
26
–
–
–
–
–
–
15
19
21
23
25
27
Adj7
Adj8
DelRise1
DelFall1
DelRise2
DelFall2
‘1’ = switch on G-Mode
‘1’ = switch on I-Mode
‘1’ = switch on R-Mode
‘1’ = disable channel
Bit 3 = channel 0 (Start) … Bit 11 = channel 8
Channel adjustment bits channel 7 (R-Mode = 2, G-Mode = 0)
Channel adjustment bits channel 8 (R-Mode = 6, G-Mode = 5)
Service bits, set ‘0’
Service bits, set ‘0’
Service bits, set ‘0’
Service bits, set ‘0’
x
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TDC-GPX
Register 3: Adr = 3
0–4
MSet
5–6
DelT1
7–8
DelT2
9 – 10
DelT3
11 – 12 DelT4
13 – 14 DelT5
15 – 16 DelT6
17 – 18 DelT7
19 – 20 DelT8
21 – 22 RaSpeed0
23 – 24 RaSpeed1
25 – 26 RaSpeed2
27
GTest
I
Register 4: Adr = 4
0–7
StartTimer
8
9
10
12
14
16
18
20
22
23
24
25
26
27
Quiet
–
–
–
–
–
–
11
13
15
17
19
21
G
R
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
G
R
M
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
I
x
G
x
R
x
x
x
x
x
x
x
x
x
M
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Setting resolution factors 1 to 31 in M-Mode
Service bits, set ‘0’
Service bits, set ‘0’
Service bits, set ‘0’
Service bits, set ‘0’
Service bits, set ‘0’
Service bits, set ‘0’
Service bits, set ‘0’
Service bits, set ‘0’
Service bits, set ‘0’
Service bits, set ‘0’
Service bits, set ‘0’
Switches TStart to DStart, TStop1 to DStop1 and TStop2 to
DStop2 (TTL to ECL, testing in G-Mode)
Mon
RaSpeed3
RaSpeed4
RaSpeed5
RaSpeed6
RaSpeed7
RaSpeed8
MasterReset
PartialReset
AluTrigSoft
EFlagHiZN
MTimerStart
MTimerStop
Register 5: Adr = 5
0 – 17
StartOff1
18 – 20
ServiceMAdj
21
StopDisStart
22
StartDisStart
23
MasterAluTrig
24
PartialAluTrig
25
26
27
MasterOenTrig
PartialOenTrig
StartRetrig
defines repetition rate of internal Start in (N + 1)*Tref
recommended: 5 µs ( (199 + 1) * 25ns )
‘1’ = Switch on Quiet Mode in G-, R- or M-Mode If Quiet is
set to ‘1’, the ALU doesn’t start automatically, but after a
rising edge at pin ALUTrigger or after writing ‘1’ into Bit
‘AluTrigSoft’ (mandatory in M-Mode)
Switch on M-Mode
Pulse-pair timing adjust, typically set ‘0’
Pulse-pair timing adjust, typically set ‘0’
Pulse-pair timing adjust, typically set ‘0’
Pulse-pair timing adjust, typically set ‘0’
Pulse-pair timing adjust, typically set ‘0’
Pulse-pair timing adjust, typically set ‘0’
‘1’ = general reset excluding configuration registers
‘1’ = general reset excluding configuration registers and
Interface FIFO content
Starts ALU in Quiet Mode
‘1’ = EF output pin is driving all the time
‘1’ = the internal MTimer is started with a Start pulse
‘1’ = the internal MTimer is started with a Stop pulse
programmable internal Start-offset
Service bits, set “0”
Stop disable before a Start pulse
Start disable after a Start pulse
Master reset by Alutrigger pin HIGH (only with no Quiet
Mode)
Partial reset by Alutrigger pin HIGH (only with no Quiet
Mode)
Master reset by OEN pin LOW (only with OEN not used)
Partial reset by OEN pin LOW (only with OEN not used)
Start retrigger
I
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M
x
x
x
TDC-GPX
Register 6: Adr = 6
0–7
Fill
Defines the level when the fill-level Flags LFx of the 2 interface FIFOs will be set.
8 – 25
StartOff2
programmable internal Start-offset (in G-Mode only)
26
InSelECL
select ECL inputs for I-Mode DStop1 -> TStop1, TStop3,
TStop5, TStop7 DSTop2 -> TStop2, TStop4, TStop6,
TStop8(single channels can be switched off using ‘Disable’
27
PowerOnECL
‘1’ = Switch-on power for ECL-inputs
When reading back register 6 the "Fill" bits 0 to 7 will be inverted.
Register 7: Adr = 7
0–7
HSDiv
8 – 10
RefClkDiv
11
ResAdj
12
NegPhase
13
Track
14
Service
15 – 27
MTimer
High speed divider PLL
Reference clock divider PLL
Switch-on resolution adjust mode
Invert phase output of PLL
cut regulation loop of PLL
Service Bits, set ‘0’
Setting internal timer in multiples of Tref, 0 – 8191
Register 14: Adr = 14
0–3
Service
Write “0”
4
16BitMode
‘1’ switches on the 16 Bit mode of the data bus
5 – 27
Service
Write “0”
After 16 Bit mode is set all further read/write commands have to be done in pairs of 16 Bit.
I
x
G
x
R
x
M
x
x
x
x
x
x
I
x
x
x
x
x
G
x
x
x
x
x
R
x
x
x
x
x
M
x
x
x
x
x
x
x
x
x
I
x
x
x
G
x
x
x
R
x
x
x
x
x
x
1.7.2 Read registers
I-Mode
Register 8: Adr = 8
0 – 16
IFIFO1
17
Slope1
18 – 25
Start#1
26 – 27
ChaCode1
Time interval data from Interface FIFO1, Hit = Stop-Start
Slope of this hit
Start number of this hit
Channel code of this hit
Register 9: Adr = 9
0 – 16
IFIFO2
17
Slope2
18 – 25
Start#2
26 – 27
ChaCode2
Time interval data from Interface FIFO2, Hit = Stop-Start
Slope of this hit
Start number of this hit
Channel code of this hit
Register 10: Adr = 10
0 – 16
Start01
17 – 27
-
Time interval between external start and first internal start
not used
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TDC-GPX
G-Mode
Register 8: Adr = 8
0 – 21
IFIFO1
22
Slope1
23 – 27
-
Time interval data from Interface FIFO1, Hit = Stop-Start
0 = falling edge, 1 = rising edge
not used
Register 9: Adr = 9
0 – 21
IFIFO2
22
Slope2
23 – 27
-
Time interval data from Interface FIFO2, Hit = Stop-Start
0 = falling edge, 1 = rising edge
not used
Register 10: Adr = 10
0 – 15
16 – 27
-
not used
not used
R-Mode & M-Mode
Register 8: Adr = 8
0 – 22
IFIFO1
23 – 27
-
Time interval data from Interface FIFO1, Hit = Stop-Start
not used
Register 9: Adr = 9
0 – 22
IFIFO2
23 – 27
-
Time interval data from Interface FIFO2, Hit = Stop-Start
not used
Register 10: Adr = 10
0 – 15
16 – 27
-
not used
not used
1.7.3 Read/Write registers
Register 11: Adr = 11
0–7
StopCounter0
8 – 15
StopCounter1
16 – 23
24 – 25
26
HFifoErrU
IFifoErrU
NotLockErrU
# of hits on DStop1,
I-Mode: not available
G-Mode: counting falling edge
R-Mode: counting rising edge
# of hits on DStop2,
I-Mode: not available
G-Mode: counting falling edge
R-Mode: counting rising edge
‘1’ unmasks full flags of Hit FIFOs to ErrFlag pin
‘1’ unmasks full flags of Interface FIFOs to ErrFlag pin
‘1’ unmasks ‘PLL not locked’ to ErrFlag pin
read only
read only
read/write
read/write
read/write
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TDC-GPX
Register 12: Adr = 12
0–7
HFifoFull
8–9
IFifoFull
10
NotLocked
11
HFifoE
12
TimerFlag
13 – 20
HFifoIntU
21 – 22
IFifoIntU
23
NotLockIntU
24
HFifioEU
25
TimerFlagU
26
Start#U
27
Service
Full flags of Hit FIFOs
Full flags of Interface FIFOs
‘PLL not locked’ flag
Falg indicating that all Hit FIFOs are empty
Flag indicating end of MTimer
‘1’ unmasks full flags of Hit FIFOs to IntFlag pin
‘1’ unmasks full flags of Interface FIFOs to IntFlag pin
‘1’ unmasks ‘PLL not locked’ to IntFlag pin
‘1’ unmasks ‘All Hit FIFOs empty’ to IntFlag pin
‘1’ unmasks end of MTimer to IntFlag pin
‘1’ unmasks highest bit of Start# (I-Mode) to IntFlag pin
Set to “0”
read only
read only
read only
read only
read only
read/write
read/write
read/write
read/write
read/write
read/write
read/write
HFifoFull and IFifoFull will be set back to "0" when reading register 12. They are re-activated by a master reset or
a partial reset.
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2 I-Mode
2.1 Block diagram I-Mode
TStop
1
TStart
TStop
2
TStop
3
7 MHz max.
at TStart
with
retrigger Input
Logic
40 MHz
clock
TStop
4
TStop
5
TStop
6
TStop
7
TStop
8
Input
Logic
Input
Logic
Input
Logic
200 MHz peak per TStop
Input
Logic
Input
Logic
Input
Logic
Input
Logic
Input
Logic
Slope
Slope
Slope
Slope
Slope
Slope
Slope
Slope
Internal
Start
generation
Measurement Core
Start
Fifo
Start select and
update logic
Startnumber
generation
Hit
Fifo1
Hit
Fifo2
Hit
Fifo3
Hit
Fifo4
Pipelined postprocessing
- compression
- Stop-Start-substraction
- data structure assembly
Hit
Fifo5
Hit
Fifo6
Collecting logic unit with
automatic bandwith distribution
28
28
Interface FIFO
28 x 256
28
Interface FIFO
28 x 256
40 MHz
max.
Read/Write
logic
28
40 MHz
max.
Data multiplexer
40 MHz
max.
WRN RDN CSN
32 cells
28
Collecting logic unit with
automatic bandwith distribution
Configuration
registers
Hit
Fifo8
Pipelined postprocessing
- compression
- Stop-Start-substraction
- data structure assembly
28
Start1 -Start0
register
Hit
Fifo7
Address
EF1
LF1
28 or 2x16
Databus
EF2
LF2
Figure 16: Block diagram
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2.2 Input circuitry I-Mode
Rise
Res
TStart
external
51K
pull-down
DStart
DStartN
0
+
TRiseEn[0]
Chan0
StartdDis
(pin)
1 S
Fall
Disable[0]
Res
TFallEn[0]
StartdDis
(pin)
InSelECL
Rise
Res
TStop1
external
51K
pull-down
DStop1
DStop1N
0
+
TRiseEn[1]
Chan1
StopDis1
(pin)
1 S
Fall
Disable[1]
Res
TFallEn[1]
StopDis1
(pin)
Rise
Res
TStop2
external
51K
pull-down
DStop2
DStop2N
0
+
TRiseEn[2]
Chan2
StopDis1
(pin)
1 S
Fall
Disable[2]
Res
TFallEn[2]
StopDis1
(pin)
Rise
Res
TStop7
external
51K
pull-down
0
TRiseEn[7]
Chan7
StopDis4
(pin)
1 S
Fall
Res
Disable[7]
TFallEn[7]
StopDis4
(pin)
Rise
Res
TStop8
external
51K
pull-down
0
TRiseEn[8]
Chan8
StopDis4
(pin)
1 S
Fall
Res
Disable[8]
TFallEn[8]
StopDis4
(pin)
Figure 17: Input circuitry
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2.3 I-Mode Basics
In this mode TDC-GPX offers
8 stop channels referring to 1 start channel,
Each of typ. 81 ps resolution
5.5 ns pulse-pair resolution
Start-retrigger up to 7 MHz
Unlimited measuring range with internal start retrigger
All inputs of LVTTL type
Selectable rising/falling edge sensitivity for all
channels
Several disable possibilities for all channels
Start Retrigger
After an initial start event, the TDC-GPX can generate
its own internal starts. This is controlled by the parameter “StartTimer” in register 4. The start retrigger
rate may not exceed 7 MHz.
Single Start
StartTimer = 0 switches off the internal Start genera17
tion. In this mode the measuring range is limited to 2
BIN ≈ 10.6 µs (@ BIN = 81 ps). Further pulses at
TStart will be ignored.
tph
Internal Start Retrigger
The period of the start repetition is programmable in
multiples of the 40 MHz reference clock between
(4+1) and (255+1) x 25ns (Register 4: StartTimer[7…0]).
The time interval between the initial, external start and
the first internal one will vary. It is therefore measured
and stored as ‘Start01’ in register 10. It can be read
out from this register as a 17 Bit integer in multiples
of BIN.
The time intervals between following starts are fixed
and referred to as (N +1) x Tref. Additionally, there is
an 8 Bit counter for the start number (Start#). The
start number is added to the output data.
A further option is to feed the highest bit of the Start
counter to the IrFlag output pin by setting register 11,
Bit 26 Start#U to one. With this signal the intenal
start number counter can externally be extended to
any size.
The internal start retrigger allows an unlimited
measuring range for the TDC-GPX.
Start
Stop
trr
tss
tph
tpl
tff
Figure 18: Measurement timings
Par.
t ph
t pl
t ss
Time (Condition)
Min.
Max.
1.5 ns
1.5 ns
0 ns min
9.4 µs
**5.2 ns *unlimited
5.5 ns typ.
#
6.9 ns max.
Description
Positive pulse width
Negative pulse width
Start to Stop
edge to edge
trr,
#
@ 87 ps resolution
t ff
*with int. start retrigger **with StopDisStart = 1
Input circuitry
The detailed input structure is shown in Figure 17:
Input circuitry. Each input separately can be set to be
sensitive to rising or falling edge. This is done in register0, TRiseEn[8…0] and TFallEn[8…0]. The LSB stands
for the TStart input, the MSB TStop8 input. A zero in
the channel bit for TRiseEn and TfallEn at the same
time disables the channel.
External Start Retrigger
A further option is to retrigger the Start externally.
This option is activated by setting StartTimer = 1 (Reg
4) and StartRetrig = 1 (Reg 5). The further behavior is
the same as for the internal start retrigger. The
maximum retrigger frequency is typically 7 MHz. The
time interval between two Starts is measured and
stored in the “Start01” register. This value is reasonable only if the delay between two Start pulses does
17
not exceed the measuring range of 2 BIN ≈ 10.6 µs.
All inputs can be disabled by hardware, the stop inputs
in pairs (pin ‘StopDis1’ disables inputs TStop1 and
TStop2, etc.). They also can be disabled by Software
setting the ‘Disable’ bits in register 2. The TDC-GPX
offers the possibility to disable the Stop inputs automatically until a Start is coming in. This is set by StopDisStart = ‘1’ in register 5.
Start01
measured
Figure 19
(N+1) * 25ns
fixed
(N+1) * 25ns
fixed
time
Asynchronous
Start
Start# 1
Start# 2
Start# 3
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With start retrigger the value StartOff1 should be set
to
StartOff1 = 2,000 (≈ 162 ns).
Start-Offset
For several reasons a mathematical offset is added to
the stop time. One reason is to allow handling StartStop intervals down to 0 and even less. This ‘StartOff1’
is set in register 5 in multiples of BIN and it is 18 Bit
wide. Internally the start offset is added to the time
measurement result and has to be subtracted from
the value read from the TDC. The other reason is to
allo the ALU to look "into the past" without handling
negative values (which the ALU could not do).
The reason is that the ALU is internally stopped for
about 50 ns during a start retrigger to add the new
start time stamp. If there is a hit on each channel
during this period the ALU will need
4 x 25 ns + 50 ns = 150 ns to transfer those data to
the IFIFO. The ALU cannot handle negative values.
Therefore the start offset is added so that
the ALU can handle the data being collected
during the break. In case the input data rate
is higher (bursts) it will be necessary to increase also the offset value , e.g. to 10,000.
Output data
Start#
Start01
Asynchronous
Start
Start# 2
Time
The start retrigger adds some indeterminacy
– due to the 25ns reference – to whether a
stop refers to the old start or the new one.
time
This is not an uncertainty. Each time stamp
that is negative after offset substraction can
be remapped to the old start by adding the
start period and reducing the start number by 1.
hit time
SyncPeriod
Start# 1
Time data
Start# 3
StartOff1
Figure 20
StopDisStart & StartDisStop
By default the Start and Stop inputs of the TDC-GPX
are open immediately after a reset.
The real time interval Start to Stop is calculated from
the output data as (Start# >0):
Time = (hittime - StartOff1 + Start01) * resolution +
(Start# - 1) * (StartTimer +1) * Tref
The consequence for the Stop channels is that even
hits coming before a Start pulse will be measured. The
bit StopDisStart in register 5 disables the Stop channels until there is a Start pulse. A consequence is that
there is a minimum delay of 7 ns after the Start before
hits are accepted on the Stop channels.
Adjusting the Start-Offset
The Start-Offset register of the TDC-GPX allows the
compensation for the offset due to the different internal delays. It allows to do measurements down to 0 ns
time intervals between Start and Stop. The correct
setting should be done by experiment.
With single-start and internal start-retrigger only the
first Start pulse is used for the measurement. In cases
where more than one Start pulse is expected this
might cause an overflow of the Hit FIFO of the Start
channel. This will produce garbage data. There we
recommend setting the StartDisStart bit in register 5.
A ‘1’ disables the Start channel after the first Start
pulse.
Procedure for single start applications:
1. Set StartOff1 = 0
2. Apply Start and Stop signals with a short delay
(e.g. 12ns)
3. Step down the interval and look at the output
data. They are getting smaller and smaller until
you pass the internal Start time stamp. The output data then jumps to a very high value.
4. Take the time interval t cross (from your generator)
where this happens
5. Calculate StartOff1 = t cross / BIN and write this
value into register 5, StartOff1. In case you expect negative values add an additional amount X
to StartOff1 and substract this value later on
from your output data
Internal Data Processing
The raw values of the stop events are stored in 32stage Hit FIFOs. One bit is added indicating the slope of
the signal. This Hit FIFO can be filled with data at a
peak rate of 182 MHz.
The following pipelined post-processing unit is responsible for compression, Start selection, correct StopStart subtraction and adding the start number to the
output data. Subsequently a collection unit transfers
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2.5 Reset
the data to the Interface FIFO, which is 256 stages
deep. This is done with respect to automatic bandwidth distribution. If a hit from one channel has been
processed, the neighbored channel gets highest priority for next operation. If there is no hit on the next, the
next sequential gets priority and so on. The maximum
rate for transfer into the Interface FIFO is 40 MHz. So
if there are hits on all channels equally distributed, the
maximum rate per channel is 10 MHz. If there are hits
on only one channel, this channel has 40 MHz maximum rate.
There are 3 ways of resetting the device:
Power-up reset: a low signal at pin PURESN
resets the whole chip.
Master-Reset: this command resets everything
except the configuration registers. It can be done
by software writing to register 4. When MasterAluTrig in register 5 is set to ‘1’ it can be done
also by a HIGH at the Alutrigger input pin.
Partial-Reset: this command resets everything
except the configuration registers and the Interface FIFOs. It can be done by software writing to
register 4. When PartialAluTrig in register 5 is
set to ‘1’ it can be done also by a HIGH at the
Alutrigger input pin.
Finally a data multiplexer adds data from both Interface FIFOs to the data bus. The data bus is 28 Bits
wide and capable of 40 MHz transfer rate. The data
bus can be switched to 16 Bit width writing
0x0000010 into address 14. A LOW at pin ‘Output
enable’ forces the bidirectional bus drivers to permanent output state. This is helpful for fast data read out
routines.
Each Interface FIFO has an empty flag (EF) and a loadlevel flag (LF). All flags are HIGH active. At low data
rates it is recommended to check the EF to see
whether there are data available for read out. It is not
allowed to read from an empty Interface FIFO. The LF
is helpful at high data rates. The load level threshold
can be set in ‘Fill’ in register 6 and is the same for
both FIFOs. As soon as the set number of data is available this can be read from the FIFO as a block without
the need of checking the EF.
Note: the load-level flags are not synchronized. The
load-level flag for a FIFO is valid only if it is not read
from this FIFO. Otherwise there might be spikes.
After a Power-on reset and a Master reset it takes 40
ns before the Start and Stop inputs accept data.
After a Partial reset it takes 75 ns before the Start
and Stop inputs accept data.
2.6 MTimer
There is an internal timer available for internal use.
The main application will be setting a dedicated time
interval between 25ns and 204.7 µs after which the
interrupt flag is set. The period is set in ‘MTimer’,
register 7, in multiples of Tref. The maximum delay is
8191 * Tref = 204.7 µs. The timer can be started by
a Stop and/or Start signal. This is set in ‘MTimerStart’
and ‘MTimerStop’, register 4. Setting Bit ‘TimerFlag’,
register 12, the interrupt flag is set when the timer
stops.
2.7 Interrupt Flag
2.4 Data structure
The user can select on which event(s) the interrupt
flag is set.
The selection is done in register 12, Bits 13 to 25, by
unmasking the dedicated bits. They are combined by
an Or-Gate to the interrupt flag.
Selectable events are
Hit FIFOs 1, 2 …or/and 8 are full
Interface FIFOs 1 or/and 2 are full
PLL not locked
All Hit FIFOs empty
End of Mtimer
The output data are integers with a BIN width defined
by the setting of the resolution adjust unit (1.6.1 Resolution adjust),
T × 2refclkdiv
BIN = ref
216 × hsdiv
Bits
27...26
Channel
code
Bits
Bit
Bits
25…18
17
16…0
Start#
Slope
Time interval data
= Start
Hit = Stop-Start
number
The time interval is calculated (externally) as:
If Start# is 0:
Time = 1 BIN(ps) * (Hit – StartOff1)
If Start# > 0:
Time = 1 BIN(ps) * (Hit – StartOff1 + Start01
+ (Start# - 1) * (StartTimer +1) * Tref
2.8 Error Flag
The user can select on which event(s) the error flag is
set.
The selection is done in register 11, Bits 16 to 26, by
unmasking the dedicated bits. They are combined by
an Or-Gate to the error flag.
Selectable events are
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Hit FIFOs 1, 2 …or/and 8 are full
Interface FIFOs 1, 2 …or/and 8 are full
PLL not locked
I-Mode, Standard deviation, TTL-inputs
1,6
1,4
2.9 Differential Inputs
1,2
Sigma (LSB)
It is possible to use the differential inputs also in IMode. Setting register 6, InSelECL= ‘1’ switches the
measurement channels to the two available differential
inputs.
The power for the differential inputs has to be
switched on separately by setting register 6, PowerOnECL = ‘1’.
1
0,8
0,6
0,4
0,2
0
0,0
2,0
4,0
2.10 I-Mode Timing & Resolution
Minimal
0.91 at 3.6V
0.889 at –40°C
0.74 at BC
8,0
10,0
Figure 21
DNL
the TDC-GPX shows a moderate differential nonlinearity (DNL) because internal propagation delays
were used for the time measurement and because
those delays are different for rising and falling edges.
But the variation from channel to channel is strongly
systematic. The following diagram shows the DNL data
at a resolution of 74 ps:
The delay parameters vary with voltage, temperature
and process tolerance. The following table lists the
derating factors.
Derating by
Voltage
Temperature
Process
6,0
Delay ∆t (µs)
Maximal
1.2 at 2.85V
1.17 at +125°C
1.31 at WC
With the stabilization of the resolution by the resolution adjust mode, the voltage of the core decreases
with decreasing temperature, and increases with increasing temperature. The setting should be done in a
way that at maximum operating temperature the
maximum core voltage is reached, and that minimum
core voltage is reached at minimum operating temperature. With this method you get two limits:
TDC-GPX: DNL, I-Mode
100
90
80
70
ps
60
50
40
Best case process, deepest temperature, lowest voltage: 0.74 x 0.889 x 1.2 = 0.789
Worst case process, highest temperature, highest
voltage: 1.31 x 1.17 x 0.91 = 1.394
30
20
10
139
133
127
121
115
109
97
103
91
85
79
73
67
61
55
49
43
37
31
25
19
13
7
1
0
Bin
With a typical resolution of 81 ps (typ. process, 25°C,
3.3 V) you get two limits for the resolution:
Resolution
Best
64 ps
Figure 22: DNL
INL
The integral non-linearity describes the deviation over
the full measuring range. The INL of the TDC-GPX for a
single Start-Stop measurement with a delay > 6 ns is
below our measurement capability and can be neglected. In the close-up region below 6 ns the deviation
is about 100 ps.
Worst
113 ps
The BIN or LSB width is defined by the setting of the
resolution adjust unit (1.6.1 Resolution adjust),
The standard deviation (1 σ) of the result is typically
0.9 LSB + 2,5ps * ∆t/µs.
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2.11 Measurement Flow
In the following we show two typical examples of register settings and measurement flow in I-Mode.
2.11.1 Single measurement
Task:
Measuring 8 channels within a window of 2 µs from Start.
//****** I-Mode, Stops against single Start **********
PuResN=Low;
PuResN=High;
// Power-up reset
StopDis1
StopDis2
StopDis3
StopDis4
// Disable inputs
=
=
=
=
High;
High;
High;
High;
_oupd( 0,0x007FC81);
_oupd( 1,0x0000000);
_oupd( 2,0x0000002);
_oupd( 3,0x0000000);
_oupd( 4,0x6000000);
_oupd( 5,0x0E004DA);
_oupd( 6,0x0000000);
_oupd( 7,0x0281FB4);
_oupd(11,0x7FF0000);
_oupd(12,0x2000000);
_oupd(14,0x0000000);
// write configuration registers:
// Rising edges, Start ringoscil.
// I-Mode
// Mtimes trig. by Start, EFlagHiZN
//StopDisStart, StartDisStart, StartOff1 = 100ns, MasterAluTrig
// Res = 82.3045ps
// Any error -> ErrFlag
// Mtimer -> IrFlag
_oupd( 4,0x6400000);
// Master reset
StopDis1
StopDis2
StopDis3
StopDis4
// Enable inputs
=
=
=
=
Low;
Low;
Low;
Low;
do
{
while(IrFlag=Low);
// Check interrupt flag
while((EF1=Low)or(EF2=Low))
{
if (EF1=Low)
{
data = _inpd(8);
Chan = (data & 0xC000000)>>26 + 1;
Time = (data & 0x1FFFF);
Printf(Chan,time);
}
if (EF2=Low)
{
data = _inpd(9);
Chan = ((data & 0xC000000)>>26) + 5;
Time = (data & 0x1FFFF);
Printf(Chan,time);
}
}
// Check empty flag
Alutrigger = High;
Alutrigger = Low;
// Data on IFIFO1?
// Read IFIFO1
// Get channel#
// Get time Stop-Start
// Data on IFIFO2?
// Read IFIFO2
// Get channel#
// Get time Stop-Start
// Master reset
} while(!quit)
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2.11.2 Continous Measurement
Task: Typical application fluorescence spectroscopy.
Measuring a continous signal stream using the internal start-retrigger.
//****** I-Mode, endless measurement range with internal start retrigger **********
PuResN=Low;
// Power-up reset
PuResN=High;
StopDis1 = High;
// Disable inputs
StopDis2 = High;
StopDis3 = High;
StopDis4 = High;
// write configuration registers:
_oupd( 0,0x007FC81);
// Rising edges, Start ringoscil.
_oupd( 1,0x0000000);
_oupd( 2,0x0000002);
// I-Mode
_oupd( 3,0x0000000);
_oupd( 4,0x2000027);
// StartTimer = 39 -> period = 1µs, EFlagHiZN
_oupd( 5,0x02004DA);
// StopDisStart, StartOff1 = 100ns
_oupd( 6,0x0000000);
_oupd( 7,0x0281FB4);
// Res = 82.3045ps
_oupd(11,0x7FF0000);
// Any error -> ErrFlag
_oupd(12,0x4000000);
// Start# overflow to IrFlag
_oupd(14,0x0000000);
_oupd( 4,0x6400027);
// Master reset
StopDis1 = Low;
// Enable inputs
StopDis2 = Low;
StopDis3 = Low;
StopDis4 = Low;
Wait(1µs);
// Wait until Start01 is available from register 10
Sta01 = -inpd(10)& 0xFFFF
// read Sta01 = interval first int. Start – ext. Start
do
{
if (EF1=Low)
// Data on IFIFO1?
{
data = _inpd(8);
// Read IFIFO1
Chan = (data & 0xC000000)>>26 + 1;
// Get channel#
Start = (data & 0x3FC0000)>>18;
// Get Start#
Time = (data & 0x1FFFF)-0x4DA;
// Get time Stop-Start
if (Time<0)
// Negative time refers to next start
{
Time = Time + 1µs;
// Remap time to old start
Start = Start –1
// Correct start number
}
Printf(Chan,Start,Time);
}
if (EF2=Low)
// Data on IFIFO2?
{
data = _inpd(9);
// Read IFIFO2
Chan = ((data & 0xC000000)>>26) + 5;
// Get channel#
Start = (data & 0x3FC0000)>>18;
// Get Start#
Time = (data & 0x1FFFF)-0x4DA;
// Get time Stop-Start
if (Time<0)
// Negative time refers to next start
{
Time = Time + 1µs;
// Remap time to old start
Start = Start –1
// Correct start number
}
Printf(Chan,Start,Time);
}
} while(!quit)
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3 G-Mode
3.1 Block diagram G-Mode
TStart1
(LVTTL)
DStart
(LVPECL)
TStop1
(LVTTL)
5 MHz max
DStop1
(LVPECL)
20 MHz cont. max
200 MHz peak max
TStop2
(LVTTL)
DStop2
(LVPECL)
20 MHz cont. max
200 MHz peak max
Input Logic
high
res
high
res
high
res
high
res
Measurement Core
Start
FIFO
Hit
FIFO1
Start
select
Logic
Stop1
value
Hit
FIFO2
Stop2
value
Hit
FIFO3
Hit
FIFO4
Hit
FIFO5
Hit
FIFO6
Hit
FIFO7
Hit
FIFO8
Stop3
value
Stop4
value
Stop5
value
Stop6
value
Stop7
value
Stop8
value
32 cells
Start
value
20 MHz
max.
Configuration
registers
20 MHz
max.
20 MHz
max.
20 MHz
max.
CLU1
CLU2
Interface Fifo1
28 x 256
Interface Fifo2
28 x 256
28
Read/Write
logic
40 MHz
max.
Data multiplexer
40 MHz
max.
4
WRN RDN CSN
28
40 MHz
max.
Address
LF1 EF1
28 or 2*16
Data bus
EF2 LF2
Figure 23
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3.2 Input Circuitry G-Mode
START: FallEn0
Rise
DStart
DStartN
+
DStart
-
TStart
Res
RiseEn0
0
1
≠ RiseEn0!
Chan0
StartdDis
(pin)
S
Fall
TStart
Disable[0]
Res
FallEn0
Chan1
StartdDis
(pin)
Rise
DStop1
+
DStop1N
-
DStop1
TStop1
Chan2
Res
0
1
Disable[1]
RiseEn1
StopDis1
(pin)
S
Chan3
Disable[2]
Fall
TStop1
Disable[3]
Chan4
Res
FallEn1
Chan5
StopDis2
(pin)
Rise
DStop2
+
DStop2N
-
DStop2
TStop2
Disable[5]
Res
StopDis3
(pin)
1 S
Fall
Chan7
Disable[6]
Disable[7]
Chan8
Res
FallEn2
StopDis4
(pin)
external pull-down resistors:
LVPECL
+
Chan6
RiseEn2
0
TStop2
Disable[4]
Disable[8]
GTest
51R
51R
LV-TTL
51K
Figure 24
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3.3 G-Mode Basics
In this mode the TDC-GPX offers:
Each STOP input has an 8 Bit stop counter, sensitive
to the falling edge. The number of hits for each input
can be read from register 11, StopCounter0 and
StopCounter1.
2 Stop channels referring to 1 start channel
Each of 36 ps resolution
Rising and Falling edge for pulse width measurement down to 1.5ns
Start-retrigger up to 5 MHz
4.7 ns pulse-pair resolution
0 to 65 µs measuring range
Minimum 32-fold multihit capability
Optional quiet mode
LVPECL inputs
Internally the Start is shifted by an offset (in multiples
of LSB). This allows measuring hits that arrive earlier
than the start signal and to measure down to 0.
Input circuitry
In G-Mode the TDC-GPX has differential low-voltage
PECL input buffers. The power for the differential inputs has to be switched on separately by setting register 6, PowerOnECL = ‘1’.
tph
Start
Stop
Alutrigger
trr
tss
tph
tpl
The detailed input structure is shown in Figure 24.
Each input separately can be set to be sensitive to
rising and/or falling edge. This is done in register0,
RiseEn0..2 and FallEn0..2. A zero in both bits for one
channel at the same time disables the channel.
trr
tva
EF
Figure 25. Measurement timings
Parameter
t ph
t pl
t ss
t r f,fr
Time (Condition)
1.5 ns (min.)
1.5 ns (min.)
0 ns min
*5.2 ns min
64 µs (max)
5.5 ns typ.
#
6.9 ns max.
1.5 ns (typ.)
t va
107 ns (max.)
t r r , t ff
All inputs can be disabled by hardware, the stop inputs
separately for rising and falling edges (pin ‘StopDis1’
disables inputs DStop1, rising edge etc.).
They also can be disabled by software setting the ‘Disable’ in register 2. The ‘Disable’ bits have to be set in
pairs, e.g Disable3 and Disable4 to disable Dstop,
falling edge.
Description
Positive pulse width
Negative pulse width
Start to Stop
*with StopDisStart = 1
equal edge to edge
#
@ 87 ps resolution
Falling edge to rising
edge and v.v.
ALU start to data valid
StopDisStart & StartDisStop
By default the Start and Stop inputs of the TDC-GPX
are open immediately after a reset.
The consequence for the Stop channels is that even
hits coming before a Start pulse will be measured. The
bit StopDisStart in register 5 disables the Stop channels until there is a Start pulse. A consequence is that
there is a minimum delay of 7 ns after the Start before
hits are accepted on the Stop channels.
In this mode the TDC-GPX has two independent STOP
input channels, each one capable of measuring the
rising and falling edge at the same time. Each channel
can store minimum 32 hits.
With single-start only the first Start pulse is used for
the measurement. In case more than one Start pulse
is expected this might cause an overflow of the Hit
FIFO of the Start channel. This will produce garbage
data. There we recommend setting the StartDisStart
bit in register 5. A ‘1’ disables the Start channel after
the first Start pulse.
External Start Retrigger
A further option is to retrigger the Start externally.
This option is activated by setting StartRetrig = 1 (Reg
5). The maximum retrigger frequency is limited to
typically 5 MHz. Higher rates will disturb the chip.
For improvement of the measurement accuracy, two
channels are internally combined, which leads to a
resolution of typical 40 ps. The paired channels are
called combined channels. Each one of these combined
channels measures rising or falling edges of one sampling channel. With this method it is possible to measure pulses with a pulse-width down to the minimum
pulse-width allowed by the differential inputs, which is
typ. 1.5 ns. Two adjacent rising or falling edges on a
sampling channel may have a delay of down to 5.5 ns
(typ.).
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FIFO is 40 MHz, 20 MHz for rising edge data and 20
MHz for falling edge data.
Start-Offset
For several reasons a mathematical offset is added to
the stop time. One reason is to compensate for different internal delays from the input buffers to the TDC
unit in the Start and Stop paths. The other reason is to
allo the ALU to look "into the past" without handling
negative values (which the ALU could not do). It allows
handling Start-Stop intervals down to 0 and even less.
In G-Mode the TDC-GPX creates a second pulse on the
Start channel by its own. Therefore two offset values
have to be set. ‘StartOff1’ in register 5 and StartOff2
in register 6, both in multiples of BIN and 18 bits wide.
Internally the start offset is added to the time measurement result and has to be subtracted from the
value read from the TDC.
Finally a data multiplexer adds data from both Interface FIFOs to the data bus. The data bus is 28 Bits
wide and capable of 40 MHz transfer rate. The data
bus can be switched to 16 Bit width writing
0x0000010 into address 14. A LOW at pin ‘Output
enable’ forces the bidirectional bus drivers to permanent output state. This is helpful for fast data read out
routines.
Each Interface FIFO has an empty flag (EF) and a loadlevel flag (LF). All flags are HIGH active. At low data
rates it is recommended to check the EF to see
whether there are data available for read out. It is not
allowed to read from an empty Interface FIFO. The LF
is helpful at high data rates. The load level threshold
can be set in ‘Fill’ in register 6 and is the same for
both FIFOs. As soon as the set number of data is available this can be read from the FIFO as a block without
the need of checking the EF.
Note: the load-level flags are not synchronized. The
load-level flag for a FIFO is valid only if it is not read
from this FIFO. Otherwise there might be spikes.
Adjusting the Start-Offset
The Start-Offset register of the TDC-GPX allows the
compensation for the offset due to the different internal delays. It allows to do measurements down to 0 ns
time intervals between Start and Stop. The correct
setting should be done by experiment.
Procedure:
1. Set StartOff1= StartOff2 = 0
2. Apply Start and Stop signals with a short delay (e.g.
12ns)
3. Step down the interval and look at the output data.
They are getting smaller and smaller until you pass
the first internal Start time stamp. The output data
then jumps to a very high value.
4. Take the time interval t cross1 (from your generator)
where this happens
5. Calculate StartOff1 = t cross1 / BIN and write this
value into register 5, StartOff1
6. Continue stepping down the time interval until you
see the same effect as in 3
7. Take the time interval t cross2 (from your generator)
and calculate StartOff2 = t cross2 / BIN
8. Write this value into register 6
Quiet Mode
TDC-GPX offers two options for the post-processing:
Quiet Mode
Non-quiet Mode
In Quiet Mode the post-processing and calculation
does not start automatically after each single event,
but after a dedicated trigger. The trigger can be given
externally by a rising slope at pin ALUTRIGGER or by
software setting a dedicated ALU-Trigger Bit. This
mode is introduced to reduce the noise during a
measurement and to allow the small values for pulsepair and pulse-width resolution.
In the Non-quiet Mode, the post-processing starts
immediately after the first hit arrived in a raw FIFO.
The post-processing doesn’t start before there is a
START signal and at least one STOP signal.
The time needed from the start of the post-processing
until first data is available in the interface FIFO is typ.
200 ns.
Internal Data Processing
The raw values of the stop events are stored in 32stage Hit FIFOs. This Hit FIFO can be filled with data at
a peak rate of 182 MHz.
The following pipelined post-processing unit is responsible for compression, Start selection and correct
Stop-Start subtraction. Subsequently a collection unit
transfers the data to the Interface FIFOs, which are
256 stages deep. Each channel has its own interface
FIFO. The maximum rate for transfer into the Interface
3.4 Data structure and readout
The output data are integers with a LSB width defined
by the setting of the resolution adjust unit.
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BIN =
Bit22
1=rising edge
0=falling edge
3.7 Interrupt Flag
Tref × 2refclkdiv 1
×
216 × hsdiv
2
The user can select on which event(s) the interrupt
flag is set.
The selection is done in register 12, Bits 13 to 25, by
unmasking the dedicated bits. They are combined by
an Or-Gate to the interrupt flag.
Selectable events are
Hit FIFOs 1, 2 …or/and 8 are full
Interface FIFOs 1 or/and 2 are full
PLL not locked
All Hit FIFOs empty
End of Mtimer
Bit21..0
Edge-to-Start result of the addressed combined channel
The data can be read from address 8 for interface
FIFO1 (DStop1) and from address 9 for interface
FIFO2 (DStop2).
3.5 Reset
There are 3 ways of resetting the device:
Power-up reset: a low signal at pin PURESN
resets the whole chip.
Master-Reset: this command resets everything
except the configuration registers. It can be done
by software writing to register 4. In non-quiet
mode MasterAluTrig in register 5 can be set to
‘1’. Then this command can be done also by a
HIGH at the Alutrigger input pin. In quiet mode
MasterOenTrig in register 5 can be set to ‘1’.
Then this command can be done also by a LOW at
the OEN input pin (only with OEN off).
Partial-Reset: this command resets everything
except the configuration registers and the Interface FIFOs. It can be done by software writing to
register 4. In non-quiet mode Partial-AluTrig in
register 5 can be set to ‘1’. Then this command
can be done also by a HIGH at the Alutrigger input pin. In quiet mode PartialOenTrig in register 5
can be set to ‘1’. Then this command can be done
also by a LOW at the OEN input pin (only with OEN
off).
3.8 Error Flag
The user can select on which event(s) the error flag is
set.
The selection is done in register 11, Bits 16 to 26, by
unmasking the dedicated bits. They are combined by
an Or-Gate to the error flag.
Selectable events are
Hit FIFOs 1, 2 …or/and 8 are full
Interface FIFOs 1, 2 …or/and 8 are full
PLL not locked
3.9 Testinputs
For test purpose a set of three TTL inputs can be multiplexed to the measuring circuit by setting Bit Gtest in
register 3. The test inputs have the same functionality
as the measure inputs, but can only handle a minimum
pulse width of 5ns and a minimum edge-to-edge distance of 20ns.
3.10 RaSpeed & Delx
The on-chip timings for measuring rising and falling
edge down to 1.5 ns are very critical. For some chips
it might be necessary to add an internal, additional
delay to guarantee correct data processing. These
delays are set by the RaSpeed bits and the DelRisex/DelFallx/DelTx in registers 2, 3 and 4. Increasing those will reduce the pulse-pair resolution of the
TDC-GPX .
RaSpeed & Delx
Pulse-pair resolution
0
5.5 ns
1
6.5 ns
2
7.5 ns
3
8.5 ns
After a Power-on reset or a Master reset it takes 40
ns before the Start and Stop inputs accept data.
After a Partial reset it takes 75 ns before the Start
and Stop inputs accept data.
3.6 MTimer
There is an internal timer available for internal use.
The main application will be setting a dedicated time
interval between 25ns and 204.7 µs after which the
interrupt flag is set. The period is set in ‘MTimer’,
register 7, in multiples of Tref. The maximum delay is
8191 * Tref = 204.7 µs. The timer can be started by
a Stop and/or Start signal. This is set in ‘MTimerStart’
and ‘MTimerStop’, register 4. Setting Bit ‘TimerFlag’,
register 12, the interrupt flag is set when the timer
stops.
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3.11 G-Mode Timing & Resolution
Standard deviation, G-Mode, TTL-inputs
The delay parameters vary with voltage, temperature
and process tolerance. The following table lists the
derating factors.
Minimal
0.91 at 3.6V
0.889 at –40°C
0.74 at BC
Sigma (LSB)
Derating by
Voltage
Temperature
Process
9
8
Maximal
1.2 at 2.85V
1.17 at +125°C
1.31 at WC
7
6
5
4
3
2
1
0
With the stabilization of the resolution by the resolution adjust mode, the voltage of the core decreases
with decreasing temperature, and increases with increasing temperature. The setting should be done in a
way that at maximum operating temperature the
maximum core voltage is reached, and that minimum
core voltage is reached at minimum operating temperature. With this method you get two limits:
0
30
40
50
60
70
Figure 26
DNL
the TDC-GPX shows a moderate differential nonlinearity (DNL) because internal propagation delays
were used for the time measurement and because
those delays are different for rising and falling edges,
but the variation from channel to channel is systematic. The following diagram shows the DNL data at a
resolution of 37 ps:
TDC-GPX: DNL, G-Mode
With a typical resolution of 40ps (typ. process, 25°C,
3.3V) you get two limits for the resolution:
60
50
Worst
56 ps
40
ps
30
20
The BIN or LSB width is defined by the setting of the
resolution adjust unit (1.6.1 Resolution adjust),
The standard deviation (1 σ) of the result is typically 1
LSB + 4 ps * ∆t/µs.
10
Bin
Figure 27
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116
111
106
96
101
91
86
81
76
71
66
61
56
51
46
41
36
31
26
21
16
11
1
0
6
Resolution (of
combined channels)
20
Delay ∆t
∆ (µs)
Best case process, deepest temperature, lowest voltage: 0.74 x 0.889 x 1.2 = 0.789
Worst case process, highest temperature, highest
voltage: 1.31 x 1.17 x 0.91 = 1.394
Best
32 ps
10
TDC-GPX
3.12 Measurement Flow
In the following we shows a typical example of register settings and measurement flow in G-Mode.
Task: Typical application laser rangefinder
Measuring Stops on 2 channels, rising and falling edge, within a window of 1 µs from Start.
//****** G-Mode, Stops against single Start **********
PuResN=Low;
PuResN=High;
// Power-up reset
StopDis1
StopDis2
StopDis3
StopDis4
// Disable inputs
=
=
=
=
High;
High;
High;
High;
_oupd( 0,0x00000FF);
_oupd( 1,0x5050500);
_oupd( 2,0x0050001);
_oupd( 3,0x0000000);
_oupd( 4,0x6000000);
_oupd( 5,0x0E00080);
_oupd( 6,0x0100000);
_oupd( 7,0x0141FB4);
_oupd(11,0x7FF0000);
_oupd(12,0x2000000);
_oupd(14,0x0000000);
// write configuration registers:
// Rising and falling edges, Start ringoscil.
// Channel adjust = 5 for each second stop channel
// G-Mode, channel adjust = 5
// Use differential inputs
// Mtimes trig. by Start, EFlagHiZN
//StopDisStart, StartDisStart, StartOff1 = 10ns, MasterAluTrig
// StartOff2 = 20ns
// Res = 41.1523ps, Mtimer = 1µs
// Any error -> ErrFlag
// Mtimer -> IrFlag
_oupd( 4,0x6400000);
// Master reset
StopDis1
StopDis2
StopDis3
StopDis4
// Enable inputs
=
=
=
=
Low;
Low;
Low;
Low;
do
{
while(IrFlag=Low);
// Check interrupt flag
while((EF1=Low)or(EF2=Low))
{
if (EF1=Low)
{
data = _inpd(8);
Chan = 1;
Edge = ((data & 0x0400000)>>26) + 1;
Time = (data & 0x3FFFFF);
Printf(Chan,Edge,Time);
}
if (EF2=Low)
{
data = _inpd(9);
Chan = 2;
Edge = ((data & 0x0400000)>>26) + 5;
Time = (data & 0x3FFFFF);
Printf(Chan,Edge,Time);
}
}
Alutrigger = High;
Alutrigger = Low;
} while(!quit)
// Check empty flag
// Data on IFIFO1?
//
//
//
//
Read IFIFO1
Channel#
Get edge
Get time Stop-Start
// Data on IFIFO2?
//
//
//
//
Read IFIFO2
Channel#
Get edge
Get time Stop-Start
// Master reset
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4 R-Mode
4.1 Block diagram R-Mode
TStart1
DStart
(LVTTL) (LVPECL)
DStop1
(LVPECL)
TStop1
(LVTTL)
9 MHz max.
TStop2
(LVTTL)
DStop2
(LVPECL)
20 MHz max.
200 MHz peak
20 MHz max.
200 MHz peak
Input Logic
high
res
Start
FIFO
Start
FIFO1
high
res
high
res
Measurement Core
Hit
Hit
Hit
FIFO3 FIFO4 FIFO5
Start
FIFO2
Stop1a
value
Start
select
Logic
Stop1b
value
Hit
FIFO6
Hit
FIFO7
Hit
FIFO8
Stop2a
value
Stop2b
value
Stop2c
value
Stop1c
value
40 MHz
28
Read/Write
logic
Interface Fifo2
28 x 256
40 MHz
max.
40 MHz
max.
28
Data multiplexer
40 MHz
max.
4
WRN RDN CSN
40 MHz
Interface Fifo1
28 x 256
Configuration
registers
32 cells
Address
LF1 EF1
28 or 2x16
Data bus
EF2 LF2
Figure 28
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4.2 Input Circuitry R-Mode
Chan0
Rise
DStart
+
DStartN
DStart
-
TStart
START: FallEn
Disable[0]
Res
RiseEn0
0
1
≠ RiseEn!
Chan1
StartdDis
(pin)
S
Fall
TStart
Disable[1]
Chan2
Res
Disable[2]
FallEn0
StartdDis
(pin)
Chan3
RiseEn1
Chan4
Rise
DStop1
+
DStop1N
-
DStop1
TStop1
0
1
Disable[3]
Res
StopDis1
(pin)
S
Fall
TStop1
Disable[4]
Chan5
Res
Disable[5]
FallEn1
StopDis2
(pin)
Chan6
Rise
DStop2
+
DStop2N
-
DStop2
TStop2
Disable[6]
Res
RiseEn2
0
Chan7
StopDis3
(pin)
1 S
Fall
TStop2
Disable[7]
Chan8
Res
FallEn2
Disable[8]
StopDis4
(pin)
external pull-down resistors:
GTest
LVPECL
+
51R
51R
LV-TTL
51K
Figure 29
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4.3 R-Mode Basics
In this mode the TDC-GPX offers:
2 Stop channels referring to 1 start channel
Each of 27 ps resolution
Start-retrigger up to 9 MHz
Rising or falling edge
5.5 ns pulse-pair resolution
0 to 40 µs measuring range
Minimum 32-fold multihit capability
Optional quiet mode
LVPECL inputs
Internally the Start is shifted by an offset (in multiples
of LSB). This allows measuring hits that arrive earlier
than the start signal and to measure down to 0 ns.
Input circuitry
In R-Mode the TDC-GPX has differential low-voltage
PECL input buffers. The power for the differential inputs has to be switched on separately by setting register 6, PowerOnECL = ‘1’.
tph
The detailed input structure is shown in Figure 29.
Each input can be set to be sensitive to rising or falling
edge. This is done in register0, RiseEn0..2 and
FallEn0..2. A zero in both bits for one channel at the
same time disables the channel.
Start
Stop
Alutrigger
trr
tss
tph
tpl
trr
All inputs can be disabled by hardware, the stop inputs
separately for rising and falling edges (pin ‘StopDis1’
disables inputs DStop1,rising edge etc.).
They also can be disabled by software setting the ‘Disable’ in register 2. The ‘Disable’ bits have to be set in
triples, e.g Disable3, Disable4 and Disable5 to disable
DStop1.
tva
EF
Figure 30 Measurement timings
Parameter
t ph
t pl
t ss
t r r , t ff
t va
Time (Condition)
1.5 ns (min.)
1.5 ns (min.)
0 ns (min)
*5.2 ns (min)
40 µs (max.)
5.5 ns typ.
#
6.9 ns max.
107 ns (max.)
Description
Minimum pulse width
Minimum pulse width
Start to Stop
StopDisStart & StartDisStop
By default the Start and Stop inputs of the TDC-GPX
are open immediately after a reset.
*with StopDisStart = 1
edge to edge
#
@ 87 ps resolution
ALU start to data valid
The consequence for the Stop channels is that even
hits coming before a Start pulse will be measured. The
bit StopDisStart in register 5 disables the Stop channels until there is a Start pulse. A consequence is that
there is a minimum delay of 7 ns after the Start before
hits are accepted on the Stop channels.
In this mode the TDC-GPX has two independent STOP
input channels, each one capable of measuring the
rising or falling. Each channel can store a minimum of
32 hits.
With single-start only the first Start pulse is used for
the measurement. In case more than one Start pulse
is expected this might cause an overflow of the Hit
FIFO of the Start channel. This will produce garbage
data. There we recommend setting the StartDisStart
bit in register 5. A ‘1’ disables the Start channel after
the first Start pulse.
For improvement of the measurement accuracy, three
channels are internally combined, which leads to a
resolution of typical 27 ps. The trebled channels are
called combined channels. Each one of these combined
channels measures rising or falling edges of one sampling channel. Two adjacent rising or falling edges on a
sampling channel may have a delay of down to 5.5 ns
(typ.).
Each STOP input has an 8 Bit stop counter, sensitive
to the rising edge. The number of hits for each input
can be read from register 11, StopCounter0 and
StopCounter1.
External Start Retrigger
A further option is to retrigger the Start externally.
This option is activated by setting StartRetrig = 1 (Reg
5). The maximum retrigger frequency is limited to
typically 9 MHz. Higher rates will disturb the chip.
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old start or the new one. This is not an uncertainty.
Each time stamp that is negative after offset substraction can be remapped to the old start by adding the
start period.
Start-Offset
For several reasons a programmable offset is added
to the stop time. One reason is to compensate for
different internal delays from the input buffers to the
TDC unit in the Start and Stop paths. The other reason
is to allo the ALU to look "into the past" without handling negative values (which the ALU could not do). It
allows handling Start-Stop intervals down to 0 and
even less. The offset value ‘StartOff1’ is set in register
5 in multiples of 3 x BIN and 18 bits wide. Internally
the start offset is added to the time measurement
result and has to be subtracted from the value read
from the TDC.
Internal Data Processing
The raw values of the stop events are stored in 32stage Hit FIFOs. This Hit FIFO can be filled with data at
a peak rate of 182 MHz.
The following pipelined post-processing unit is responsible for compression, Start selection and correct
Stop-Start subtraction. Subsequently a collection unit
transfers the data to the Interface FIFOs, which are
256 stages deep. Each channel has its own interface
FIFO. The maximum rate for transfer into the Interface
FIFO is 40 MHz.
Adjusting the Start-Offset
The Start-Offset register of the TDC-GPX allows the
compensation for the offset due to the different internal delays. It allows to do measurements down to 0 ns
time intervals between Start and Stop. The correct
setting should be done by experiment.
Finally a data multiplexer adds data from both Interface FIFOs to the data bus. The data bus is 28 Bits
wide and capable of 40 MHz transfer rate. The data
bus can be switched to 16 Bit width writing
0x0000010 into address 14. A LOW at pin ‘Output
enable’ forces the bidirectional bus drivers to permanent output state. This is helpful for fast data read out
routines.
Each Interface FIFO has an empty flag (EF) and a loadlevel flag (LF). All flags are HIGH active. At low data
rates it is recommended to check the EF to see
whether there are data available for read out. It is not
allowed to read from an empty Interface FIFO. The LF
is helpful at high data rates. The load level threshold
can be set in ‘Fill’ in register 6 and is the same for
both FIFOs. As soon as the set number of data is available this can be read from the FIFO as a block without
the need of checking the EF.
Procedure for single start applications:
1. Set StartOff1 = 0
2. Apply Start and Stop signals with a short delay (e.g.
12ns)
3. Step down the interval and look at the output data.
They are getting smaller and smaller until you pass
the internal Start time stamp. The output data then
jumps to a very high value.
4. Take the time interval t cross (from your generator)
where this happens
5. Calculate StartOff1 = t cross / 3 x BIN and write this
value into register 5, StartOff1. In case you expect
negative values add an additional amount X to StartOff1 and substract this value later on from your
output data
Note: the load-level flags are not synchronized. The
load-level flag for a FIFO is valid only if it is not read
from this FIFO. Otherwise there might be spikes.
With start retrigger the value StartOff1 should be set
to
StartOff1 = 1,000 (≈ 81 ns).
The reason is that the ALU is internally stopped for
about 50 ns during a start retrigger to add the new
start time stamp. If there is a hit during this period the
ALU will need
25 ns + 50 ns = 75 ns to transfer those data to the
IFIFO. The ALU cannot handle negative values. Therefore the start offset is added so that the ALU can
handle the data being collected during the break. In
case the input data rate is higher (bursts) it might be
necessary to increase also the offset value , e.g. to
10,000.
The start retrigger adds some indeterminacy – due to
the 25ns reference – to whether a stop refers to the
Quiet Mode
TDC-GPX offers two options for the post-processing:
Quiet Mode
Non-quiet Mode
In Quiet Mode the post-processing and calculation
does not start automatically after each single event,
but after a dedicated trigger. The trigger can be given
externally by a rising slope at pin ALUTRIGGER or by
software setting a dedicated ALU-Trigger Bit. This
mode is introduced to reduce the noise during a
measurement and to allow the small values for pulsepair and pulse-width resolution.
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interval between 25ns and 204.7 µs after which the
interrupt flag is set. The period is set in ‘MTimer’,
register 7, in multiples of Tref. The maximum delay is
8191 * Tref = 204.7 µs. The timer can be started by
a Stop and/or Start signal. This is set in ‘MTimerStart’
and ‘MTimerStop’, register 4. Setting Bit ‘TimerFlag’,
register 12, the interrupt flag is set when the timer
stops.
In the Non-quiet Mode, the post-processing starts
immediately after the first hit arrived in a raw FIFO.
The post-processing doesn’t start before there is a
START signal and at least one STOP signal.
The time needed from the start of the post-processing
until first data is available in the interface FIFO is typ.
200 ns.
4.4 Data structure and readout
4.7 Interrupt Flag
The output results are integers with a LSB width defined by the setting of the resolution adjust unit.
T × 2refclkdiv 1
BIN = ref
×
216 × hsdiv
3
Bit 27 … 23
Not used
The user can select on which event(s) the interrupt
flag is set.
The selection is done in register 12, Bits 13 to 25, by
unmasking the dedicated bits. They are combined by
an Or-Gate to the interrupt flag.
Selectable events are
Hit FIFOs 1, 2 …or/and 8 are full
Interface FIFOs 1 or/and 2 are full
PLL not locked
All Hit FIFOs empty
End of Mtimer
Bit 22...0
Edge-to-Start result of the addressed combined channel
The data can be read from address 8 for interface
FIFO1 and from address 9 for interface FIFO2.
4.5 Reset
4.8 Error Flag
There are 3 ways of resetting the device:
Power-up reset: a low signal at pin PURESN
resets the whole chip.
Master-Reset: this command resets everything
except the configuration registers. It can be done
by software writing to register 4. In non-quiet
mode MasterAluTrig in register 5 can be set to
‘1’. Then this command can be done also by a
HIGH at the Alutrigger input pin. In quiet mode
MasterOenTrig in register 5 can be set to ‘1’.
Then this command can be done also by a LOW at
the OEN input pin (only with OEN off).
Partial-Reset: this command resets everything
except the configuration registers and the Interface FIFOs. It can be done by software writing to
register 4. In non-quiet mode Partial-AluTrig in
register 5 can be set to ‘1’. Then this command
can be done also by a HIGH at the Alutrigger input pin. In quiet mode PartialOenTrig in register 5
can be set to ‘1’. Then this command can be done
also by a LOW at the OEN input pin (only with OEN
off).
The user can select on which event(s) the error flag is
set.
The selection is done in register 11, Bits 16 to 26, by
unmasking the dedicated bits. They are combined by
an Or-Gate to the error flag.
Selectable events are
Hit FIFOs 1, 2 …or/and 8 are full
Interface FIFOs 1, 2 …or/and 8 are full
PLL not locked
4.9 Testinputs
For test purpose a set of three TTL inputs can be multiplexed to the measuring circuit by setting Bit Gtest in
register 3. The test inputs have the same functionality
as the measure inputs, but can only handle a minimum
pulse width of 5ns and a minimum edge-to-edge distance of 20ns.
4.10 RaSpeed & Delx
The on-chip timings for measuring rising and falling
edge down to 1.5 ns are very critical. For some chips
it might be necessary to add an internal, additional
delay to guarantee correct data processing. These
delays are set by the RaSpeed bits and the DelRisex/DelFallx/DelTx in registers 2, 3 and 4. Increasing those will reduce the pulse-pair resolution of the
TDC-GPX .
RaSpeed & Delx
Pulse-pair resolution
1
5.5 ns
2
6.5 ns
3
7.5 ns
After a Power-on reset or a Master reset it takes 40
ns before the Start and Stop inputs accept data.
After a Partial reset it takes 75 ns before the Start
and Stop inputs accept data.
4.6 MTimer
There is an internal timer available for internal use.
The main application will be setting a dedicated time
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The standard deviation (1 σ) of the result is typically
1.4 LSB + 2,8 ps * ∆t/µs.
4
8.5 ns
The on-chip timings for measuring rising and falling
edge down to 1.5 ns are very critical. For some chips
it might be necessary to add an internal, additional
delay to guarantee correct data processing. These
delays are set by the RaSpeed bits and the DelRisex/DelFallx/DelTx in registers 2, 3 and 4. Increasing those will reduce the pulse-pair resolution of the
TDC-GPX .
RaSpeed & Delx
Pulse-pair resolution
0
5.5 ns
1
6.5 ns
2
7.5 ns
3
8.5 ns
R-Mode, Standard deviation, TTL-inputs
7
6
Sigma (LSB)
5
1
0
0,0
Process
5,0
10,0
15,0
20,0
25,0
30,0
35,0
40,0
45,0
Delay ∆ t (µs)
Figure 31
The pulse width limit is 1.5 ns typically, limited by the
input buffers.
TDC-GPX is working in resolution adjust mode. The
resolution adjust unit is identical with TDC-F1’s unit.
The delay parameters vary with voltage, temperature
and process tolerance. The following table lists the
derating factors.
Minimal
0.91 at 3.6V
0.889 at –
40°C
0.74
3
2
4.11 R-Mode Timing & Resolution
Derating by
Voltage
Temperature
4
The measurement range depends on the bin size and
the coarse counter. Its typical value is:
Measurement range
= 54 x 32767 x 27 ps
= 47 µs
DNL
The TDC-GPX shows a moderate differential nonlinearity (DNL) because internal propagation delays
were used for the time measurement and because
those delays are different for rising and falling edges,
but the variation from channel to channel is systematic. The following diagram shows the DNL data at a
resolution of 27 ps:
Maximal
1.2 at 2.85V
1.17 at
+125°C
1.31
With the stabilization of the resolution by the resolution adjust mode, the voltage of the core decreases
with decreasing temperature, and increases with increasing temperature. The setting should be done in a
way that at maximum operating temperature the
maximum core voltage is reached, and that minimum
core voltage is reached at minimum operating temperature. With this method you get two limits:
TDC-GPX: DNL, R-Mode
35
30
25
Best case process, deepest temperature, lowest voltage: 0.74 x 0.889 x 1.2 = 0.789
Worst case process, highest temperature, highest
voltage: 1.31 x 1.17 x 0.91 = 1.394
ps
20
15
10
From validation measurement the typical BIN size has
been 27 ps (typ. process, 25°C, 3.3V). With the abovementioned derating factors this gives two limits for the
resolution:
5
BIN
Resolution
Best
21 ps
Worst
38 ps
Figure 32
The BIN or LSB width is defined by the setting of the
resolution adjust unit (1.6.1 Resolution adjust),
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151
145
139
133
127
121
115
109
97
103
91
85
79
73
67
61
55
49
43
37
31
25
19
13
7
1
0
TDC-GPX
4.12 Measurement Flow
In the following we shows a typical example of register settings and measurement flow in R-Mode.
Task1: Typical application spectroscopy or testing.
Given a Start signal with 1 MHz rate. To each Start there is one Stop event on channel 1. The time between Stop
and Start shall be measured with high resolution, using the LVTTL inputs.
Choice: R-Mode with Start retrigger, using the Fill level flags.
//****** R-Mode, Stop against Start **********
PuResN=Low;
PuResN=High;
// Power-up reset
StopDis1
StopDis2
StopDis3
StopDis4
// Disable inputs
=
=
=
=
High;
High;
High;
High;
_oupd( 0,0x000009F);
_oupd( 1,0x0620620);
_oupd( 2,0x0062004);
_oupd( 3,0x8000000);
_oupd( 4,0x2000000);
_oupd( 5,0x80004DA);
_oupd( 6,0x00000C8);
_oupd( 7,0x0001FB4);
_oupd(11,0x7FF0000);
_oupd(12,0x0000000);
_oupd(14,0x0000000);
//
//
//
//
//
//
//
//
//
//
//
write configuration registers:
Rising and falling edges, Start ringoscil.
Channel adjust = 6 & 2
R-Mode, channel adjust = 6 & 2
Use LVTTL inpus
EFlagHiZN
StartOff1 = 100ns, StartRetrigger
Fill = 200
Res = 27.4348ps
Any error -> ErrFlag
No IrFlag
_oupd( 4,0x2400001);
// Master reset
StopDis1
StopDis2
StopDis3
StopDis4
// Enable inputs
=
=
=
=
Low;
Low;
Low;
Low;
do
{
if (LF1=High)
{
for (i=0;i<200,I++)
{
data = _inpd(8);
Time = (data & 0x7FFFFF)-3*0x4DA;
Printf(Time);
}
}
} while(!quit)
// Fill level=200 IFIFO1 reached?
// Read 200 times
// Read IFIFO1
// Get time Stop-Start
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Task2: Typical application laser rangefinder
Given a Start signal with 10 kHz rate. To each Start there is an unknown number of Stops on channel 1. The
maximum range is 1 µs. The time between Stop and Start shall be measured with very high resolution, using the
LVPECL inputs.
Choice: R-Mode with quiet mode and internal Timer.
//****** R-Mode, Stop against Start **********
PuResN=Low;
PuResN=High;
// Power-up reset
StopDis1
StopDis2
StopDis3
StopDis4
// Disable inputs
=
=
=
=
High;
High;
High;
High;
_oupd( 0,0x000009F);
_oupd( 1,0x0620620);
_oupd( 2,0x0062004);
_oupd( 3,0x0000000);
_oupd( 4,0x6000100);
_oupd( 5,0x00004DA);
_oupd( 6,0x8000000);
_oupd( 7,0x0141FB4);
_oupd(11,0x7FF0000);
_oupd(12,0x2000000);
_oupd(14,0x0000000);
//
//
//
//
//
//
//
//
//
//
//
write configuration registers:
Rising and falling edges, Start ringoscil.
Channel adjust = 6 & 2
G-Mode, channel adjust = 6 & 2
Use LVPECL inpus
EFlagHiZN, Quiet mode, Mtimer on Start
StartOff1 = 100ns
Power-on ECL
Res = 27.4348ps, Mtimer = 1 µs
Any error -> ErrFlag
Mtimer -> Interrupt flag
_oupd( 4,0x6400100);
// Master reset
StopDis1
StopDis2
StopDis3
StopDis4
// Enable inputs
=
=
=
=
Low;
Low;
Low;
Low;
do
{
while(IrFlag=Low);
// Check interrupt flag
Alutrigger = High;
Alutrigger = Low;
// Trigger Alu
wait(100ns);
// Time to calculate first hit
while(EF1=Low)
{
data = _inpd(8);
Time = (data & 0x7FFFFF);
Printf(Time);
}
_oupd( 4,0x6400100);
} while(!quit)
// Check empty flag
// Read IFIFO1
// Get time Stop-Start
// Master reset
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5 M-Mode
5.1 Block diagram M-Mode
TStart1
DStart
(LVTTL) (LVPECL)
DStop1
(LVPECL)
TStop1
(LVTTL)
500 kHz max.
TStop2
(LVTTL)
500 kHz max.
DStop2
(LVPECL)
500 kHz max.
Input Logic
high
res
Start
FIFO
Start
FIFO1
high
res
high
res
Measurement Core
Hit
Hit
Hit
FIFO3 FIFO4 FIFO5
Start
FIFO2
Stop1a
value
Start
select
Logic
Stop1b
value
Hit
FIFO6
Hit
FIFO7
Hit
FIFO8
Stop2a
value
Stop2b
value
Stop2c
value
Stop1c
value
40 MHz
28
Read/Write
logic
Interface Fifo2
28 x 256
40 MHz
max.
40 MHz
max.
28
Data multiplexer
40 MHz
max.
4
WRN RDN CSN
40 MHz
Interface Fifo1
28 x 256
Configuration
registers
32 cells
Address
LF1 EF1
28 or 2x16
Data bus
EF2 LF2
Figure 33
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5.2 Input Circuitry M-Mode
Chan0
Rise
DStart
+
DStartN
DStart
-
TStart
START: FallEn
Disable[0]
Res
RiseEn0
0
1
≠ RiseEn!
Chan1
StartdDis
(pin)
S
Fall
TStart
Disable[1]
Chan2
Res
Disable[2]
FallEn0
StartdDis
(pin)
Chan3
RiseEn1
Chan4
Rise
DStop1
+
DStop1N
-
DStop1
TStop1
0
1
Disable[3]
Res
StopDis1
(pin)
S
Fall
TStop1
Disable[4]
Chan5
Res
Disable[5]
FallEn1
StopDis2
(pin)
Chan6
Rise
DStop2
+
DStop2N
-
DStop2
TStop2
Disable[6]
Res
RiseEn2
0
Chan7
StopDis3
(pin)
1 S
Fall
TStop2
Disable[7]
Chan8
Res
FallEn2
Disable[8]
StopDis4
(pin)
external pull-down resistors:
GTest
LVPECL
+
51R
51R
LV-TTL
51K
Figure 34
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5.3 M-Mode Basics
Maximum resolution:
Standard deviation down to 10 ps,
Peak-peak down to 70 ps
2 stop-channels referring to 1 start channel
1 Hit per channel
0 ns to 40 µs measuring range
Quiet mode
LVPECL inputs
Max. 500 kHz continuous rate per channel
Max. 1 MHz continuous rate per chip
FallEn0..2. A zero in both bits for one channel at the
same time disables the channel.
All inputs can be disabled by hardware, the stop inputs
separately for rising and falling edges (pin ‘StopDis1’
disables inputs DStop1,rising edge etc.).
They also can be disabled by software setting the ‘Disable’ in register 2. The ‘Disable’ bits have to be set in
triples, e.g Disable3, Disable4 and Disable5 to disable
DStop1.
tph
StopDisStart & StartDisStop
By default the Start and Stop inputs of the TDC-GPX
are open immediately after a reset.
Start
Stop
tss
tph
Alutrigger
The consequence for the Stop channels is that even
hits coming before a Start pulse will be measured. The
bit StopDisStart in register 5 disables the Stop channels until there is a Start pulse. A consequence is that
there is a minimum delay of 7 ns after the Start before
hits are accepted on the Stop channels.
tsa
tva
EF
Figure 35: Measurement timings
Parameter
t ph
t pl
t ss
t sa
t va
Time (Condition)
1.5 ns (min.)
3.2 ns (min.)
0 ns (min)
40 µs (max.)
400 ns (min)
1 µs (max.)
Description
Minimum pulse width
Minimum pulse width
Start to Stop
With single-start only the first Start pulse is used for
the measurement. In case more than one Start pulse
is expected this might cause an overflow of the Hit
FIFO of the Start channel. This will produce garbage
data. There we recommend setting the StartDisStart
bit in register 5. A ‘1’ disables the Start channel after
the first Start pulse.
Stop to ALU trigger
ALU trigger to data valid
Start-Offset
For several reasons a programmable offset is added
to the stop time. One reason is to compensate for
different internal delays from the input buffers to the
TDC unit in the Start and Stop paths. It allows handling
Start-Stop intervals down to 0 and even less. The offset value ‘StartOff1’ is set in register 5 in multiples of
the I-Mode BIN and 18 bits wide. Internally the start
offset is added to the time measurement result and
has to be subtracted from the value read from the
TDC.
M-Mode is activated by setting MSet = 31 (Reg3) and
Mon = 1 (Reg4).
The M-Mode for maximum resolution is basically an
extension of the R-Mode. The block diagram and the
input circuitry are the same as in R-Mode. Also the
furhter settings are the same as in R-Mode.
In this mode the TDC-GPX accepts only one Stop per
channel. It is necessary to select M-Mode in combination with quiet mode.
Input circuitry
In M-Mode the TDC-GPX has differential low-voltage
PECL input buffers. The power for the differential inputs has to be switched on separately by setting register 6, PowerOnECL = ‘1’.
Adjusting the Start-Offset
The Start-Offset register of the TDC-GPX allows the
compensation for the offset due to the different internal delays. It allows to do measurements down to 0 ns
time intervals between Start and Stop. The correct
setting should be done by experiment.
The detailed input structure is shown in Figure 29.
Each input can be set to be sensitive to rising or falling
edge. This is done in register0, RiseEn0..2 and
Procedure for single start applications:
1. Set StartOff1 = 0
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2. Apply Start and Stop signals with a short delay (e.g.
12ns)
3. Step down the interval and look at the output data.
They are getting smaller and smaller until you pass
the internal Start time stamp. The output data then
jumps to a very high value.
4. Take the time interval t cross (from your generator)
where this happens
5. Calculate StartOff1 = t cross / BIN and write this
value into register 5, StartOff1. In case you expect
negative values add an additional amount X to StartOff1 and substract this value later on from your
output data
externally by a rising slope at pin ALUTRIGGER or by
software setting a dedicated ALU-Trigger Bit.
The time needed from the start of the post-processing
until first data is available in the interface FIFO is typ.
900 ns.
5.4 Data structure and readout
The output results are integers with a LSB width defined by the setting of the resolution adjust unit, divided by MSet.
BIN =
Internal Data Processing
The raw values of the stop events are stored in the Hit
FIFOs.
Tref × 2refclkdiv 1
1
× ×
216 × hsdiv
3 MSet + 1
Bit 27 … 23
Not used
The following pipelined post-processing unit is responsible for compression, Start selection and correct
Stop-Start subtraction. Subsequently a collection unit
transfers the data to the Interface FIFOs. Each channel
has its own interface FIFO. The maximum rate for
transfer into the Interface FIFO is 40 MHz.
Bit 22...0
Edge-to-Start result of the addressed combined channel
The data can be read from address 8 for interface
FIFO1 and from address 9 for interface FIFO2.
5.5 Reset
There are 3 ways of resetting the device:
Power-up reset: a low signal at pin PURESN
resets the whole chip.
Master-Reset: this command resets everything
except the configuration registers. It can be done
by software writing to register 4. In non-quiet
mode MasterAluTrig in register 5 can be set to
‘1’. Then this command can be done also by a
HIGH at the Alutrigger input pin. In quiet mode
MasterOenTrig in register 5 can be set to ‘1’.
Then this command can be done also by a LOW at
the OEN input pin (only with OEN off).
Partial-Reset: this command resets everything
except the configuration registers and the Interface FIFOs. It can be done by software writing to
register 4. In non-quiet mode Partial-AluTrig in
register 5 can be set to ‘1’. Then this command
can be done also by a HIGH at the Alutrigger input pin. In quiet mode PartialOenTrig in register 5
can be set to ‘1’. Then this command can be done
also by a LOW at the OEN input pin (only with OEN
off).
Finally a data multiplexer adds data from both Interface FIFOs to the data bus. The data bus is 28 Bits
wide and capable of 40 MHz transfer rate. The data
bus can be switched to 16 Bit width writing
0x0000010 into address 14. A LOW at pin ‘Output
enable’ forces the bidirectional bus drivers to permanent output state. This is helpful for fast data read out
routines.
Each Interface FIFO has an empty flag (EF) and a loadlevel flag (LF). All flags are HIGH active. At low data
rates it is recommended to check the EF to see
whether there are data available for read out. It is not
allowed to read from an empty Interface FIFO. The LF
is helpful at high data rates. The load level threshold
can be set in ‘Fill’ in register 6 and is the same for
both FIFOs. As soon as the set number of data is available this can be read from the FIFO as a block without
the need of checking the EF.
Note: the load-level flags are not synchronized. The
load-level flag for a FIFO is valid only if it is not read
from this FIFO. Otherwise there might be spikes.
After a Power-on reset or a Master reset it takes 40
ns before the Start and Stop inputs accept data.
After a Partial reset it takes 75 ns before the Start
and Stop inputs accept data.
Quiet Mode
In M-Mode it is mandatory to use the Quiet mode.
In Quiet Mode the post-processing and calculation
does not start automatically after each single event,
but after a dedicated trigger. The trigger can be given
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5.6 MTimer
Derating by
Voltage
Temperature
There is an internal timer available for internal use.
The main application will be setting a dedicated time
interval between 25ns and 204.7 µs after which the
interrupt flag is set. The period is set in ‘MTimer’,
register 7, in multiples of Tref. The maximum delay is
8191 * Tref = 204.7 µs. The timer can be started by
a Stop and/or Start signal. This is set in ‘MTimerStart’
and ‘MTimerStop’, register 4. Setting Bit ‘TimerFlag’,
register 12, the interrupt flag is set when the timer
stops.
Process
Minimal
0.91 at 3.6V
0.889 at –
40°C
0.74
Maximal
1.2 at 2.85V
1.17 at
+125°C
1.31
With the stabilization of the resolution by the resolution adjust mode, the voltage of the core decreases
with decreasing temperature, and increases with increasing temperature. The setting should be done in a
way that at maximum operating temperature the
maximum core voltage is reached, and that minimum
core voltage is reached at minimum operating temperature. With this method you get two limits:
5.7 Interrupt Flag
The user can select on which event(s) the interrupt
flag is set.
The selection is done in register 12, Bits 13 to 25, by
unmasking the dedicated bits. They are combined by
an Or-Gate to the interrupt flag.
Selectable events are
Hit FIFOs 1, 2 …or/and 8 are full
Interface FIFOs 1 or/and 2 are full
PLL not locked
All Hit FIFOs empty
End of Mtimer
Best case process, deepest temperature, lowest voltage: 0.74 x 0.889 x 1.2 = 0.789
Worst case process, highest temperature, highest
voltage: 1.31 x 1.17 x 0.91 = 1.394
The BIN size is calculated as BIN R-Mode /MSet. The
standard deviation in M-Mode is basically limited by the
noise of the measuring unit and has been measured
with 10 ps + 8 ps * ∆t/µs.. The BIN size has no real
influence on this.
5.8 Error Flag
The user can select on which event(s) the error flag is
set.
The selection is done in register 11, Bits 16 to 26, by
unmasking the dedicated bits. They are combined by
an Or-Gate to the error flag.
Selectable events are
Hit FIFOs 1, 2 …or/and 8 are full
Interface FIFOs 1, 2 …or/and 8 are full
PLL not locked
The pulse width limit is minimum 1.5 ns, limited by the
input buffers.
The measurement range depends on the M-Mode bin
size and the coarse counter. Its typical value is:
1
Range = 2 23 × BINR − Mode ×
≈ 7µs(MSet = 31)
MSet + 1
INL
As a speciality of M-Mode the integral non-linearity
shows a deviation of the measured to the real time
interval in the near range. The width and height of the
non-linear range depends linearily on the MSet value.
5.9 Testinputs
For test purpose a set of three TTL inputs can be multiplexed to the measuring circuit by setting Bit Gtest in
register 3. The test inputs have the same functionality
as the measure inputs, but can only handle a minimum
pulse width of 5ns and a minimum edge-to-edge distance of 20ns.
5.10 M-Mode Timing &
Resolution
TDC-GPX is working in resolution adjust mode.
The intrinsic delay parameters vary with voltage, temperature and process tolerance. The resolution adjust
unit uses the voltage depency to compensate for temperature and process variations. The following table
lists the derating factors.
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5.11 Measurement Flow
In the following we shows a typical example of register settings and measurement flow in M-Mode.
Task: Typical application laserscanner.
Given a Start signal with 10 kHz rate. To each Start there is one Stop event on channel 1. The time between Stop
and Start shall be measured with high resolution, using the LVPECL inputs.
Choice: M-Mode, triggering the external laser,
//****** M-Mode, Stop against Start **********
PuResN=Low;
PuResN=High;
// Power-up reset
StopDis1
StopDis2
StopDis3
StopDis4
// Disable inputs
=
=
=
=
High;
High;
High;
High;
_oupd( 0,0x000008B);
_oupd( 1,0x0620620);
_oupd( 2,0x0062004);
_oupd( 3,0x000001E);
_oupd( 4,0x6000300);
_oupd( 5,0x0000000);
_oupd( 6,0x8000000);
_oupd( 7,0x0001FB4);
_oupd(11,0x7FF0000);
_oupd(12,0x2000000);
_oupd(14,0x0000000);
//
//
//
//
//
//
//
//
//
//
//
write configuration registers:
Rising edges, Start ringoscil.
Channel adjust = 6 & 2
R-Mode, channel adjust = 6 & 2
Use LVPECL inputs, MSet = 30
EFlagHiZN, Quiet Mode, M-Mode
Switch on ECL power
Bin = 0.8850ps (resolution ~ 10ps rms)
Any error -> ErrFlag
MTimer to IrFlag
_oupd( 4,0x2400001);
// Master reset
StopDis1
StopDis2
StopDis3
StopDis4
// Enable inputs
=
=
=
=
Low;
Low;
Low;
Low;
do
{
TriggerLaser;
// send trigger to the laser
while(!(_inpw(8) & 0x0020));
_outpd(4,0x7000300);
while((_inpd(8) & 0x0800)>0);
// Check Interrupt flag
// Reg4, ALU trigger
// Check Empty flag
FIFO0 = _inpd(8) & 0x7FFFFF;
printf("%5.3fns\n",float(FIFO1)*27.4348/1000/31);
_outpd(4,0x6400300);
} while(!quit)
// Read FIFO0
// Display time in ns
// Master reset
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6 Bug Report
6.1 Data Bus: 16 Bit Mode
Subject:
CSN in 16-Bit mode
When working with a 16 Bit databus, register 14 Bit 4 = 1, there is a malfunction of CSN.
Relevance:
Systems with not only a TDC-GPX at the 16 Bit bus but other chips o TDCs connected too.
Description:
In 16 Bit mode we have two internal latches that collect the data for the high-word and the low-word and put them
together to one 28 bit value. Strobes on RDN or WRN toggle between the two latches. This should be deactived
when CSN is high but it is not.
As long as CSN is high no data are written in the TDC-GPX but the latches are toggled. If CSN goes low and the
pointer is already on the high-word latch then the data with the next RDN/WRN strobe will be wrong.
Workaround:
1. By Software
The following sequence at the beginning of any communication with the TDC-GPX will guarantee that the pointer
shows to the low-word latch:
Write
Write
Write
Write
Adr
Adr
Adr
Adr
=
=
=
=
15,
14,
14,
14,
Val
Val
Val
Val
=
=
=
=
0x00 (empty address)
0x00
0x00 now the 16 Bit mode is definitely off, latch pointers are correct
0x10 Switch on 16 Bit mode again
2. By Hardware
Disable the RDN/WRN lines with CSN = High
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TDC-GPX
7 Last Changes
12
31
02
18
th
st
nd
th
April 2006
May 2006
Nov 2006
Jan 2008
Correction in sections 3.5, 4.5, 5.5.
New section 1.6.3.
4.12 offset calculation
OEN not used -> Vddo
Contact
Headquarter
Germany
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[email protected]
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European Distributors
Belgium
(Vlaanderen)
CenS (Micro) Electronics BV.
PO Box 2331/ NL 7332 EA Apeldoorn
Lamfe Amerikaweg 67
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Fax: +31 (0) 55 3560211
[email protected]
www.censelect.nl
France
microel (CATS S.A.)
Great Britain
2001 Electronic Components Ltd.
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19, avenue de Norvège
Z.A. de Courtaboeuf - BP 3
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Italy
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Netherlands
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Lamfe Amerikaweg 67
NL 7332 BP Apeldoorn
Tel. : +33 1 69 07 08 24
Fax : +33 1 69 07 17 23
[email protected]
www.microel.fr
Tel. +44 1438 74 2001
Fax +44 1438 74 2001
[email protected]
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Tel: +39 02 485 611 1
Fax: +39 02 485 611 242
email: [email protected]
www.deltacomp.it
Tel: +31 (0) 55 3558611
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[email protected]
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Switzerland
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Russia
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Moscow, 129626, Russia
Tel.: +41-1-308 6666
Fax: +41-1-308 6655
email: [email protected]
www.ccontrols.ch
Tel\Fax: +7-495-987-42-10,
Tel: +7-095-107-19-62
Mobile +7-916-993-67-57
Email: [email protected]
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American Distributors
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of America
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Tel: 513-583-9491
Fax: 513-583-9476
email: [email protected]
www.acam-usa.com
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Asian Distributors
India
Brilliant Electro-Sys. Pvt. Ltd.
4, Chiplunker Building, 4 Tara Temple Lane,
Lamington Road,
Bombay – 400 007
Israel
ArazimLtd.
4 Hamelacha St. Lod
P.O.Box 4011
Lod 71110
Japan
DMD–Daiei Musen Denki Co., Ltd.
10-10, Sotokanda, 3-Chome, Chiyoda-Ku
Tokyo 101-0021
P.R. China
Broadtechs Technology Co. Ltd.
Shanghai Office:
3C JinHuan Building, 489 Xiang Yang Road
South
Shanghai, 200031
South Korea
SamHwa Technology Co., Ltd.
#4 4F Kyungwon building, 416-6
Jakjeon-dong
GYEYANG-GU, INCHEON 407-060
Tel: +91 22 2387 5565
Fax: +91 22 2388 7063
www.brilliantelectronics.com
[email protected]
Tel: 972-8-9230555
Fax: 972-8-9230044
email: [email protected]
www.arazim.co.il
Tel: +81 (0)3 3255 0931
Fax: +81 (0)3 3255 9869
[email protected]
www.daiei-dmd.co.jp
Tel.: +86-21-54654391
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Email: [email protected]
www.acam-china.com
Tel: +82 32 556 5410
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www.isamhwa.com
[email protected]
The information provided herein is believed to be reliable; however, acam assumes no responsibility for inaccuracies or omissions. Acam assumes no responsibility for the use of this information, and all use of such information shall be entirely at the
user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the
circuits described herein are implied or granted to any third party. acam does not authorize or warrant any acam product for
use in life support devices and/or systems.
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