IDT7MB4048 512K x 8 CMOS STATIC RAM MODULE Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High-density 4-megabit (512K x 8) Static RAM module • Fast access time: 25ns (max.) Surface mounted plastic packages on a 32-pin, 600 mil FR-4 DIP substrate • Single 5V (±10%) power supply • Inputs/outputs directly TTL-compatible The IDT7MB4048 is a 4-megabit (512K x 8) Static RAM module constructed on a multilayer epoxy laminate (FR-4) substrate using four 1 megabit SRAMs and a decoder. The IDT7MB4048 is available with access times as fast as 25ns. The IDT7MB4048 is packaged in a 32-pin FR-4 DIP resulting in the JEDEC footprint in a package 1.6 inches long and 0.6 inches wide. All inputs and outputs of the IDT7MB4048 are TTL-compatible and operate from a single 5V supply. Fully asynchronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use. PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM A 18 A 16 A 14 A 12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 Vcc A 15 A 17 ADDRESS A 13 A8 A9 A 11 CS WE OE WE OE 19 512K x 8 RAM A 10 CS 8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O 2675 drw 02 2675 drw 01 DIP TOP VIEW PIN NAMES I/O0-7 Data Inputs/Outputs A0-18 Addresses CS WE OE Chip Select Write Enable Output Enable VCC Power GND Ground 2675 tbl 01 The IDT logo is a registered trademark of Integrated Device Technology Inc. COMMERCIAL TEMPERATURE RANGE DECEMBER 1995 ©1996 Integrated Device Technology, Inc. DSC-2675/6 7.11 1 IDT7MB4048 512K x 8 CMOS STATIC RAM MODULE ABSOLUTE MAXIMUM RATINGS(1) TRUTH TABLE Mode CS COMMERCIAL TEMPERATURE RANGE OE WE Output Power Symbol VTERM Terminal Voltage with Respect to GND TA Standby H X X High-Z Standby Read L L H DOUT Active Read L H H High-Z Active Write L X L DIN Active 2675 tbl 02 CAPACITANCE(1) (TA = +25°C, f = 1.0MHz) Symbol Parameter Conditions Commercial Unit –0.5 to +7.0 V Operating Temperature 0 to +70 °C TBIAS Temperature Under Bias –10 to +85 °C TSTG Storage Temperature –55 to +125 °C IOUT DC Output Current 50 mA Typ. Unit CIN Input Capacitance VIN = 0V 35 pF CIN(C) Input Capacitance (CS) VIN = 0V 8 pF COUT Output Capacitance VOUT = 0V 35 pF NOTE: 1. This parameter is guaranteed by design, but not tested. 2675 tbl 03 Rating NOTE: 2675 tbl 05 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS RECOMMENDED OPERATING Symbol Parameter Min. Typ. Max. Unit TEMPERATURE AND SUPPLY VOLTAGE VCC GND Supply Voltage 4.5 Supply Voltage 0 5 5.5 0 0 V Grade V VIH Input High Voltage 2.2 — 6 V VIL Input Low Voltage –0.5(1) — 0.8 V Commercial Ambient Temperature GND VCC 0°C to +70°C 0V 5V ± 10% 2675 tbl 06 NOTE: 1. VIL = –2.0V for pulse width less than 10ns. 2675 tbl 04 DC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, TA = 0°C to +70°C) 7MB4048SxxP Symbol Parameter Test Conditions Min. Max. Unit |ILI| Input Leakage VCC = Max., VIN = GND to VCC — 8 Output Leakage VCC = Max., CS = VIH, VOUT = GND to VCC µA |ILO| — 8 µA VOL Output Low Voltage VCC = Min., IOL = 8mA — 0.4 V VOH Output High Voltage VCC = Min., IOH = –1mA 2.4 — V ICC Dynamic Operating Current VCC = Max., CS ≤ VIL; f = fMAX, Outputs Open — 480 mA ISB Standby Supply Current (TTL Levels) — 250 mA — 170 mA ISB1 Full Standby Supply Current (CMOS Levels) CS ≥ VIH, VCC = Max., f = fMAX, Outputs Open CS ≥ VCC - 0.2V, VIN ≥ VCC - 0.2V or ≤ 0.2 2675 tbl 07 7.11 2 IDT7MB4048 512K x 8 CMOS STATIC RAM MODULE COMMERCIAL TEMPERATURE RANGE AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 & 2 2675 tbl 09 +5 V +5 V 480 Ω 480 Ω DATAOUT DATAOUT 255Ω 255Ω 30 pF* 5 pF* 2675 drw 05 2675 drw 04 Figure 2. Output Load (for tOLZ, tCHZ, tOHZ, tWHZ, tOW and tCLZ) Figure 1. Output Load AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, TA = 0°C to +70°C) 7MB4048 Symbol Read Cycle Parameter –25 –30 Min. Max. Min. Max. –35 Min. Max. Unit tRC Read Cycle Time 25 — 30 — 35 — ns tAA Address Access Time — 25 — 30 — 35 ns tACS Chip Select Access Time — 25 — 30 — 35 ns tOE Output Enable to Output Valid — 12 — 15 — 15 ns tOHZ(1) Output Disable to Output in High-Z — 12 — 12 — 15 ns tOLZ(1) Output Enable to Output in Low-Z 0 — 0 — 0 — ns tCLZ(1) Chip Select to Output in Low-Z 5 — 5 — 5 — ns tCHZ(1) Chip Deselect to Output in High-Z — 14 — 16 — 20 ns tOH Output Hold from Address Change 3 — 3 — 3 — ns tPU(1) Chip Select to Power-Up Time 0 — 0 — 0 — ns tPD(1) Chip Deselect to Power-Down Time — 25 — 30 — 35 ns — 35 — ns Write Cycle tWC Write Cycle Time 25 — 30 tWP Write Pulse Width 17 — 20 — 25 — ns tAS(2) Address Set-up Time 3 — 0 — 0 — ns tAW Address Valid to End-of-Write 20 — 25 — 30 — ns tCW Chip Select to End-of-Write 20 — 25 — 30 — ns tDW Data to Write Time Overlap 15 — 17 — 20 — ns tDH(2) Data Hold Time 0 — 0 — 0 — ns tWR(2) Write Recovery Time 0 — 0 — 0 — ns tWHZ(1) Write Enable to Output in High-Z — 15 — 15 — 15 ns tOW(1) 2 — 5 — 5 — ns Output Active from End-of-Write NOTES 1. This parameter is guaranteed by design, but not tested. 2. tAS=0ns for CS controlled write cycles. tDH, tWR= 3ns for CS controlled write cycles. 7.11 2675 tbl 10 3 IDT7MB4048 512K x 8 CMOS STATIC RAM MODULE COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 1(1) tRC ADDRESS tAA OE tOE CS tOLZ tOH (5) tACS tCLZ (5) tCHZ (5) tOHZ (5) DATAOUT 2675 drw 06 TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4) tRC ADDRESS tAA tOH tOH DATAOUT 2675 drw 07 TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4) CS tACS tCLZ (5) tCHZ (5) DATAOUT 2675 drw 08 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS = VIL. 3. Address valid prior to or coincident with CS transition LOW. 4. OE = VIL. 5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested. 7.11 4 IDT7MB4048 512K x 8 CMOS STATIC RAM MODULE COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 7) tWC ADDRESS OE tAW CS tWP tAS (7) tWR WE tWHZ tOHZ DATAOUT (6) tOHZ (6) tOW (6) (6) (4) (4) tDH tDW DATAIN DATA VALID 2675 drw 09 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 3, 5) tWC ADDRESS tAW CS tAS tCW tWR WE tDH tDW DATAIN DATA VALID 2675 drw 10 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested. 7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 7.11 5 IDT7MB4048 512K x 8 CMOS STATIC RAM MODULE COMMERCIAL TEMPERATURE RANGE PACKAGE DIMENSIONS 1.590 1.610 0.600 0.620 TOP VIEW SIDE VIEW 0.360 MAX. Pin 1 0.035 0.065 0.015 0.025 0.100 TYP. 0.590 0.620 0.007 0.013 0.120 0.175 BOTTOM VIEW 2675 drw 11 ORDERING INFORMATION(1) IDT XXXX Device Type A 999 A Power Speed Package A Process/ Temperature Range Blank Commercial (0°C to +70°C) P SOJs mounted on an FR-4 DIP 25 30 35 Speed in Nanoseconds S Standard Power 7MB4048 512K x 8 Static RAM Module (FR-4 substrate) 2675 drw 12 7.11 6