IDT IDT7MB4145S20Z

IDT7MP4045
IDT7MP4145
256K x 32
CMOS STATIC RAM MODULE
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 1 megabyte static RAM module
(IDT7MP4145 upgradeable to 4 megabyte, IDT7MP4120)
• Low profile 64 pin ZIP (Zig-zag In-line vertical Package)
or 64 pin SIMM (Single In-line Memory Module) for
IDT7MP4045 and 72 pin SIMM (Single In-line Memory
Module) for IDT7MP4145
The IDT7MP4045/4145 is a 256K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate using 8
256K x 4 static RAMs in plastic SOJ packages. Availability of
four chip select lines (one for each group of two RAMs)
provides byte access. The IDT7MP4045 is available with
access time as fast as 10ns with minimal power consumption.
The IDT7MP4045 is packaged in a 64 pin FR-4 ZIP (Zigzag In-line vertical Package)or a 64 pin SIMM (Single In-line
Memory Module) where as the 7MP4145 is packaged in a 72
pin SIMM (Single In-line Memory Module). The 4045 ZIP
configuration allows 64 pins to be placed on a package 3.65
inches long and 0.365 inches wide. The 7MP4045 ZIP is only
0.585 inches high, this low profile package is ideal for systems
with minimum board spacing while the SIMM configuration
allows use of edge mounted sockets to secure the module.
All inputs and outputs of the IDT7MP4045/4145 are TTLcompatible and operate from a single 5V supply. Full asynchronous circuitry requires no clocks or refresh for operation
and provides equal access and cycle times for ease of use.
Identification pins are provided for applications in which
different density versions of the module are used. In this way,
the target system can read the respective levels of PD pins to
determine a 256K depth.
The contact pins are plated with 100 micro-inches of nickel
covered by 30 micro-inches minimum of selective gold.
• Very fast access time: 15ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maximum noise immunity
• Inputs/outputs directly TTL-compatible
PIN CONFIGURATION – 7MP4045(1)
1
PD 0
I/O0
I/O1
I/O2
I/O3
VCC
A7
A8
A9
I/O4
I/O5
I/O6
I/O7
WE
A14
CS1
CS3
A16
GND
I/O16
I/O17
I/O18
I/O19
A10
A11
A12
A13
I/O20
I/O21
I/O22
I/O23
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 ZIP,
34
SIMM
TOP VIEW 33
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
GND
PD1
I/O8
I/O9
I/O10
I/O11
A0
A1
A2
I/O12
I/O13
I/O14
I/O15
GND
A15
PD 0 – GND
PD 1 – GND
FUNCTIONAL BLOCK DIAGRAM
CS1 CS2 CS3 CS4
CS2
ADDRESS
18
2
WE
OE
CS4
A17
OE
I/O24
I/O25
I/O26
I/O27
A3
A4
A5
VCC
A6
I/O28
I/O29
I/O30
I/O31
PD
256K x 32
RAM
8
8
8
8
I/O 0-31
2703 drw 02
PIN NAMES
I/O0–31
Data Inputs/Outputs
A0–17
Addresses
CS1–4
WE
OE
PD0–1
2703 drw 01
NOTE:
1. Pins 2 and 3 (PD0 and PD1) are read by the user to determine the density
of the module. If PD0 reads GND and PD1 reads GND, then the module
has a 256K depth.
Chip Selects
Write Enable
Output Enable
Depth Identification
VCC
Power
GND
Ground
NC
No Connect
2703 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
SEPTEMBER 1996
1996 Integrated Device Technology, Inc.
DSC-2703/7
15.2
1
IDT7MP4045/7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION – 7MP4145(1)
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
Conditions
Max.
Unit
Parameter
Min.
Typ.
Max.
Unit
NC
PD3
PD0
I/O0
I/O1
I/O2
I/O3
VCC
A7
A8
A9
I/O4
I/O5
I/O6
I/O7
VCC
Supply Voltage
4.5
5.0
5.5
V
A14
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
—
6.0
V
—
0.8
V
CIN(C)
Input Capacitance
(CS)
V(IN) = 0V
20
pF
CIN(A)
Input Capacitance
(Address & Control)
V(IN) = 0V
70
pF
CI/O
I/O Capacitance
V(OUT) = 0V
12
pF
NOTE:
1. This parameter is guaranteed by design but not tested.
2703 tbl 02
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
VIL
Input Low Voltage
2.2
–0.5
(1)
NOTE:
1. VIL (min) = –1.5V for pulse width less than 10ns.
WE
CS1
CS3
A16
GND
I/O16
I/O17
I/O18
I/O19
A10
A11
A12
A13
I/O20
I/O21
I/O22
I/O23
GND
NC
NC
2703 tbl 03
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
Commercial
0°C to +70°C
0V
VCC
5.0V ± 10%
2703 tbl 04
TRUTH TABLE
Mode
Standby
CS
OE
WE
Output
Power
H
X
X
High-Z
Standby
Read
L
L
H
DATAOUT
Active
Write
L
X
L
DATAIN
Active
Read
L
H
H
High-Z
Active
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
NC
PD2
GND
PD1
I/O8
I/O9
I/O10
I/O11
A0
A1
A2
I/O12
I/O13
I/O14
I/O15
GND
A15
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
CS4
PD0 - GND
PD1 - GND
PD2 - OPEN
PD3 - OPEN
CS2
A17
OE
I/O24
I/O25
I/O26
I/O27
A3
A4
A5
VCC
A6
I/O28
I/O29
I/O30
I/O31
NC
NC
2703 drw 15
SIMM
TOP VIEW
2703 tbl 05
NOTE:
1. Pins 3,4,6,and 7 (PD0-3) are read by the user to determine the density of
the module. If PD0, PD1 read GND and PD2, PD3 read OPEN, then the
module has a 256K depth.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Value
Unit
–0.5 to +7.0
V
0 to +70
°C
VTERM
Terminal Voltage with
Respect to GND
TA
Operating Temperature
TBIAS
Temperature Under Bias
–10 to +85
°C
TSTG
Storage Temperature
–55 to +125
°C
IOUT
DC Output Current
50
mA
NOTE:
2703 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
15.2
2
IDT7MP4045/7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ±10%, TA = 0°C to +70°C)
Symbol
Min.
Max.
Unit
|ILI|
Input Leakage
(Address and Control)
Parameter
VCC = Max.; VIN = GND to VCC
Test Conditions
—
80
µA
|ILI|
Input Leakage (Data)
VCC = Max.; VIN = GND to VCC
—
10
µA
|ILO|
Output Leakage
VCC = Max.; CS = VIH, VOUT = GND to VCC
—
10
µA
VOL
Output LOW
VCC = Min., IOL = 8mA
—
0.4
V
VOH
Output HIGH
VCC = Min., IOH = –4mA
2.4
—
V
2703 tbl 07
Symbol
Parameter
Test Conditions
ICC
Dynamic Operating
Current
f = fMAX; CS = VIL
VCC = Max.; Output Open
ISB
Standby Supply
Current
CS ≥ VIH, VCC = Max.
Outputs Open, f = fMAX
ISB1
Full Standby
Supply Current
CS ≥ VCC – 0.2V; f = 0
VIN > VCC – 0.2V or < 0.2V
Max.
Unit
1360
mA
480
mA
120
mA
2703 tbl
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1-4
2703 tbl 09
+5 V
+5 V
480 Ω
480 Ω
DATAOUT
DATAOUT
255Ω
*Includes scope and jig.
255Ω
30 pF*
2703 drw 03
Figure 1. Output Load
5 pF*
2703 drw 04
Figure 2. Output Load
(for tOLZ,tOHZ, tCHZ, tCLZ, tWHZ, tOW)
15.2
3
IDT7MP4045/7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±10%, TA = 0°C to +70°C)
’4045SxxZ, ’4045/4145SxxM
–15
Symbol
Parameter
–20
Min.
Max.
Min.
Max.
Unit
15
—
20
—
ns
Read Cycle
tRC
Read Cycle Time
tAA
Address Access Time
—
15
—
20
ns
tACS
Chip Select Access Time
—
15
—
20
ns
tCLZ(1)
Chip Select to Output in Low-Z
3
—
5
—
ns
tOE
Output Enable to Output Valid
—
8
—
10
ns
tOLZ(1)
Output Enable to Output in Low-Z
0
—
0
—
ns
tCHZ(1)
Chip Deselect to Output in High-Z
—
8
—
10
ns
Output Disable to Output in High-Z
—
8
—
10
ns
Output Hold from Address Change
3
—
3
—
ns
tPU
(1)
Chip Select to Power-Up Time
0
—
0
—
ns
tPD
(1)
Chip Deselect to Power-Down Time
—
15
—
20
ns
tOHZ
(1)
tOH
Write Cycle
tWC
Write Cycle Time
15
—
20
—
ns
tCW
Chip Select to End-of-Write
12
—
15
—
ns
tAW
Address Valid to End-of-Write
12
—
15
—
ns
tAS
Address Set-up Time
0
—
0
—
ns
tWP
Write Pulse Width
12
—
15
—
ns
tWR
Write Recovery Time
0
—
0
—
ns
tWHZ(1)
Write Enable to Output in High-Z
—
8
—
13
ns
tDW
Data to Write Time Overlap
10
—
12
—
ns
tDH
Data Hold from Write Time
0
—
0
—
ns
tOW(1)
Output Active from End-of-Write
0
—
0
—
ns
NOTE:
1. This parameter is guaranteed by design but not tested.
2703 tbl 11
15.2
4
IDT7MP4045/7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
ADDRESS
tAA
OE
tOE
tOH
tOLZ (5)
CS
tACS
tCLZ (5)
tOHZ
(5)
tCHZ (5)
DATA OUT
2703 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
tRC
ADDRESS
tAA
tOH
DATAOUT
t OH
PREVIOUS DATA VALID
DATA VALID
2703 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS
tACS
tCLZ
(5)
tCHZ
(5)
DATAOUT
2703 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to or coincident with CS transition LOW.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
15.2
5
IDT7MP4045/7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (1, 2, 3, 7)
tWC
ADDRESS
OE
tAW
CS
tWP (7)
tAS
tWR
WE
tWHZ
tOHZ
DATA OUT
(6)
tOHZ
(6)
tOW(6)
(6)
(4)
(4)
tDW
DATA IN
tDH
DATA VALID
2703 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED) (1, 2, 3, 5)
tWC
ADDRESS
tAW
CS
tAS
tCW
tWR
WE
tDW
DATAIN
tDH
DATA VALID
2703 drw 11
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
15.2
6
IDT7MP4045/7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
7MP4045 ZIP VERSION
3.640
3.660
0.585
MAX.
PIN 1
0.365
MAX.
COMPONENT AREA
0.015
0.025
0.100
TYP.
0.250
TYP.
0.100
TYP.
0.050
TYP.
0.125
0.190
SIDE VIEW
FRONT VIEW
COMPONENT AREA
BACK VIEW
PIN 1
2703 drw 12
7MP4045 SIMM VERSION
3.840
3.860
0.365
MAX.
3.580
3.588
0.630
MAX.
0.390
0.410
COMPONENT AREA
0.240
0.260
0.250
TYP.
PIN 1
0.050
TYP.
0.045
0.055
SIDE VIEW
FRONT VIEW
COMPONENT AREA
BACK VIEW
PIN 1
2703 drw 13
15.2
7
IDT7MP4045/7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
7MP4145 SIMM VERSION
4.240
4.260
0.350
MAX.
3.974
3.994
0.640
0.660
0.390
0.410
0.240
0.260
0.250
TYP.
PIN 1
0.050
TYP.
0.045
0.055
SIDE VIEW
FRONT VIEW
0.070
0.090
BACK VIEW
PIN 1
2703 drw 16
ORDERING INFORMATION
IDT XXXXX
Device
Type
X
Power
X
X
X
Speed
Package
Process/
Temperature
Range
Blank
Z
M
15
20
S
Commercial (0°C to +70°C)
FR-4 ZIP (Zig-Zag In-line vertical Package,
7MP4045 only)
FR-4 SIMM (Single In-line Memory Module)
Speed in Nanoseconds
Standard Power
7MP4045
7MP4145
256K x 32 Static RAM Module
256K x 32 Static RAM Module
2703 drw 14
15.2
8