IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE Integrated Device Technology, Inc. FEATURES DESCRIPTION • High-density 4MB Static RAM module • Low profile 72-pin ZIP (Zig-zag In-line vertical Package) or 72-pin SIMM (Single In-line Memory Module) • Fast access time: 20ns (max.) • Surface mounted plastic components on an epoxy laminate (FR-4) substrate • Single 5V (±10%) power supply • Multiple GND pins and decoupling capacitors for maximum noise immunity • Inputs/outputs directly TTL-compatible The IDT7MP4120 is a 1M x 32 Static RAM module constructed on an epoxy laminate (FR-4) substrate using 8 1M x 4 Static RAMs in plastic packages. Availability of four chip select lines (one for each group of two RAMs) provides byte access. The IDT7MP4120 is available with access time as fast as 20ns with minimal power consumption. The IDT7MP4120 is packaged in a 72-pin FR-4 ZIP (Zigzag In-line vertical Package)or a 72-pin SIMM (Single In-line Memory Module). The ZIP configuration allows 72 pins to be placed on a package 4.05" long and 0.365" wide. At only 0.60" high, this low-profile package is ideal for systems with minimum board spacing while the SIMM configuration allows use of edge mounted sockets to secure the module. All inputs and outputs of the IDT7MP4120 are TTL-compatible and operate from a single 5V supply. Full asynchronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use. Four identification pins (PD0, PD1, PD2 and PD3) are provided for applications in which different density versions of the module are used. In this way, the target system can read the respective levels of PD0, PD1, PD2 and PD3 to determine a 1M depth. The contact pins are plated with 100 micro-inches of nickel covered by 30 micro-inches minimum of selective gold. PIN CONFIGURATION(1) NC PD3 PD0 I/O 0 I/O 1 I/O 2 I/O 3 VCC A7 A8 A9 I/O 4 I/O 5 I/O 6 I/O 7 WE A14 CS1 CS3 A16 GND I/O 16 I/O 17 I/O 18 I/O 19 A10 A11 A12 A13 I/O 20 I/O 21 I/O 22 I/O 23 GND A19 NC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 NC PD2 GND PD1 I/O 8 I/O 9 I/O 10 I/O 11 A0 A1 A2 I/O 12 I/O 13 I/O 14 I/O 15 GND A15 PD0 - GND PD1 - NC PD2 - GND PD3 - NC FUNCTIONAL BLOCK DIAGRAM CS1 CS2 CS3 CS4 CS2 CS4 A0 – A19 A17 OE 3 20 1M x 32 RAM WE OE I/O 24 I/O 25 I/O 26 I/O 27 A3 A4 A5 VCC A6 I/O 28 I/O 29 I/O 30 I/O 31 A18 NC PD0 – PD3 8 I/O0-7 8 8 8 I/O8-15 I/O16-23 I/O24-31 3019 drw 02 PIN NAMES 3019 drw 01 ZIP, SIMM TOP VIEW NOTE: 1. Pins 3, 4, 6 and 7 (PD0, PD1, PD2 and PD3 respectively) are read by the user to determine the density of the module. If PD0 reads GND, PD1 reads NC, PD2 reads GND and PD3 reads NC, then the module has a 1M depth. I/O0–I/O31 Data Inputs/Outputs A0–A19 Addresses CS1–CS4 WE OE Chip Selects Write Enable Output Enable PD0–PD3 Depth Identification VCC Power GND Ground NC No Connect 3019 tbl 01 The IDT logo is a registered trademark of Integrated Device Technology Inc. COMMERCIAL TEMPERATURE RANGE SEPTEMBER 1996 1996 Integrated Device Technology, Inc. DSC-3019/5 7.07 1 IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE COMMERCIAL TEMPERATURE RANGE CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol CI/O Parameter (1) Conditions Data I/O Capacitance TRUTH TABLE 15 pF Standby H X Read L L Write L X Read L H V(IN) = 0V Input Capacitance (Address) V(IN) = 0V 60 pF CIN2 Input Capacitance (WE, OE) V(IN) = 0V 75 pF V(IN) = 0V 20 pF Output Power X High-Z Standby H DATAOUT Active L DATAIN Active H High-Z Active 3019 tbl 05 Input Capacitance (CS) NOTE: 1. This parameter is guaranteed by design but not tested. 3019 tbl 02 ABSOLUTE MAXIMUM RATINGS(1) Symbol RECOMMENDED DC OPERATING CONDITIONS Symbol CS OE WE Unit CIN1 CIN3 Mode Max. Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage 2.2 — 6.0 V VIL Input Low Voltage –0.5(1) — 0.8 NOTE: 1. VIL (min) = –1.5V for pulse width less than 10ns. V 3019 tbl 03 Rating Value Unit –0.5 to +7.0 V 0 to +70 °C VTERM Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias –10 to +85 °C TSTG Storage Temperature –55 to +125 °C IOUT DC Output Current 50 mA NOTE: 3019 tbl 06 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Ambient Temperature GND Commercial 0°C to +70°C 0V VCC 5.0V ± 10% 3019 tbl 04 DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±10%, TA = 0°C to +70°C) Symbol Min. Max. Unit |ILI| Input Leakage (Address and Control) Parameter VCC = Max.; VIN = GND to VCC Test Conditions — 80 µA |ILI| Input Leakage (Data) VCC = Max.; VIN = GND to VCC — 10 |ILO| Output Leakage VCC = Max.; CS = VIH, VOUT = GND to VCC µA — 10 µA VOL Output LOW VCC = Min., IOL = 8mA — 0.4 V VOH Output HIGH VCC = Min., IOH = –4mA 2.4 — V 3019 tbl 07 Symbol Parameter Test Conditions 7MP4120 Max. Unit 1280 mA ICC Dynamic Operating Current f = fMAX; CS = VIL VCC = Max.; Output Open ISB Standby Supply Current CS ≥ VIH, VCC = Max. Outputs Open, f = fMAX 480 mA ISB1 Full Standby Supply Current CS ≥ VCC – 0.2V; f = 0 VIN > VCC – 0.2V or < 0.2V 120 mA 3019 tbl 08 7.07 2 IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE COMMERCIAL TEMPERATURE RANGE AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels Output Load 1.5V See Figures 1 and 2 2769 tbl 09 +5 V +5 V 480 Ω 480 Ω DATAOUT DATAOUT 255Ω 255Ω 30 pF* 5 pF* 3019 drw 04 3019 drw 03 *Includes scope and jig. Figure 1. Output Load Figure 2. Output Load (for tOLZ,tOHZ, tCHZ, tCLZ, tWHZ, tOW) 7.07 3 IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VCC = 5V ±10%, TA = 0°C to +70°C) 7MP4120SxxZ/M –20 Symbol Parameter Min. –25 Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 20 — 25 — ns tAA Address Access Time — 20 — 25 ns Chip Select Access Time — 20 — 25 ns tACS (1) tCLZ Chip Select to Output in Low-Z 3 — 3 — ns tOE Output Enable to Output Valid — 12 — 15 ns tOLZ(1) Output Enable to Output in Low-Z 0 — 0 — ns tCHZ(1) Chip Deselect to Output in High-Z — 10 — 12 ns tOHZ(1) Output Disable to Output in High-Z — 10 — 12 ns tOH Output Hold from Address Change 3 — 3 — ns tPU(1) Chip Select to Power-Up Time 0 — 0 — ns Chip Deselect to Power-Down Time — 20 — 25 ns 20 — 25 — ns tPD (1) Write Cycle tWC Write Cycle Time tCW Chip Select to End-of-Write 17 — 20 — ns tAW Address Valid to End-of-Write 17 — 20 — ns tAS Address Set-up Time 0 — 0 — ns tWP Write Pulse Width 15 — 20 — ns tWR Write Recovery Time 3 — 3 — ns tWHZ(1) Write Enable to Output in High-Z — 10 — 15 ns tDW Data to Write Time Overlap 12 — 15 — ns tDH Data Hold from Write Time 0 — 0 — ns tOW(1) Output Active from End-of-Write 0 — 0 — NOTE: 1. This parameter is guaranteed by design, but not tested. ns 3019 tbl 10 7.07 4 IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 1(1) tRC ADDRESS tAA OE tOE CS tOLZ tOH (5) tACS tCLZ (5) tOHZ (5) tCHZ (5) DATA OUT 3019 drw 05 TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4) tRC ADDRESS tAA tOH DATAOUT t OH PREVIOUS DATA VALID DATA VALID 3019 drw 06 TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4) CS tACS tCLZ (5) tCHZ (5) DATAOUT 3019 drw 07 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected. CS = VIL. 3. Address valid prior to or coincident with CS transition LOW. 4. OE = VIL. 5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested. 7.07 5 IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (1, 2, 3, 7) tWC ADDRESS OE tAW CS tWP (7) tAS tWR WE tWHZ tOHZ DATA OUT tOHZ (6) (6) (6) (6) tOW (4) (4) tDW DATA IN tDH DATA VALID 3019 drw 08 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED) (1, 2, 3, 5) tWC ADDRESS tAW CS tAS tCW tWR WE tDW DATAIN tDH DATA VALID 3019 drw 09 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested. 7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 7.07 6 IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE COMMERCIAL TEMPERATURE RANGE PACKAGE DIMENSIONS ZIP VERSION FRONT VIEW SIDE VIEW 3.940 3.960 0.365 MAX 0.580 0.600 PIN 1 0.100 TYP 0.015 0.025 0.250 TYP 0.100 TYP 0.125 0.175 0.025 TYP 0.025 TYP 0.050 TYP PIN 1 REAR VIEW 3019 drw 10 SIMM VERSION 4.240 4.260 0.350 MAX. 3.980 3.988 0.640 0.660 0.240 0.260 0.390 0.410 0.250 TYP. PIN 1 0.070 0.090 0.050 TYP. 0.045 0.055 SIDE VIEW FRONT VIEW BACK VIEW 7.07 PIN 1 3019 drw 11 7 IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX X X X X Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0°C to +70°C) Z M FR-4 ZIP (Zig-Zag In-line vertical Package) FR-4 SIMM (Single In-line Memory Module) 20 25 S Speed in Nanoseconds Standard Power 7MP4120 1M x 32 Static RAM Module 3019 drw 12 7.07 8