IDT IDT7017L15PF

PRELIMINARY
HIGH-SPEED
32K x 9 DUAL-PORT
STATIC RAM
Features
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT7017L
Active: 1W (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT7017 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
◆
◆
◆
◆
◆
◆
◆
◆
IDT7017L
than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/WL
CE0L
CE1L
OEL
R/WR
CE0R
CE1R
OE R
I/O
Control
I/O0-8L
I/O
Control
I/O0-8R
(1,2)
(1,2)
BUSYL
A14L
A0L
.
BUSYR
32Kx9
MEMORY
ARRAY
7017
Address
Decoder
15
CE0L
CE1L
OEL
R/W L
Address
Decoder
A14R
A0R
15
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
(2)
INTL
(1)
M/S
NOTES:
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
CE0R
CE1R
OER
R/WR
SEMR
(2)
INTR
5642 drw 01
NOVEMBER 2003
1
©2003 Integrated Device Technology, Inc.
DSC-5642/1
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
Description
The IDT7017 is a high-speed 32K x 9 Dual-Port Static RAM. The
IDT7017 is designed to be used as a stand-alone 288K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 18-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE0 and CE1) permit the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 1W of power.
The IDT7017 is packaged in a 100-pin Thin Quad Flatpack (TQFP).
Pin Configurations(1,2,3)
NC
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
NC
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
A6R
NC
NC
06/23/03
Index
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
NC
NC
Vcc
NC
NC
NC
NC
CE0L
CE1L
SEML
R/WL
OEL
GND
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
68
8
67
9
10
IDT7017PF
PN100-1(4)
11
66
65
64
12
100-Pin TQFP
Top View(5)
13
14
15
63
62
61
60
59
16
17
58
57
18
19
20
56
21
55
22
54
23
53
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
24
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
NC
NC
GND
NC
NC
NC
NC
CE0R
CE1R
SEMR
R/WR
OER
GND
GND
NC
GND
I/O 8L
I/O 7L
I/O 6L
I/O 5L
I/O 4L
I/O3L
I/O2L
GND
I/O1L
I/O 0L
Vcc
GND
I/O0R
I/O 1R
I/O2R
Vcc
I/O3R
I/O4R
I/O5R
I/O6R
I/O 7R
I/O 8R
NC
NC
5642 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
2
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A14L
A0R - A14R
Address
I/O0L - I/O8L
I/O0R - I/O8R
Data Input/Output
SEML
SEMR
Semaphore Enable
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
5642 tbl 01
Absolute Maximum Ratings(1)
Symbol
Commercial
& Industrial
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
Temperature
Under Bias
-55 to +125
TSTG
Storage
Temperature
-65 to +150
IOUT
DC Output Current
V TERM(2)
TBIAS
Rating
o
o
50
Recommended DC Operating
Conditions
Symbol
C
C
mA
5642 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
VCC
Supply Voltage
GND
Ground
Military
Commercial
Industrial
GND
Vcc
O
-55 C to +125 C
0V
5.0V + 10%
0 C to +70 C
0V
5.0V + 10%
-40 C to +85 C
0V
5.0V + 10%
O
O
O
O
O
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
Input High Voltage
2.2
____
VIL
Input Low Voltage
-0.5(1)
____
(2)
6.0
0.8
V
V
5642 tbl 04
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
Capacitance
(TA = +25°C, f = 1.0MHz)
Maximum Operating Temperature
and Supply Voltage(1)
Grade
Min.
VIH
Symbol
Ambient
Temperature(2)
Parameter
Parameter(1)
CIN
Input Capacitance
COUT
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
5642 tbl 05
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
5642 tbl 03
NOTES:
1. Industrial Temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter TA. This is the "instant on" case temperature.
3
6.42
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
Truth Table I: Chip Enable(1,2)
CE0
CE1
VIL
VIH
< 0.2V
>VCC -0.2V
Port Selected (CMOS Active)
VIH
X
Port Deselected (TTL Inactive)
X
VIL
Port Deselected (TTL Inactive)
>VCC -0.2V
X
Port Deselected (CMOS Inactive)
X
<0.2V
Port Deselected (CMOS Inactive)
CE
L
H
Mode
Port Selected (TTL Active)
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only.
2. 'H' = VIH and 'L' = VIL.
3. CMOS standby requires 'X' to be either < 0.2V or > V CC - 0.2V.
5642 tbl 06
Truth Table II: Non-Contention Read/Write Control
Inputs(1)
(2)
Outputs
Mode
R/W
OE
SEM
I/O0-8
H
X
X
H
High-Z
Deselected: Power-Down
L
L
X
H
DATAIN
Write to memory
L
H
L
H
DATAOUT
X
X
H
X
High-Z
CE
Read memory
Outputs Disabled
5642 drw 07
NOTES:
1. A0L – A14L ≠ A0R – A14R.
2. Refer to Chip Enable Truth Table.
Truth Table III: Semaphore Read/Write Control(1)
Inputs
(2)
Outputs
R/W
OE
SEM
I/O0-8
H
H
L
L
DATAOUT
Read Semaphore Flag Data Out
H
↑
X
L
DATAIN
Write I/O0 into Semaphore Flag
L
X
X
L
______
CE
Mode
Not Allowed
NOTES:
1. There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0-I/O8). These eight semaphore flags are addressed by A0-A2.
2. Refer to Chip Enable Truth Table.
4
5642 tbl 08
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%)
7017L
Symbol
Parameter
Min.
Max.
Unit
VCC = 5.5V, VIN = 0V to VCC
___
5
µA
Output Leakage Current
CE = VIH, VOUT = 0V to V CC
___
5
µA
VOL
Output Low Voltage
IOL = 4mA
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
V
|ILI|
(1)
Input Leakage Current
|ILO |
Test Conditions
5642 tbl 09
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
7017L15
Com'l Only
Typ.(1) Max
7017L20
Com'l
& Ind
Typ.(1) Max
Unit
mA
Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(2)
COM'L
L
220
340
200
300
IND
L
____
____
200
325
Standby Current
(Both Ports - TTL Level
Inputs)
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX(2)
COM'L
L
65
100
50
75
IND
L
____
____
50
90
Standby Current
(One Port - TTL Level
Inputs)
CE"A" = VIL and CE"B" = VIH(4)
Active Port Outputs Disabled,
f=fMAX(2), SEMR = SEML = VIH
COM'L
L
145
225
130
195
IND
L
____
____
130
210
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V, VIN > VCC - 0.2V
or VIN < 0.2V, f = 0(3)
SEMR = SEML > VCC - 0.2V
COM'L
L
0.2
3.0
0.2
3.0
IND
L
____
____
0.2
6.0
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(4),
SEMR = SEML > VCC - 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V, Active Port
Outputs Disabled, f = fMAX(2)
COM'L
L
135
220
120
190
IND
L
____
____
120
205
mA
mA
mA
mA
5642 tbl 10
NOTES:
1. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5
6.42
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
AC Test Conditions
5V
GND to 3.0V
Input Pulse Levels
893Ω
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
5V
DATAOUT
BUSY
INT
893Ω
DATAOUT
30pF
347Ω
347Ω
5pF*
Figures 1 and 2
Output Load
5642 tbl 11
5642 drw 03
5642 drw 04
Figure 2. Output Test Load
(for t LZ, tHZ, tWZ, tOW)
* Including scope and jig.
Figure 1. AC Output Test Load
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
CE(6)
tAOE
(4)
OE
R/W
tLZ
tOH
(1)
(4)
DATAOUT
VALID DATA
tHZ
(2)
BUSYOUT
tBDD
(3,4)
5642 drw 05
Timing of Power-Up Power-Down
CE
ICC
(6)
tPU
tPD
50%
50%
ISB
5642 drw 06
.
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD .
5. SEM = VIH.
6. Refer to Chip Enable Truth Table.
6
.
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
7017L15
Com'l Only
Symbol
Parameter
7017L20
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
ns
tAA
Address Access Time
____
15
____
20
ns
tACE
Chip Enable Access Time (4)
____
15
____
20
ns
tAOE
Output Enable Access Time
____
10
____
12
ns
tOH
Output Hold from Address Change
3
____
3
____
ns
tLZ
Output Low-Z Time(1,2)
3
____
3
____
ns
____
10
____
10
ns
0
____
0
____
ns
____
15
____
20
ns
10
____
ns
____
20
tHZ
Output High-Z Time
tPU
(1,2)
Chip Enable to Power Up Time
(2)
(2)
tPD
Chip Disable to Power Down Time
tSOP
Semaphore Flag Update Pulse (OE or SEM)
10
____
tSAA
Semaphore Address Access Time
____
15
ns
5642 tbl 12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
7017L15
Com'l Only
Symbol
Parameter
7017L20
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
15
____
20
____
ns
tEW
Chip Enable to End-of-Write
(3)
12
____
15
____
ns
tAW
Address Valid to End-of-Write
12
____
15
____
ns
0
____
0
____
ns
ns
WRITE CYCLE
tWC
Write Cycle Time
(3)
tAS
Address Set-up Time
tWP
Write Pulse Width
12
____
15
____
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
10
____
15
____
ns
____
10
____
10
ns
0
____
ns
10
ns
ns
tHZ
tDH
tWZ
tOW
Output High-Z Time
Data Hold Time
(1,2)
(4)
0
____
(1,2)
____
10
____
(1,2,4)
0
____
0
____
5
____
ns
5
____
ns
Write Enable to Output in High-Z
Output Active from End-of-Write
tSWRD
SEM Flag Write to Read Time
5
____
tSPS
SEM Flag Contention Window
5
____
5642 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
7
6.42
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
(9,10)
CE or SEM
tWP (2)
tAS(6)
tWR
(3)
R/W
tWZ
(7)
tOW
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
5642 drw 07
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
tAW
(9,10)
CE or SEM
tAS
(6)
(3)
tEW (2)
tWR
R/W
tDW
tDH
DATAIN
5642 drw 08
NOTES:
1. R/W or CE = V IH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = V IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW . If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP .
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Chip Enable Truth Table.
8
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
tAW
tOH
VALID ADDRESS
tWR
tACE
tEW
SEM
tSOP
tDW
DATAOUT
VALID(2)
DATAIN VALID
DATA0
tAS
tWP
tDH
R/W
tSWRD
OE
tAOE
tSOP
Write Cycle
Read Cycle
5642 drw 09
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O8) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
5642 drw 10
NOTES:
1. DOR = DOL = VIL, CEL = CE R = VIH (Refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
9
6.42
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
7017L15
Com'l Only
Symbol
Parameter
7017L20
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
15
____
20
ns
tBDA
BUSY Disable Time from Address Not Matched
____
15
____
20
ns
tBAC
BUSY Access Time from Chip Enable Low
____
15
____
20
ns
tBDC
BUSY Access Time from Chip Enable High
____
15
____
17
ns
tAPS
Arbitration Priority Set-up Time (2)
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
15
____
17
ns
12
____
15
____
ns
0
____
0
____
ns
12
____
15
____
ns
____
30
____
45
ns
____
25
____
30
ns
tWH
(5)
Write Hold After BUSY
BUSY TIMING (M/S=VIL)
tWB
tWH
BUSY Input to Write (4)
(5)
Write Hold After BUSY
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay (1)
Write Data Valid to Read Data Delay
(1)
5642 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
10
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDH
tDW
DATAIN "A"
VALID
tAPS
(1)
ADDR"B"
MATCH
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
tDDD
(3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL, refer to Chip Enable Truth Table.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), BUSY is an input. Then for this example BUSY "A" = VIH and BUSY "B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
tWB(3)
BUSY"B"
tWH (1)
R/W"B"
(2)
5642 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH.
3. tWB is only for the 'Slave' version.
11
6.42
5642 drw 11
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1,3)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS
(2)
CE"B"
tBAC
tBDC
BUSY"B"
5642 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1)
ADDR"A"
ADDRESS "N"
tAPS
ADDR"B"
(2)
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
5642 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Chip Enable Truth Table.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
7017L15
Com'l Only
Symbol
Parameter
7017L20
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tINS
Interrupt Set Time
____
15
____
20
ns
tINR
Interrupt Reset Time
____
15
____
20
ns
5642 tbl 15
12
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
Waveform of Interrupt Timing(1,5)
tWC
(2)
INTERRUPT SET ADDRESS
ADDR"A"
tAS
(3)
tWR
(4)
CE"A"
R/W"A"
tINS (3)
INT"B"
5642 drw 15
tRC
ADDR"B"
INTERRUPT CLEAR ADDRESS
(2)
tAS (3)
CE"B"
OE"B"
tINR (3)
INT"B"
5642 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
Truth Table IV — Interrupt Flag(1,4,5)
Left Port
R/WL
L
X
X
X
CEL
L
X
X
L
OEL
X
X
X
L
Right Port
A14L-A0L
7FFF
INTL
X
R/WR
X
CER
X
OER
X
A14R-A0R
X
INTR
Function
(2)
Set Right INTR Flag
(3)
Reset Right INTR Flag
L
X
X
X
L
L
7FFF
H
X
(3)
L
L
X
7FFE
X
Set Left INTL Flag
(2)
X
X
X
X
X
Reset Left INTL Flag
7FFE
L
H
5642 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = V IL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. Refer to Chip Enable Truth Table.
13
6.42
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
Truth Table V —Address BUSY
Arbitration(4)
Inputs
Outputs
CEL
CER
A0L-A14L
A 0R-A14R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write
Inhibit(3)
5642 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7017 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSY R = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D8 Left
D0 - D8 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7017.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O8). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT7017 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7017 has an automatic power down feature controlled
by CE. The CE0 and CE1 control the on-chip power down circuitry that
permits the respective port to go into a standby mode when not selected
(CE = HIGH). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
5642 tbl 18
(INTL) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as CER = R/WR = VIL per Truth Table
IV. The left port clears the interrupt through access of address location
7FFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right
port interrupt flag (INTR) is asserted when the left port writes to memory
location 7FFF (HEX) and to clear the interrupt flag (INTR), the right port
must read the memory location 7FFF. The message (9 bits) at 7FFE or
7FFF is user-defined since it is an addressable SRAM location. If the
interrupt function is not used, address locations 7FFE and 7FFF are not
used as mail boxes, but as part of the random access memory. Refer to
Table IV for the interrupt operation.
14
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT7017 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
can result in a glitched internal write inhibit signal and corrupted data
in the slave.
Semaphores
A15
CE0
MASTER
Dual Port RAM
CE0
SLAVE
Dual Port RAM
BUSYL
BUSYL
BUSYR
BUSYR
CE1
MASTER
Dual Port RAM
CE1
SLAVE
Dual Port RAM
BUSYL
BUSYL
BUSYR
BUSYR
,
5642 drw 17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7017 RAMs.
Width Expansion Busy Logic
Master/Slave Arrays
When expanding an IDT7017 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAMs array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use
the BUSY signal as a write inhibit signal. Thus on the IDT7017 RAM the
BUSY pin is an output if the part is used as a master (M/S pin = VIH), and
the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual
write pulse can be initiated with the R/W signal. Failure to observe this timing
The IDT7017 is an extremely fast Dual-Port 32K x 9 CMOS Static RAM
with an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table II where CE and SEM are both HIGH.
Systems which can best use the IDT7017 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit
from a performance increase offered by the IDT7017s hardware
semaphores, which provide a lockout mechanism without requiring
complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7017 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very highspeed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
15
6.42
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT7017 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a LOW input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, CE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none of
the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Table VI). That semaphore
can now only be modified by the side showing the zero. When a one is
written into the same location from the same side, the flag will be set to a
one for both sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Table
VI). As an example, assume a processor writes a zero to the left port at
a free semaphore location. On a subsequent read, the processor will verify
that it has written successfully to that location and will assume control over
the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
D
Q
SEMAPHORE
REQUEST FLIP FLOP
Q
D
WRITE
D0
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
5642 drw 18
Figure 4. IDT7017 Semaphore Logic
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one side
receives the token. If one side is earlier than the other in making the
request, the first side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be arbitrarily made
to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
16
Preliminary
Industrial and Commercial Temperature Ranges
IDT7017L
High-Speed 32K x 9 Dual-Port Static RAM
Ordering Information
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
100-pin TQFP (PN100-1)
15
20
Commercial Only
Commercial & Industrial
L
Low Power
7017
288K (32K x 9) Dual-Port RAM
Speed in
nanoseconds
5642 drw 19
Preliminary Datasheet:
"PRELIMINARY' datasheets contain descriptions for products that are in early release.
Datasheet Document History
11/06/03 :
Initial Data Sheet
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
17
6.42
for Tech Support:
831-754-4613
[email protected]