IDT74LVC138A 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH 5 VOLT TOLERANT I/O FEATURES: IDT74LVC138A DESCRIPTION: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • All inputs, outputs, and I/Os are 5V tolerant • Supports hot insertion • Available in QSOP, SOIC, SSOP, and TSSOP packages The LVC138A 3-line to 8-line decoder/demultiplexer is built using advanced dual metal CMOS technology. This device is designed for highperformance memory-decoding or data-routing applications requiring very short propagation delay times. In high performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one activehigh enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVC138A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 15 Y0 A 1 14 Y1 Select Inputs 2 13 B Y2 12 3 Y3 C 11 Data Outputs Y4 10 Y5 9 G1 Y6 6 7 Y7 Enable Inputs 4 G2A G2B 5 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE AUGUST 1999 1 ©1999 Integrated Device Technology, Inc. DSC-4722/1 IDT74LVC138A 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol A 1 16 VCC B 2 15 Y0 C 3 14 Y1 G2A 4 13 Y2 G2B 5 12 Y3 G1 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA IIK IOK Continuous Clamp Current, VI < 0 or VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. QSOP/ SOIC/ SSOP/ TSSOP TOP VIEW CAPACITANCE (TA = +25°C, F = 1.0MHz) PIN DESCRIPTION Pin Names G1 Input Enable Input Enables (Active LOW) G2A, G2B Yx Data Outputs A, B, C Parameter(1) Symbol Description Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 5.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF NOTE: 1. As applicable to the device type. Select Data Inputs FUNCTION TABLE(1) Enable Inputs Select Inputs Outputs G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X X H H H H H H H H X X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care 2 IDT74LVC138A 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V, VIN = GND or VCC — — 100 — — 10 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 500 µA IIH IIL NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Unit — V VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — 2.2 — VCC = 3V Output LOW Voltage Max. IOH = – 0.1mA VCC = 2.7V VOL Min. VCC – 0.2 VCC = 2.3V to 3.6V 2.4 — VCC = 3V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 3 IDT74LVC138A 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, TA = 25°C Symbol CPD VCC = 2.5V±0.2V VCC = 3.3V±0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz — 27 pF Parameter Power Dissipation Capacitance SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol Parameter VCC = 2.7V VCC = 3.3V ± 0.3V Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay A to B, C to Yx — — — 7.9 1 6.7 ns tPLH tPHL Propagation Delay G2A or G2B to Yx — — — 7.4 1 6.5 ns tPLH tPHL Propagation Delay G1 to Yx — — — 6.4 1 5.8 ns tSU Setup Time, at A, B, and C before G 2.4 — 2.5 — 2.3 — ns tH Hold Time, at A, B, and C after G 1.6 — 1.5 — 1.5 — ns Output Skew(2) — — — — — 1 ns tSK(o) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2 Skew between any two outputs of the same package and switching in the same direction. 4 IDT74LVC138A 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 2.5V±0.2V VLOAD VIH VCC(2)= 3.3V±0.3V & 2.7V Unit 2 x Vcc 6 V Vcc 2.7 V VT Vcc / 2 1.5 V VLZ 150 300 mV VHZ 150 300 mV CL 30 50 pF tPHL tPLH tPHL VIH VT 0V OPPOSITE PHASE INPUT TRANSITION LVC QUAD Link Propagation Delay VIN tPZL VOUT D.U.T. OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω RT CL LVC QUAD Link Test Circuit for All Outputs VIH VT 0V CONTROL INPUT GND 500Ω DISABLE ENABLE Open (1, 2) tPLH OUTPUT VLOAD VCC Pulse Generator VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. tPLZ VLOAD/2 VT VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V LVC QUAD Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. Enable and Disable Times SWITCH POSITION Test Switch Open Drain Disable Low Enable Low VLOAD Disable High Enable High GND All Other Tests Open INPUT OUTPUT 1 tPLH1 tSK (x) tPLH2 tH tREM SYNCHRONOUS CONTROL ASYNCHRONOUS CONTROL tSU tH LVC QUAD Link Set-up, Hold, and Release Times VOH VT VOL LOW-HIGH-LOW PULSE VOH VT VOL OUTPUT 2 tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V TIMING INPUT VIH VT 0V tPHL1 tSK (x) DATA INPUT VT tW HIGH-LOW-HIGH PULSE tPHL2 VT LVC QUAD Link tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Pulse Width LVC QUAD Link Output Skew - tSK(X) NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74LVC138A 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION XX IDT XXXX XX LVC Device Type Package Temp. Range Q DC PY PG CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 138A Quarter Size Outline Package Small Outline IC Shrink Small Outline Package Thin Shrink Small Outline Package 3-Line to 8-Line Decoder/Demultiplexer, ±24mA 74 -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459