IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS FEATURES: DESCRIPTION: • Input frequency: - For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, or 622.08MHz - For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz, 333.26MHz, or 666.52MHz - For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz, 312.5MHz, or 625MHz - For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz, 322.26MHz, or 644.53MHz • Output frequency range selection • 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT • Regenerated input clock on QREG • Lock indicator • Power-down mode • LVPECL or LVDS outputs • Two modes of output frequency range - Mode 0: QOUT range 155.5 - 166.6MHz. QREG is a regenerated version of the input clock. - Mode 1: QOUT range 622 - 666.5MHz. QREG is a regenerated version of the input clock frequency. • Hitless switchover • Differential LVPECL, LVDS, or single-ended LVTTL input interface • 2.375 - 3.465V core and I/O • Available in VFQFPN package The IDT5T929 generates a high precision FEC (Forward Error Correction) or non-FEC source clock for SONET/SDH systems as well as a source clock for Gigabit Ethernet systems. This device also has clock regeneration capability: it creates a "clean" version of the clock input by using the internal oscillator to square the input clock's rising and falling edges and remove jitter. In the event that the main clock input fails, the device automatically locks to a backup reference clock using a hitless switchover mechanism. This device detects loss of valid CLKIN and leaves the VCO of the PLL at the last valid frequency while an alternate input REFIN is selected. If CLKIN and REFIN are different frequencies, the multiplication factor will be adjusted to retain the same output frequency. The IDT5T929 can act as a translator from a differential LVPECL, LVDS, or single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T929-10 has LVDS outputs and the IDT5T929-30 has LVPECL outputs. The two modes of output frequency range are controlled by the SELmode. When SELmode is high or low, the QOUT is a multiplied version of the input clock while QREG is a regenerated version of the input clock. APPLICATIONS: • • • • • Terabit routers Gigabit ethernet systems SONET / SDH systems Digital cross connects Optical transceiver modules FUNCTIONAL BLOCK DIAGRAM CLKIN CLKIN QREG INPUT MUX DIVN PLL QREG QOUT DIVM REFIN REFIN QOUT CONTROL LOGIC LOCK, FREQ. DETECTOR PD SELMODE LOCK The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2004 1 c 2004 Integrated Device Technology, Inc. DSC 6400/13 IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE 28 27 26 25 24 23 Symbol VDD GND ABSOLUTE MAXIMUM RATINGS(1) QOUT QOUT GND VDD PD PIN CONFIGURATION 22 GND 1 21 VDD CLKIN 2 20 GND CLKIN 3 19 QREG GND 4 18 QREG REFIN 5 17 GND REFIN 6 16 VDD GND 7 15 LOCK GND Max Unit VDD Power Supply Voltage –0.5 to +4.1 V VI Input Voltage –0.5 to +4.1 V VO Output Voltage –0.5 to VDD+0.5 V TJ Junction Temperature 150 °C TSTG Storage Temperature –65 to +165 °C NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. 14 CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V) Parameter GND 13 VDD 12 VDD 11 SELMODE 10 TEST 9 TEST VDD 8 Description Typ. Max. Unit CIN Input Capacitance Description 2.5 3 pF COUT Output Capacitance — — pF NOTE: 1. Capacitance applies to all inputs except SELmode. VFQFPN TOP VIEW RECOMMENDED OPERATING RANGE Symbol Description Min. Typ. Max. Unit TA Ambient Operating Temperature –40 +25 +85 °C VDD Power Supply Voltage 2.375 — 3.465 V VT Termination Voltage (LVPECL) — VDD – 2 — V Termination Voltage (LVDS) — 1.2 — 2 IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE INPUT FREQUENCY RANGE(1) LOCK FREQUENCY DETECTOR The 5T929 will lock to, and track, a valid CLKIN signal; LOCK will be low when this has occurred. If CLKIN fails, the 5T929 PLL will smoothly switch to lock to REFIN without generating any glitches on the output. The fact that the PLL is locked to REFIN rather than CLKIN is indicated by a high state on LOCK. When a valid input is then applied to CLKIN, the 5T929 will smoothly switch back to locking on CLKIN, and LOCK will go low. LOCK will also switch to high should the frequency of CLKIN drift close to the limits of the VCO tuning range. 19.4MHz - 20.9MHz 38.8MHz - 41.7MHz 77.7MHz - 83.4MHz 155.5MHz - 167MHz 311MHz - 334MHz 622MHz - 667MHz NOTE: 1. The PLL will automatically detect the input frequency and adjust the multiply ratio to generate the appropriate output frequency. OUTPUT FREQUENCY RANGE SELmode QOUT/QOUT QREG/QREG Unit L H 155.5 - 166.6 regenerated CLKIN/CLKIN MHz 622 - 666.5 regenerated CLKIN/CLKIN MHz PIN DESCRIPTION Pin Name I/O Type CLKIN, CLKIN I Adjustable(1) Differential or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float to LVTTL threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected on the floating input. Description REFIN, REFIN I Adjustable(1) Differential reference clock input. The reference clock input is used as an input to the PLL when CLKIN/CLKIN fails. Differential or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float to LVTTL threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected on the floating input. SELmode I 2-level(2) 2 level input to select output frequency range for QOUT/QOUT and QREG/QREG (see Output Frequency Range table) PD I LVTTL QOUT, QOUT 0 Adjustable(3) Power Down Control. Shuts off entire chip when LOW. Differential clock output. LVPECL or LVDS outputs. QREG, QREG 0 Adjustable Regenerated clock output from CLKIN/CLKIN, LVPECL, or LVDS outputs. LOCK 0 LVTTL (3) TEST LOW when PLL is locked to CLKIN, HIGH in all other conditions Factory testing only. This pin should be left unconnected. NC No connection VDD PWR Power Supply GND PWR Ground NOTES: 1. Inputs are capable of translating the following interface standards: Single-ended 3.3V LVTTL levels Single-ended 2.5V LVTTL levels Differential LVPECL levels Differential LVDS levels 2. 2-level inputs are static inputs and must be tied to VDD or GND. 3. Outputs can be LVPECL or LVDS. 3 IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE CLOCK INPUT/OUTPUT CONFIGURATION DESCRIPTION Application Non-FEC REFIN (MHz) 19.44, 38.88, 77.76, 155.52, 311.04, 622.08 CKIN (MHz) SELmode 19.44 LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH 38.88 77.76 155.52 311.04 622.08 FEC 20.83, 41.66, 83.31, 166.63, 333.26, 666.52 20.83 41.66 83.31 166.63 333.26 666.52 10GE copper 19.53, 39.06, 78.12, 156.25, 312.5, 625 19.53 39.06 78.12 156.25 312.5 625 10GE optical 20.14, 40.28, 80.56, 161.13, 322.26, 644.53 20.14 40.28 80.56 161.13 322.26 644.53 4 QREG (MHz) QOUT (MHz) 19.44 19.44 38.88 38.88 77.76 77.76 155.52 155.52 311.04 311.04 622.08 622.08 20.83 20.83 41.66 41.66 83.31 83.31 166.63 166.63 333.26 333.26 666.52 666.52 19.53 19.53 39.06 39.06 78.12 78.12 156.25 156.25 312.50 312.5 625 625 20.14 20.14 40.28 40.28 80.56 80.56 161.13 161.13 322.26 322.26 644.53 644.53 155.52 622.08 155.52 622.08 155.52 622.08 155.52 622.08 155.52 622.08 155.52 622.08 166.63 666.52 166.63 666.52 166.63 666.52 166.63 666.52 166.63 666.52 166.63 666.52 156.25 625 156.25 625 156.25 625 156.25 625 156.25 625 156.25 625 161.13 644.53 161.13 644.53 161.13 644.53 161.13 644.53 161.13 644.53 161.13 644.53 IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS(1,2) Symbol IDD_PD ∆IDD Parameter Test Conditions Typ. Max Unit Power Supply Current VDD = Max., PD = GND, All outputs unloaded — 50 µA Power Supply Current per Input HIGH VDD = Max., VIN = 2.375V — 100 µA VDD = Max., QOUT = 622MHz, All outputs unloaded — 200 mA (LVTTL inputs only) ITOT Total Power Supply Current NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. As a general requirement, these parts must be capable of operating at the maximum frequency under a nominal load at a reasonable operating temperature. That means that these parts must not burn up under extended use in a typical application. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol VIHH VILL I2 Parameter Input HIGH Voltage Level(1) Input LOW Voltage Level(1) 2-Level Input DC Current Test Conditions 2-Level Inputs Only 2-Level Inputs Only VIN = VDD VIN = GND Min. VDD – 0.4 — — –200 HIGH Level LOW Level Max — 0.4 200 — Unit V V µA NOTE: 1. These inputs are normally wired to VDD or GND. If these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and the PLL may require additional tAQ time before all datasheet limits are achieved. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVTTL Symbol IIH IIL VIK VIN VIH VIL Parameter Input HIGH Current Input LOW Current Clamp Diode Voltage DC Input Voltage DC Input HIGH DC Input LOW Test Conditions VDD = 3.465V VDD = 3.465V VDD = 2.375V, IIN = -18mA Min. — — — - 0.3 1.7 — Typ. — — - 0.7 — — — Max ±1 ±1 - 1.2 +3.465 — 0.7 Unit µA V V V V DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVPECL(1) Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD = 3.465V -20 1 — +20 µA — VDD - 0.3 V 100 — — mV — VDD - 0.9 V Input Characteristics IIN Input Current (CLKIN, REFIN) VCMR Common Mode Input Voltage VDIF Differential Voltage Required to Toggle Input Output Characteristics VOH Output Voltage HIGH (terminated through 50Ω tied to VDD - 2V)(2) VDD - 1.15 VOL Output Voltage LOW (terminated through 50Ω tied to VDD - 2V) VDD - 1.95 — VDD - 1.61 V 0.55 — 0.93 V VSWING (2) Peak-to-Peak Output Voltage Swing NOTES: 1. VDD = 2.375 - 3.645V. 2. Not to exceed VDD - 0.05V. 5 IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVDS Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD = 3.465V -20 — +20 µA Input Characteristics IIN Input Current (CLKIN, REFIN) VCM Common Mode Input Voltage Range VDIF Differential Voltage Required to Toggle Input (1) 0.9 — VDD - 0.05 V 100 — — mV Output Characteristics VOT(+) Differential Output Voltage for the TRUE Binary State 247 — 454 mV VOT(-) Differential Output Voltage for the FALSE Binary State -247 — -454 mV ∆VOT Change in VOT Between Complementary Output States — — 50 mV VOS Output Common Mode Voltage (Offset Voltage) 1.125 1.2 1.375 V ∆VOS Change in VOS Between Complementary Output States — — 50 mV VOUT(+) and VOUT(-) = 0V — 9 24 mA VOUT(+) = VOUT(-) — 6 12 mA Min. Typ. Max. Unit 40 50 60 % IOS Outputs Short Circuit Current IOSD Differential Outputs Short Circuit Current NOTE: 1. Not to exceed VDD - 0.05V. INPUT TIMING REQUIREMENTS Symbol Parameter REFH Input Reference Clock Duty Cycle FREF Input Reference Clock Range 19.44 — 666.52 MHz REFTOL Input Reference Clock Frequency Tolerance -100 — 100 ppm FCLKIN Clock in Frequency Range 19.44 — 666.52 MHz Clock in Duty Cycle 40 50 60 % Acquisition Time from Return of Valid CLKIN — 60 150 us Frequency Tolerance for LOCK -600 ±450 600 ppm Max. Unit MHz CLKIN H tAQ LOCKTOL tJIT(TOL) Tolerance to Input Jitter GR-253 Sect. 5.6.2.2 AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol QOUT Parameter Multiplied Clock Output Frequency QREG Regenerated Clock Output Frequency CLKIN Input Clock Frequency tR Output Rise Time tF Output Fall Time tSK PLLBW tP tJ tDUTY Min. Typ. SELmode = LOW 155.52 — 166.63 SELmode = HIGH 622.08 — 666.52 19.44 — 666.52 MHz 19.44 — 667 MHz LVPECL — 150 — ps LVDS — 100 — LVPECL — 150 — LVDS — 100 — ps Skew between QOUT and QREG — 10 20 ps PLL Bandwidth 250 305 500 KHz dB Jitter Transfer Peaking — 0.05 0.1 Output frequency = 622MHz - 666.5MHz — 0.4 1 Jitter Generation(1) Output frequency = 155.5MHz - 166.6MHz — 0.8 3.4 (with 12KHz to 20MHz filter) Output frequency = 77.7MHz - 83.4MHz — 1.2 3.5 45 — 55 Output Duty Cycle NOTE: 1. All input frequencies permitted by PLL bandwidth. 6 ps (RMS) % IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE TEST CONDITIONS A LVDS DRIVER 50Ω VDIFF VT TEST POINT 50Ω B Test Circuit for LVDS Output Characteristics A 50Ω VDIFF VT 50Ω B Test Circuit for LVDS Input Characteristics A LVPECL DRIVER 50Ω VDIFF VDD - 2V 50Ω B Test Circuit for LVPECL Output Characteristics A 50Ω VDIFF VB 50Ω B VB = VDD - 2V Test Circuit for LVPECL Input Characteristics 7 IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type XX Package X Process CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 I -40°C to +85°C (Industrial) NL Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package 5T929-10 5T929-30 Precision Clock Generator - LVDS Output Precision Clock Generator - LVPECL Output for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 8 for Tech Support: [email protected] (408) 654-6459