IDT5V928 8 OUTPUT CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE IDT5V928 8 OUTPUT CLOCK GENERATOR DESCRIPTION: FEATURES: • • • • • • • • 3V to 3.6V operating voltage 50MHz to 160MHz output frequency range Input from fundamental crystal oscillator or external source Internal PLL feedback (loading feedback output relative to other outputs, adjusts propagation delay between REF inputs and outputs) Select inputs (S[1:0]) for FB divide selection (multiply ratio of 2, 3, 4, 4.25, 5, 6, 6.25, and 8) Low jitter PLL bypass for testing and power-down control (S1 = H, S0 = H, µ A) powers part down <500µ Available in TSSOP package The IDT5V928 is a low-cost, low skew, low jitter, and high-performance clock synthesizer. It has been specially designed to interface with Gigabit Ethernet (125MHz), Fibre CHannel (106.25MHz), and OC-3 (155.52MHz) applications. It can be programmed to provide output frequencies ranging from 50MHz to 160MHz, with input frequencies ranging from 6.25MHz to 80MHz. The IDT5V928 includes an internal RC filter that provides excellent jitter characteristics and eliminates the need for external components. When using the optional crystal input, the chip accepts a 10 - 40MHz fundamental mode crystal with a maximum equivalent series resistance of 50Ω. APPLICATIONS: • • • • • • Gigabit ethernet Router Network switches SAN Instrumentation Fibre channel FUNCTIONAL BLOCK DIAGRAM OE VCO DIVIDE 1/N Q0 PH AS E DETEC TO R REF CH ARGE PU M P LO OP FILTER VC O Q1 Q2 0 Q3 1 Q4 Q5 X2 CRY STAL OSCILLATO R Q6 SELECT MO D E Q7 X1 S1 S0 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE FEBRUARY 2003 1 c 2003 Integrated Device Technology, Inc. DSC 5854/5 IDT5V928 8 OUTPUT CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION S0 REF 1 24 X1 2 23 S1 X2 3 22 OE VDD 4 21 GND VDDQ 5 20 VDDQ Q0 6 19 Q7 Q1 7 18 Q6 GND 8 17 GND Symbol Description VDD/VDDQ Max. Unit Supply Voltage to Ground – 0.5 to +4.6 V VI Input Voltage – 0.5 to +4.6 V IO Output Current ±50 mA TSTG Storage Temperature – 65 to +150 °C TJ Junction Temperature 150 °C NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 9 16 GND GND Q2 10 15 Q5 Q3 11 14 Q4 PIN DESCRIPTION VDDQ 12 13 VDDQ Pin Name Type TSSOP TOP VIEW CRYSTAL SPECIFICATION The crystal oscillators should be fundamental mode quartz crystals: overtone crystals are not suitable. Crystal frequency should be specified for parallel resonance with 50Ω maximum equivalent series resonance. Crystal tuning capacitors should be connected from X2/REF to GND and from X1 to GND. Description S[1:0] I Three level divider/mode select pins. Float to MID. OE I Output enable bar. OE has a pull-down. Output Q[1:7] tristated when HIGH. Output Q0 remains running when in PLL mode and tri-states when in TEST mode. X1 I Crystal oscillator input. Connect to GND if oscillator not required. X2 I Crystal oscillator output. Leave unconnected for clock input. REF I Input clock. Connect to X2 if crystal oscillator is used. Q[1:7] O Output at N*REF frequency Q0 O Output at N*REF internally connected for PLL feedback VDDQ PWR VDD PWR Power supply for the device outputs. Connect to VDD on PCB. Power supply for the device core and inputs. Connect to VDD on PCB. GND PWR Ground supply DIVIDE SELECTION TABLE(1) S1 S0 Divide-by-N Value Mode L L 2 PLL L M 3 PLL L H 4 PLL M L 4.25 PLL M M 5 PLL M H 6 PLL H L 6.25 PLL H M 8 PLL H H TEST TEST (2) NOTES: 1. H = HIGH M = MEDIUM L = LOW 2. Test mode for low frequency testing. In this mode, REF clock bypasses the VCO (VCO powered down) and the crystal oscillator is powered down. 2 IDT5V928 8 OUTPUT CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE COMMON OUTPUT FREQUENCY EXAMPLES (MHz) Output 50 Input 25 10 16 12 25 10 15 20 FB Divide Selection S[1:0] LL MH LH MH LM HM MH MM Output 60 64 72 75 80 90 100 106.25 106.25 120 125 125 125 150 155.52 Input 17 25 15 20 25 62.5 25 19.44 FB Divide Selection S[1:0] HL ML HM HL MM LL MH HM OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit VDD/VDDQ Power Supply Voltage 3 3.3 3.6 V TA Operating Temperature - 40 25 +85 °C CL Output Load Capacitance — — 15 pF CIN Input Capacitance, OE, F = 1MHz, VIN = 0V, TA = 25°C — 5 7 pF DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VDD/VDDQ = 3.3V ±0.3V Symbol VIL VIH VIHH VIMM VILL IIN I3 IIH VOL VOH Parameter Input LOW Voltage Input HIGH Voltage Input HIGH Voltage Input MID Voltage Input LOW Voltage Input Leakage Current (REF input only) 3-Level Input DC Current, S[1:0] Input HIGH Current Output LOW Voltage Output HIGH Voltage Test Conditions 3-level input only 3-level input only 3-level input only VIN = VDD or GND,VDD = Max. VIN = VDD HIGH Level VIN = VDD/2 MID Level VIN = GND LOW Level VIN = VDD IOL = 12mA IOH = -12mA 3 Min. — 2 VDD - 0.6 VDD/2 - 0.3 — -5 — - 50 - 200 — — 2.4 Typ. — — — — — — — — — — — — Max 0.8 — — VDD/2 + 0.3 0.6 +5 +200 +50 — 100 0.4 — Unit V V V V V µA µA µA V V IDT5V928 8 OUTPUT CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol IDD_PD Parameter Test Conditions (1) Power Down Current VDD = Max. Min. Typ. Max Unit — — 500 µA S[1:0] = HH OE = L; REF = L; X1 = L All outputs unloaded ∆IDD Supply Current per Input VDD = Max., VIN = 3V — — 30 µA IDD Dynamic Supply Current VDD = 3.6V — — 130 mA Unit S[1:0] = LL OE = L FOUT = 150MHz All outputs unloaded NOTE: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter Test Conditions Min. Typ. Max. tR, tF Rise Time, Fall Time 0.8V to 2V — 0.7 1.5 ns dT Output/Duty Cycle VT = VDDQ/2 45 50 55 % tPD REF to Q0(1) VT = VDDQ/2 tSK Output to Output Skew (Q0 to Q1:7) Equal loads tJ Cycle - Cycle Jitter fOUT ≥ 100MHz fOUT fOUT ≥ 100MHz, all N -200 — 200 50 < fOUT < 160MHz, N ≤ 4 -200 — 200 50 < fOUT < 160MHz, N ≥ 4.25 -350 — 350 Output Frequency ps — — 200 ps -100 — 100 ps 50 — 160 MHz NOTE: 1. When using a clock input. INPUT TIMING REQUIREMENTS Symbol Description(1) Min. Max. Unit — 10 ns/V Input clock pulse, HIGH or LOW(2) 2 — ns DH Input duty cycle(2) 10 90 % fOSC XTAL oscillator frequency — 40 MHz 50/N 160/N MHz tR, tF Maximum input rise and fall time, 0.8V to 2V(2) tPWC fIN Input frequency(2) NOTES: 1. Where pulse width implied by DH is less than the tPWC limit, tPWC limit applies, 2. When using a clock input. 4 IDT5V928 8 OUTPUT CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE AC TEST LOADS AND WAVEFORMS V DD 150 Ω OUTPUT 150 Ω 15pF AC Test Load 3V 2V V TH = V D D /2 0.8 0V 1ns 1ns Input Test Waveform VDDQ 2V V TH = V D DQ /2 0.8 0V tR tF Output Waveform 5 IDT5V928 8 OUTPUT CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXX Device Type X Package X Proceed I Industrial Temperature Range (- 40° C to + 85° C) PG Thin Shrink Small Outline Package 5V928 Communications Clock Multiplier CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459