CY62138V MoBL™ 2-Mbit (256K x 8) Static RAM This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that reduces power consumption by 99% when addresses are not toggling. The device can be put into standby mode when deselected (CS1 HIGH or CS2 LOW). Features • High Speed: — 70 ns • Low voltage range: — 2.7V – 3.6V • Ultra-low active power • Low standby power • Easy memory expansion with CS1/CS2 and OE features • TTL-compatible inputs and outputs Writing to the device is accomplished by taking Chip Enable One (CS1) and Write Enable (WE) inputs LOW and Chip Enable Two (CS2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable One (CS1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CS2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. • Automatic power-down when deselected • CMOS for optimum speed/power • Available in non Pb-free 36-ball FBGA package Functional Description The CY62138V is a high-performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CS1 HIGH or CS2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CS1 LOW, CS2 HIGH, and WE LOW). The CY62138V is available in a 36-ball FBGA package. Logic Block Diagram Pin Configuration 36-ball FBGA TOP View I/O0 A4 A5 A6 A7 A8 CS1 CS 2 256K x 8 ARRAY SENSE AMPS A0 A1 A2 A3 ROW DECODER Data in Drivers 3 4 5 6 A0 A1 CS2 A3 A6 A8 A I/O4 A2 WE A4 A7 I/O0 B NC A5 I/O1 C I/O5 I/O2 VSS VCC D VCC VSS E I/O2 F I/O3 I/O4 POWER DOWN I/O6 NC A17 I/O6 I/O7 OE CS1 A16 A15 I/O3 G I/O7 A9 A10 A11 A12 A13 A14 H A9 A 10 A 11 A12 A13 A14 A15 A16 A17 WE OE 2 I/O1 I/O5 COLUMN DECODER 1 Cypress Semiconductor Corporation Document #: 38-05088 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 21, 2006 [+] Feedback CY62138V MoBL™ Product Portfolio Power Dissipation (Industrial) VCC Range (V) Product VCC(min) VCC(typ)[1] VCC(max) Speed (ns) 2.7 3.0 3.6 70 CY62138V Operating, ICC (mA) Standby, ISB2 (µA) Typ.[1] Maximum Typ.[1] Maximum 7 15 1 15 DC Input Voltage[2] .................................... −0.5V to VCC + 0.5V Maximum Ratings Output Current into Outputs (LOW) .............................20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature .....................................−65°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied ..................................................−55°C to +125°C Operating Range Supply Voltage to Ground Potential..................−0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ........................................ −0.5V to VCC + 0.5V Device CY62138V Range Industrial Ambient Temperature VCC −40°C to +85°C 2.7V to 3.6V Electrical Characteristics Over the Operating Range CY62138V Parameter Description Test Conditions Min. VOH Output HIGH Voltage IOH = −1.0 mA VCC = 2.7V VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V VIH Input HIGH Voltage VCC = 3.6V VIL Input LOW Voltage VCC = 2.7V IIX Input Leakage Current GND < VI < VCC −1 IOZ Output Leakage Current GND < VO < VCC, Output Disabled −1 ICC VCC Operating Supply Current IOUT = 0 mA, f = fMax = 1/tRC, CMOS Levels CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V, f = fMax ISB2 Automatic CE Power-down Current— CMOS Inputs CE > VCC−0.3V VIN > VCC−0.3V or VIN < 0.3V, f = 0 Unit V 0.4 V 2.2 VCC + 0.5V V −0.5 0.8 V +1 +1 µA +1 +1 µA 7 15 mA 1 2 mA 100 µA 15 µA IOUT = 0 mA, f = 1 MHz, CMOS Levels Automatic CE Power-down Current— CMOS Inputs Max. 2.4 VCC = 3.6V ISB1 Typ.[1] VCC = 3.6V 1 Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max. Unit 6 pF 8 pF Notes: 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25°C. 2. VIL(min) = –2.0V for pulse durations less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05088 Rev. *B Page 2 of 9 [+] Feedback CY62138V MoBL™ AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES OUTPUT VCC Typ 10% R2 30 pF 90% 10% 90% GND < 5 ns < 5 ns INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V Parameters 3.0V Unit R1 1105 Ohms R2 1550 Ohms RTH 645 Ohms VTH 1.75 Volts Data Retention Characteristics (Over the Operating Range) Parameter Conditions[4] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR Operation Recovery Time Typ.[1] Min. 1.0 VCC = 1.0V, CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V, No input may exceed VCC+0.3V 0.1 Max. Unit 3.6 V 5 µA 0 ns 100 µs Data Retention Waveform[5] DATA RETENTION MODE VCC VCC(min.) tCDR VDR > 1.0V VCC(min.) tR CE Notes: 4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 5. CE is the combination of both CS1 and CS2. Document #: 38-05088 Rev. *B Page 3 of 9 [+] Feedback CY62138V MoBL™ Switching Characteristics Over the Operating Range[4] 70 ns Parameter Description Min. Max. Unit Read Cycle tRC Read Cycle Time 70 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 70 ns tDOE OE LOW to Data Valid 35 ns tLZOE OE LOW to Low-Z[6] tHZOE OE HIGH to High-Z[6, 7] tLZCE CE LOW to Low-Z[6] tHZCE CE HIGH to High-Z[6, 7] tPU CE LOW to Power-up tPD CE HIGH to Power-down 70 10 ns ns 5 ns 25 10 ns ns 25 0 ns ns 70 ns Write Cycle[8, 9] tWC Write Cycle Time 70 ns tSCE CE LOW to Write End 60 ns tAW Address Set-up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 50 ns tSD Data Set-up to Write End 30 ns tHD Data Hold from Write End 0 ns tHZWE WE LOW to High-Z[6, 7] tLZWE WE HIGH to Low-Z[6] 25 10 ns ns Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[10, 11] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Notes: 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. Document #: 38-05088 Rev. *B Page 4 of 9 [+] Feedback CY62138V MoBL™ Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[5, 11, 12] tRC CE tACE OE tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE tPD tPU ICC VCC SUPPLY CURRENT 50% 50% ISB Write Cycle No. 1 (WE Controlled)[5, 8, 13, 14] tWC ADDRESS CE tAW tSA WE tHA tPWE OE tSD DATA I/O tHD DATAIN VALID NOTE 15 tHZOE Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05088 Rev. *B Page 5 of 9 [+] Feedback CY62138V MoBL™ Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[5, 8, 13, 14] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATAIN VALID Write Cycle No. 3 (WE Controlled, OE LOW)[5, 9, 14] tWC ADDRESS CE tAW tHA tSA WE tSD DATA I/O NOTE 15 tHZWE Document #: 38-05088 Rev. *B tHD DATAIN VALID tLZWE Page 6 of 9 [+] Feedback CY62138V MoBL™ Typical DC and AC Characteristics STANDBY CURRENT vs. AMBIENT TEMPERATURE 1.4 3.0 1.2 2.5 1.0 2.0 I CC ISB2 µA NORMALIZED I CC NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.8 0.6 VIN = VCC typ. TA = 25°C 0.4 ISB 1.5 1.0 0.5 0.0 0.2 0.0 1.7 2.2 2.7 3.2 -0.5 −55 3.7 NORMALIZED STANDBY CURRENT vs. SUPPLY VOLTAGE 105 NORMALIZED I CC vs.CYCLE TIME 1.50 1.4 NORMALIZEDICC 1.2 ISB2 1.0 0.8 0.6 25 AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) NORMALIZED ISB VCC = VCC typ. VIN = VCC typ. VIN = VCC typ. TA = 25°C 0.4 VCC = 3.3V TA = 25°C 1.00 0.50 0.2 0.10 0.0 1.0 3.7 2.8 1.9 5 1 15 10 CYCLE FREQUENCY (MHz) SUPPLY VOLTAGE (V) Truth Table CS1 CS2 WE OE Inputs/Outputs Mode Power H X X X High-Z Deselect/Power-down Standby (ISB) X L X X High-Z Deselect/Power-down Standby (ISB) L H H L Data Out Read Active (ICC) L H L X Data In Write Active (ICC) L H H H High-Z Deselect, Output Disabled Active (ICC) Ordering Information Speed (ns) Ordering Code Package Diagram 70 CY62138VLL-70BAI 51-85099 Package Type 36-ball Fine Pitch Ball Grid Array (7 x 7 x 1.2 mm) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts Document #: 38-05088 Rev. *B Page 7 of 9 [+] Feedback CY62138V MoBL™ Package Diagram 36-ball FBGA (7 x 7 x 1.2 mm) (51-85099) TOP VIEW BOTTOM VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2 3 4 5 6 6 4 3 2 1 B C C F G D E F 2.625 7.00±0.10 E 0.75 A B 5.25 A D 7.00±0.10 5 G H H A 1.875 A 0.75 B 7.00±0.10 3.75 7.00±0.10 0.15(4X) 0.15 C 0.21±0.05 0.53±0.05 0.25 C B 51-85099-*C 0.36 SEATING PLANE C 1.20 MAX. More Battery Life is a trademark, and MoBL is a registered trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05088 Rev. *B Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62138V MoBL™ Document History Page Document Title: CY62138V MoBL™ 2-Mbit (256K x 8) Static RAM Document Number: 38-05088 REV. ECN NO. Issue Date Orig. of Change ** 107348 06/12/01 SZV Change from Spec #: 38-00729 to 38-05088 *A 114936 05/28/02 CBD Replaced wrong package diagram with correct diagram (36-ball FBGA [see p. 8]) *B 486789 SEE ECN VKN Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court”. Updated Ordering Information table Document #: 38-05088 Rev. *B Description of Change Page 9 of 9 [+] Feedback