CYPRESS W158

W158
Spread Spectrum System Frequency Synthesizer
Features
CPU Output Jitter: ...................................................... 150 ps
• Maximized EMI suppression using Cypress’s spread
spectrum technology
• Intel® CK98 Specification compliant
• 0.5% downspread outputs deliver up to 10 dB lower EMI
• Four skew-controlled copies of CPU output
• Eight copies of PCI output (synchronous w/CPU output)
• Four copies of 66-MHz fixed frequency 3.3V clock
• Two copies of CPU/2 outputs for synchronous memory
reference
• Three copies of 16.67-MHz IOAPIC clock, synchronous
to CPU clock
• One copy of 48-MHz USB output
• Two copies of 14.31818-MHz reference clock
• Programmable to 133- or 100-MHz operation
• Power management control pins for clock stop and shut
down
• Available in 56-pin SSOP
CPUdiv2, IOAPIC Output Jitter: ..................................250 ps
48 MHz, 3V66, PCI Output Jitter: ................................ 500 ps
CPU0:3, CPUdiv2_ 0:1 Output Skew: ......................... 175 ps
PCI_F, PCI1:7 Output Skew: .......................................500 ps
3V66_0:3, IOAPIC0:2 Output Skew: ...........................250 ps
CPU to 3V66 Output Offset: ........... 0.0 to1.5 ns (CPU leads)
3V66 to PCI Output Offset:.......... 1.5 to 3.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ...... 1.5 to 4.0 ns (CPU leads)
CPU to PCI Output Offset: ............ 1.5 to 4.0 ns (CPU leads)
Logic inputs, except SEL133/100#, have 250-kΩ pull-up
resistors
Table 1. Pin Selectable Frequency[1]
SEL133/100#
1
0
CPU0:3 (MHz)
133 MHz
100 MHz
PCI
33.3 MHz
33.3 MHz
Note:
1. See Table 2 for complete mode selection details.
Key Specifications
Supply Voltages: ...................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
Block Diagram
X1
X2
Pin Configuration
2
XTAL
OSC
REF0:1
CPU_STOP#
STOP
Clock
Logic
4
CPU0:3
2
÷2
CPUdiv2_0:1
PLL 1
SEL1
SEL133/100#
÷2/÷1.5
STOP
Clock
Logic
4
3V66_0:3
1
PCI_F
÷2
PWRDWN#
7
STOP
Clock
Logic
PCI1:7
PCI_STOP#
3
Power
Down
Logic
÷2
IOAPIC0:2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
W158
SPREAD#
SEL0
GND
REF0
REF1
VDDQ3
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
GND
3V66_0
3V66_1
VDDQ3
GND
3V66_2
3V66_3
VDDQ3
SEL133/100#
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDQ2
IOAPIC2
IOAPIC1
IOAPIC0
GND
VDDQ2
CPUdiv2_1
CPUdiv2_0
GND
VDDQ2
CPU3
CPU2
GND
VDDQ2
CPU1
CPU0
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWRDWN#
SPREAD#
SEL1
SEL0
VDDQ3
48MHz
GND
Three-state
Logic
1
PLL2
48MHz
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
October 12, 1999, rev. **
W158
Pin Definitions
Pin
Pin No.
Type
Pin Description
41, 42, 45, 46
O CPU Clock Outputs 0 through 3: These four CPU clocks run at a frequency set by
SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2.
CPUdiv2_ 0:1
49, 50
O Synchronous Memory Reference Clock Output 0 through 1: Reference clock for Direct RDRAM clock generators running at 1/2 CPU clock frequency. Output voltage swing
is set by the voltage applied to VDDQ2.
PCI1:7
9, 11, 12, 14,
O PCI Clock Outputs 1 through 7: These seven PCI clock outputs run synchronously to
15, 17, 18
the CPU clock. Voltage swing is set by the power connection to VDDQ3. PCI1:7 outputs
are stopped when PCI _STOP# is held LOW.
PCI_F
8
O PCI_F (PCI Free-running): This PCI clock output runs synchronously to the CPU clock.
Voltage swing is set by the power connection to VDDQ3. PCI_F is not affected by the state
of PCI_STOP#.
REF0:1
2, 3
O 14.318-MHz Reference Clock Output: 3.3V copies of the 14.318-MHz reference clock.
IOAPIC0:2
53, 54, 55
O I/O APIC Clock Output: Provides 16.67-MHz fixed frequency. The output voltage swing
is set by the power connection to VDDQ2.
48MHz
30
O 48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by voltage
applied to VDDQ3.
3V66_0:3
21, 22, 25, 26
O 66-MHz Output 0 through 3: Fixed 66-MHz outputs. Output voltage swing is controlled
by voltage applied to VDDQ3.
Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting clock output
SEL0:1
32, 33
I
modes.
Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output freSEL133/100#
28
I
quency as shown in Table 1.
Crystal Connection or External Reference Frequency Input: Connect to either a
X1
5
I
14.318-MHz crystal or an external reference signal.
X2
6
O Crystal Connection: An output connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
Active LOW Spread Spectrum Enable: 3.3V LVTTL-compatible input that enables
SPREAD#
34
I
spread spectrum mode when held LOW.
Active LOW Power Down Input: 3.3V LVTTL-compatible asynchronous input that rePWRDWN#
35
I
quests the device to enter power-down mode.
Active LOW CPU Clock Stop: 3.3V LVTTL-compatible asynchronous input that stops all
CPU_STOP#
36
I
CPU and 3V66 clocks when held LOW. CPUdiv2 outputs are unaffected by this input.
Active LOW PCI Clock Stop: 3.3V LVTTL-compatible asynchronous input that stops all
PCI_STOP#
37
I
PCI outputs except PCI_F when held LOW.
Power Connection: Power supply for PCI output buffers, 48-MHz USB output buffer,
VDDQ3
4, 10, 16, 23,
P
27, 31, 39
Reference output buffers, 3V66 output buffers, core logic, and PLL circuitry. Connect to
3.3V supply.
Power Connection: Power supply for IOAPIC, CPU, and CPUdiv2 output buffers. ConVDDQ2
43, 47, 51, 56
P
nect to 2.5V supply.
GND
1, 7, 13, 19,
G Ground Connection: Connect all ground pins to the common system ground plane.
20, 24, 29, 38,
40, 44, 48, 52
Pin Name
CPU0:3
All CPU, PCI, and IOAPIC clocks can be synchronously modulated for spread spectrum operations. Cypress employs proprietary techniques that provide the maximum EMI reduction
while minimizing the clock skews that could reduce system
timing margins. Spread Spectrum modulation is enabled by
the active LOW control signal SPREAD#.
Overview
The W158 is designed to provide the essential frequency
sources to work with advanced multiprocessing Intel architecture platforms. Split voltage supply signaling provides 2.5V
and 3.3V clock frequencies operating up to 133 MHz.
The W158 also includes power management control inputs. By
using these inputs, system logic can stop CPU and/or PCI
clocks or power down the entire device to conserve system
power.
From a low-cost 14.31818-MHz reference crystal oscillator,
the W158 generates 2.5V clock outputs to support CPUs, core
logic chip set, and Direct RDRAM clock generators. It also provides skew-controlled PCI and IOAPIC clocks synchronous to
CPU clock, 48-MHz Universal Serial Bus (USB) clock, and replicates the 14.31818-MHz reference clock.
2
W158
Spread Spectrum Clocking
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1.
The output clock is modulated with a waveform depicted in
Figure 2. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% downspread. Figure 2
details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
As shown in Figure 1, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log10(P) + 9*log10(F)
Time
Figure 2. Modulation Waveform Profile
3
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
100%
80%
60%
40%
20%
0%
–20%
–40%
–60%
–80%
–100%
10%
Frequency Shift
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
W158
Mode Selection Functions
The W158 supports the following operating modes controlled through the SEL133/100#, SEL0, and SEL1 inputs.
Table 2. Select Functions
SEL133/100#
SEL1
SEL0
0
0
0
All Outputs Three-State
Function
0
0
1
(Reserved)
0
1
0
Active 100-MHz, 48-MHz PLL Inactive
0
1
1
Active 100-MHz, 48-MHz PLL Active
1
0
0
Test Mode
1
0
1
(Reserved)
1
1
0
Active 133-MHz, 48-MHz PLL Inactive
1
1
1
Active 133-MHz, 48-MHz PLL Active
Table 3. Truth Table
SEL
133/100#
SEL1
SEL0
CPU
CPUdiv2
3V66
PCI
48MHz
REF
IOAPIC
Notes
0
0
0
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
2
0
0
1
n/a
n/a
n/a
n/a
n/a
n/a
n/a
0
1
0
100 MHz
50 MHz
66 MHz
33 MHz
HI-Z
14.318 MHz 16.67 MHz
3
0
1
1
100 MHz
50 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz 16.67 MHz
4, 7, 8
1
0
0
TCLK/2
TCLK/4
TCLK/4
TCLK/8
TCLK/2
1
0
1
n/a
n/a
n/a
n/a
n/a
1
1
0
133 MHz
66 MHz
66 MHz
33 MHz
HI-Z
14.318 MHz 16.67 MHz
3
1
1
1
133 MHz
66 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz 16.67 MHz
4, 7, 8
TCLK
TCLK16
n/a
n/a
5, 6
Table 4. Maximum Supply Current
Max. 2.5V supply consumption
Max. discrete cap loads,
VDDQ2=2.625V
All static inputs=VDDQ3 or GND
Max. 3.3V supply consumption
Max. discrete cap loads,
VDDQ3=3.465V or GND
Powerdown Mode
(PWRDWN#=0)
100 µA
200 µA
Full Active 100 MHz
SEL133/100#=0
SEL1, 0=11
CPU_STOP#, PCI_STOP#=1
75 mA
160 mA
Full Active 133 MHz
SEL133/100#=0
SEL1, 0=11
CPU_STOP#, PCI_STOP#=1
90 mA
160 mA
Condition
Notes:
2. Provided for board level “bed of nails” testing.
3. 48-MHz PLL disabled to reduce component jitter.
4. Normal” mode of operation.
5. TCLK is a test clock over driven on the X1 input during test mode. TCLK mode is based on 133-MHz CPU select logic.
6. Required for DC output impedance verification.
7. Range of reference frequency is min.=14.316, nominal = 14.31818 MHz, max.=14.32 MHz.
8. Frequency accuracy of 48 MHz is +167 PPM to match USB default.
4
W158
Table 5. Clock Enable Configuration[9, 10, 11, 12, 13, 14]
CPU_STOP# PWRDWN# PCI_STOP#
CPU
CPUdiv2
IOAPIC
3V66
PCI
PCI_F
REF,
48MHz
OSC.
VCOs
X
0
X
LOW
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
0
1
0
LOW
ON
ON
LOW
LOW
ON
ON
ON
ON
0
1
1
LOW
ON
ON
LOW
ON
ON
ON
ON
ON
1
1
0
ON
ON
ON
ON
LOW
ON
ON
ON
ON
1
1
1
ON
ON
ON
ON
ON
ON
ON
ON
ON
Table 6. Power Management State Transition[15, 16]
Latency
Signal
Signal State
No. of rising edges of PCI Clock
CPU_STOP#
0 (disabled)
1
1 (enabled)
1
PCI_STOP#
0 (disabled)
1
1 (enabled)
1
PWRDWN#
1 (normal operation)
3 ms
0 (power down)
2 max.
Timing Diagrams
CPU_STOP# Timing Diagram[17, 18, 19, 20, 21, 22]
CPU
(internal)
PCI
CPU_STOP#
PCI_STOP#
HI
PWRDWN#
HI
CPU
(external)
3V66
Notes:
9. LOW means outputs held static LOW as per latency requirement below.
10. ON means active.
11. PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs.
12. All 3V66 as well as all CPU clocks stop cleanly when CPU_STOP# is pulled LOW.
13. CPUdiv2, IOAPIC, REF, 48MHz signals are not controlled by the CPU_STOP# functionality and are enabled in all conditions except PWRDWN#=LOW.
14. An “x” indicates a “don’t care” condition.
15. Clock on/off latency is defined in the number of rising edges of the free-running PCI clock between when the clock disable goes LOW/HIGH to when the first
valid clock comes out of the device.
16. Power up latency is from when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
17. All internal timing is referenced to the CPU clock.
18. The internal label means inside the chip and is a reference only. This, in fact, may not be the way that the control is designed.
19. CPU_STOP# signal is an input signal that must be made synchronous to free-running PCI_F.
20. 3V66 clocks also stop/start before.
21. PWRDWN# and PCI_STOP# are shown in a HIGH state.
22. Diagrams shown with respect to 133 MHz. Similar operation when CPU clock is 100 MHz.
5
W158
Timing Diagrams (continued)
PCI_STOP# Timing Diagram[18, 22, 23, 24, 25, 26]
CPU
PCI
(internal)
PCI_STOP#
CPU_STOP#
HI
PWRDWN#
HI
PCI_F
(external)
PCI
(external)
PWRDWN# Timing Diagram[18, 22, 23, 27, 28]
CPU
(internal)
PCI
(internal)
PWRDWN#
CPU
(external)
PCI
(external)
VCO
Crystal
Notes:
23. All internal timing is referenced to the CPU clock.
24. PCI_STOP# signal is an input signal that must be made synchronous to PCI_F output.
25. All other clocks continue to run undisturbed.
26. PWRDWN# and CPU_STOP# are shown in a HIGH state.
27. PWRDWN is an asynchronous input and metastable conditions could exist. This signal must be synchronized.
28. The shaded Sections on the VCO and the Crystal signals indicate an active clock.
6
W158
Absolute Maximum Ratings
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
.
Parameter
Description
Rating
Unit
V
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
–65 to +150
°C
0 to +70
°C
–55 to +125
°C
2 (min.)
kV
TSTG
Storage Temperature
TA
Operating Temperature
TB
Ambient Temperature under Bias
ESDPROT
Input ESD Protection
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
160
mA
90
mA
Supply Current
IDD-3.3V
IDD-2.5
Combined 3.3V Supply Current
CPU0:3 =133 MHz[29]
Combined 2.5V Supply Current
[29]
CPU0:3 =133 MHz
Logic Inputs (All referenced to VDDQ3 = 3.3V)
VIL
Input Low Voltage
GND
–0.3
0.8
V
VIH
Input High Voltage
2.0
VDD+
0.3
V
IIL
Input Low Current[30]
–25
µA
[30]
IIH
Input High Current
10
µA
IIL
Input Low Current, SEL133/100#[30]
–5
µA
5
µA
Max.
Unit
50
mV
IIH
[30]
Input High Current, SEL133/100#
Clock Outputs
CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2)
Test Condition
Min.
VOL
Output Low Voltage
IOL = 1 mA
VOH
Output High Voltage
IOH = –1 mA
2.2
IOL
Output Low Current
VOL = 1.25V
45
IOH
Output High Current
VOH = 1.25V
48MHz, REF (Referenced to VDDQ3)
Output Low Voltage
VOL
VOH
Output High Voltage
IOL
IOH
Test Condition
Typ.
V
65
100
mA
45
65
100
mA
Min.
Typ.
Max.
Unit
50
mV
IOL = 1 mA
IOH = –1 mA
3.1
Output Low Current
VOL = 1.5V
45
65
100
mA
Output High Current
VOH = 1.5V
45
65
100
mA
Min.
Typ.
Max.
Unit
50
mV
PCI, 3V66 (Referenced to VDDQ3)
Test Condition
V
VOL
Output Low Voltage
IOL = 1 mA
VOH
Output High Voltage
IOH = –1 mA
3.1
IOL
Output Low Current
VOL = 1.5V
70
100
145
mA
IOH
Output High Current
VOH = 1.5V
65
95
135
mA
Notes:
29. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors.
30. W158 logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).
7
V
W158
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input threshold Voltage[31]
CLOAD
Load Capacitance, Imposed on
External Crystal[32]
CIN,X1
X1 Input Capacitance[33]
Pin X2 unconnected
1.65
V
18
pF
28
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
COUT
Output Pin Capacitance
6
pF
LIN
Input Pin Inductance
7
nH
Except X1 and X2
5
pF
3.3V AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, V DDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[34]
3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
66.6
Unit
f
Frequency
Note 35
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior
to frequency stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination
value.
15
MHz
Ω
Notes:
31. X1 input threshold voltage (typical) is VDD/2.
32. The W158 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF;
this includes typical stray capacitance of short PCB traces to crystal.
33. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
34. Period, jitter, offset, and skew measured on rising edge at 1.5V.
35. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz.
8
W158
PCI Clock Outputs, PCI_F and PCI1:7 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
[36]
Typ.
Max.
Unit
tP
Period
Measured on rising edge at 1.5V
30
ns
tH
High Time
Duration of clock cycle above 2.4V
12
ns
tL
Low Time
Duration of clock cycle below 0.4V
12
ns
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
tJC
Jitter, Cycle-to-Cycle
tSK
1
4
V/ns
1
4
V/ns
45
55
%
Measured on rising edge at 1.5V. Maximum difference of
cycle time between two adjacent cycles.
500
ps
Output Skew
Measured on rising edge at 1.5V
500
ps
tO
3V66 to PCI Clock
Skew
Covers all 3V66/PCI outputs. Measured on rising edge at
1.5V. 3V66 leads PCI output.
1.5
3
ns
tq
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at
1.5V. CPU leads PCI output.
1.5
4
ns
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for determining series termination value.
Ω
15
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
f
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Typ.
Max.
14.318
Unit
MHz
2
V/ns
0.5
2
V/ns
45
55
%
3
ms
Ω
25
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
MHz
fD
Deviation from 48 MHz
(48.008 – 48)/48
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Note:
36. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
9
25
Ω
W158
2.5V AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, V DDQ2= 2.5V±5%
fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[37]
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
CPU = 133 MHz
Parameter
Description
Test Condition/Comments
CPU = 100 MHz
Min. Typ. Max. Min.
Typ. Max. Unit
tP
Period
Measured on rising edge at 1.25V
7.5
tH
High Time
Duration of clock cycle above 2.0V
1.87
3.0
ns
tL
Low Time
Duration of clock cycle below 0.4V
1.67
2.8
ns
tR
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
4
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Maximum difference of cycle time between
two adjacent cycles.
150
150
ps
tSK
Output Skew
Measured on rising edge at 1.25V
175
175
ps
fST
Frequency Stabilization from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
3
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for determining series termination value.
7.65
10
10.2
ns
Ω
20
20
CPU = 133 MHz
CPU = 100 MHz
CPUdiv2 Clock Outputs, CPUdiv2_0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min.
Typ. Max. Unit
tP
Period
Measured on rising edge at 1.25V
15
tH
High Time
Duration of clock cycle above 2.0V
5.25
7.5
ns
tL
Low Time
Duration of clock cycle below 0.4V
5.05
7.3
ns
tR
Output Rise Edge Rate Measured from 0.4V to 2.0V
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
tD
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Maximum difference of cycle time between
two adjacent cycles.
tSK
Output Skew
Measured on rising edge at 1.25V
fST
Frequency Stabilization from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used for determining series termination value.
Note:
37. Period, Jitter, offset, and skew measured on rising edge at 1.25V.
10
15.3
1
4
20
20
20.4
1
ns
4
V/ns
1
4
V/ns
45
55
%
250
250
ps
175
175
ps
3
3
ms
20
Ω
W158
IOAPIC Clock Outputs, IOAPIC0:2 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency
Note 38
tR
Output Rise Edge Rate
Measured from 0.4V to 2.0V
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.25V
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Ordering Information
W158
Package
Name
H
Typ
Max
16.67
Note:
38. IOAPIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz.
Ordering Code
Min
Package Type
56-pin SSOP (300 mils)
Document #: 38-00819
11
1
Unit
MHz
4
V/ns
1
4
V/ns
45
55
%
3
ms
20
Ω
W158
Package Diagram
56-Pin Small Shrink Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
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