W144
440BX AGPset Spread Spectrum Frequency Synthesizer
Features
Table 1. Pin Selectable Frequency
• Maximized electromagnetic interference (EMI)
suppression using Cypress’ Spread Spectrum
technology
• Single chip system frequency synthesizer for Intel®
440BX AGPset
• Two copies of CPU output
• Six copies of PCI output 1
• One 48-MHz output for USB
• One 24-MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• Thirteen SDRAM outputs provide support for three
DIMMs
• Supports frequencies up to 150 MHz
• I2C interface for programming
• Power management control inputs
Logic Block Diagram
REF0/(PCI_STOP#)
REF1/FS2
XTAL
OSC
PLL Ref Freq
Stop
Clock
Control
I/O Pin
Control
VDDQ2
IOAPIC
CLK_STOP#
CPU1
CPU_F
÷2,3,4
VDDQ3
PCI_F/MODE
PCI1/FS3
PCI2
PCI3
Stop
Clock
Control
PCI4
SDATA
SCLK
I2C
Logic
VDDQ3
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
**PCI1/FS3
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDATA
I2C
SCLK
{
PCI5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
W144
VDDQ2
Stop
Clock
Control
PLL 1
Input Address
CPU_F, CPU1
FS2 FS1 FS0
(MHz)
PCI_F, 1:5 (MHz)
1
1
1
133.6
33.4 (CPU/4)
1
1
0
124
31 (CPU/4)
1
0
1
150
37.5 (CPU/4)
1
0
0
140
35 (CPU/4)
0
1
1
105
35 (CPU/3)
0
1
0
110
36.7 (CPU/3)
0
0
1
115
38.3 (CPU/3)
0
0
0
120
40 (CPU/3)
1
1
1
100.2
33.4 (CPU/3)
1
1
0
133.3
44.43 (CPU/3)
1
0
1
112
37.3 (CPU/3)
1
0
0
103
34.3 (CPU/3)
0
1
1
66.8
33.4 (CPU/2)
0
1
0
83.3
41.7 (CPU/2)
0
0
1
75
37.5 (CPU/2)
0
0
0
124
41.3 (CPU/3)
Pin Configuration [1]
VDDQ3
X1
X2
FS3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ2
IOAPIC
REF1/FS2*
GND
CPU_F
CPU1
VDDQ2
CLK_STOP#
SDRAM_F
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS0*
24MHz/FS1*
VDDQ3
48MHz/FS0
PLL2
÷2
SDRAMIN
Stop
Clock
Control
24MHz/FS1
VDDQ3
SDRAM0:11
12
SDRAM_F
Note:
1. * Has an internal pull-up resistors. It should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping
while ** has an internal pull down resistor.
Cypress Semiconductor Corporation
Document #: 38-07153 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 16, 2004
W144
Pin Description
Pin Name
CPU_F
No.
44
CPU1
43
PCI2:5
10, 11, 12,
13
8
PCI1/FS3
PCI_F/MODE
7
CLK_STOP#
41
IOAPIC
47
48MHz/FS0
26
24MHz/FS1
25
REF1/FS2
46
REF0/
(PCI_STOP#)
2
SDRAMIN
15
SDRAM0:11
SDRAM_F
38, 37, 35,
34, 32, 31,
29, 28, 21,
20, 18, 17
40
Type
Description
O
Free-running CPU Clock: Output voltage swing is controlled by the voltage applied to
VDDQ2. See Tables 1 and 6 for detailed frequency information.
O
CPU Clock Output 1: This CPU clock output is controlled by the CLK_STOP# control
pin. Output voltage swing is controlled by voltage applied to VDDQ2.
O
PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3.
I/O
Fixed PCI Clock Output: As an output. frequency is set by the FS0:3 inputs or through
serial input interface, see Tables 1 and 6. This output is affected by the PCI_STOP# input.
When an input, latches data selecting the frequency of the CPU and PCI outputs.
I/O
Fixed PCI Clock Output: As an output, frequency is set by the FS0:3 inputs or through
serial input interface, see Tables 1 and 6. This output is not affected by the PCI_STOP#
input. When an input, sets function of pin 2.
I
CLK_STOP# input: When brought LOW, affected clock outputs are stopped LOW after
completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected clock
outputs start, beginning with a full clock cycle (2–3 CPU clock latency).
O
IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing
is controlled by VDDQ2. This output is disabled when CLK_STOP# is set LOW.
I/O
48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output
can be used as the reference for the Universal Serial Bus. Upon power-up FS0 input will
be latched, which will set clock frequencies as described in Table 1.
I/O
24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output
can be used as the clock input for a Super I/O chip. Upon power-up FS1 input will be
latched, which will set clock frequencies as described in Table 1.
I/O
I/O Dual-Function REF0 and FS2 pin: Upon power-up, FS2 input will be latched, which
will set clock frequencies as described in Table 1. When an output, this pin provides a
fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins.
I/O
Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin.
The PCI_STOP# input enables the PCI 1:5 outputs when HIGH and causes them to
remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F.
Its effects take place on the next PCI_F clock cycle. When an output, this pin provides a
fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins.
I
Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs
(SDRAM0:11, SDRAM_F).
O
Buffered Outputs: These twelve dedicated outputs provide copies of the signal provided
at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when
CLK_STOP# input is set LOW.
O
SCLK
SDATA
X1
24
23
4
I
I/O
I
X2
5
I
1, 6, 14,
19, 27, 30,
36
42, 48
P
VDDQ3
VDDQ2
GND
3, 9, 16,
22, 33, 39,
45
Document #: 38-07153 Rev. *B
P
G
Free-running Buffered Output: This dedicated output provides a copy of the SDRAMIN
input which is not affected by the CLK_STOP# input
Clock pin for I2C Circuitry
Data pin for I2C Circuitry
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an external
reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI
outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to 3.3V supply.
Power Connection: Power supply for IOAPIC, CPU_F, and CPU1 output buffers.
Connect to 2.5V or 3.3V.
Ground Connections: Connect all ground pins to the common system ground plane.
Page 2 of 14
W144
nation of assigned device functions. A short time after
power-up, the logic state of each pin is latched and the pins
become clock outputs. This feature reduces device pin count
by combining clock outputs with input select pins.
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3:..................................................................... 3.3V±5%
VDDQ2:..................................................................... 2.5V±5%
SDRAMIN to SDRAM0:11 Delay: ......................... 3.7 ns typ.
Upon W144 power up, the first 2 ms of operation is used for
input logic selection. During this period, the five I/O pins (7, 8,
25, 26, 46) are three-stated, allowing the output strapping
resistor on the l/O pins to pull the pin and their associated
capacitive clock load to either a logic HIGH or LOW state. At
the end of the 2ms period, the established logic “0” or “1”
condition of the l/O pin is latched. Next the output buffer is
enabled converting the l/O pins into operating clock outputs.
The 2-ms timer starts when VDD reaches 2.0V. The input bits
can only be reset by turning VDD off and then back on again.
SDRAM0:11 (leads) to SDRAM_F Skew: ............. 0.4 ns typ.
Table 2. Mode Input Table
Mode
Pin2
0
PCI_STOP#
1
REF0
Overview
The W144 was developed as a single-chip device to meet the
clocking needs of the Intel 440BX AGPset. In addition to the
typical outputs provided by standard 100-MHz 440BX FTGs,
the W144 adds a thirteen output buffer, supporting SDRAM
DIMM modules in conjunction with the chipset.
Cypress’s proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. When
enabled, this feature reduces the peak EMI measurements of
not only the output signals and their harmonics, but also of any
other clock signals that are properly synchronized to them.
Functional Description
I/O Pin Operation
Pins 7, 8, 25, 26, and 46 are dual-purpose l/O pins. Upon
power-up these pins act as logic inputs, allowing the determi-
It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive
impedance of clock outputs are <40Ω (nominal) which is
minimally affected by the 10-kΩ strap to ground or VDD. As
with the series termination resistor, the output strapping
resistor should be placed as close to the l/O pin as possible in
order to keep the interconnecting trace short. The trace from
the resistor to ground or VDD should be kept less than two
inches in length to prevent system noise coupling during input
logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that VDD has stabilized. If VDD has not yet reached
full value, output frequency initially may be below target but will
increase to target once VDD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
VDD
Output Strapping Resistor
10 kΩ
(Load Option 1)
Series Termination Resistor
Clock Load
W144
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
Q
10 kΩ
(Load Option 0)
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Document #: 38-07153 Rev. *B
Page 3 of 14
W144
Jumper Options
Output Strapping Resistor
VDD
10 k
W144
Series Termination Resistor
Ω
Power-on
Reset
Timer
Resistor Value R
Hold
Output
Low
Output Three-state
Q
Clock Load
R
Output
Buffer
D
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
Spread Spectrum Feature
Spread Spectrum clocking is activated or deactivated by
selecting the appropriate values for bits 1–0 in data byte 0 of
the I2C data stream. Refer to Table 7 for more details.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced.
This effect is depicted in Figure 3.
5dB/div
SSFTG
Amplitude (dB)
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
Typical Clock
dB = 6.5 + 9*log10(P) + 9*log10(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is specified in Table 7. Figure 4
details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
Frequency Span (MHz)
-SS%
+SS%
Figure 3. Clock Harmonic with and without SSCG
Modulation Frequency Domain Representation
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
FREQUENCY
MAX (+0.5%)
MIN (–0.5%)
Figure 4. Typical Modulation Profile
Document #: 38-07153 Rev. *B
Page 4 of 14
W144
Operation
Serial Data Interface
The W144 features a two-pin, serial data interface that can be
used to configure internal register settings that control
particular device functions. Upon power-up, the W144
initializes with default register settings, therefore the use of this
serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic
outputs of the chipset. Clock device register changes are
normally made upon system initialization, if any are required.
The interface can also be used during system operation for
power management functions. Table 3 summarizes the control
functions of the serial data interface.
Data is written to the W144 in eleven bytes of eight bits each.
Bytes are written in the order shown in Table 4.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock outputs
to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change under
normal system operation.
Spread Spectrum
Enabling
Enables or disables spread spectrum clocking.
For EMI reduction.
Output Three-state
Puts clock output into a high-impedance state.
Production PCB testing.
(Reserved)
Reserved function for future device revision or
production device testing.
No user application. Register bit must be
written as 0.
Table 4. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address
11010010
Commands the W144 to accept the bits in Data Bytes 0–6 for internal
register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W144 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
Command Code
Don’t Care
Unused by the W144, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
3
Byte Count
Don’t Care
Unused by the W144, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
Document #: 38-07153 Rev. *B
Page 5 of 14
W144
Table 4. Byte Writing Sequence (continued)
Byte
Sequence
Byte Name
4
Data Byte 0
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
11
Data Byte 7
Bit Sequence
Refer to Table 5
Byte Description
The data bits in Data Bytes 0–7 set internal W144 registers that control
device operation. The data bits are only accepted when the Address Byte
bit sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 5, Data Byte Serial Configuration Map.
Writing Data Bytes
Each bit in Data Bytes 0–7 controls a particular device function
except for the “reserved” bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Table 5. Data Bytes 0-7 Serial Configuration Map
Table 6 details additional frequency selections that are
available through the serial data interface.
Table 7 details the select functions for Byte 0, bits 1 and 0.
Affected Pin
Bit(s)
Pin No.
Bit Control
Pin Name
Control Function
0
1
Default
–
0
Data Byte 0
7
–
–
(Reserved)
6
–
–
SEL_2
–
See Table 6
0
5
–
–
SEL_1
See Table 6
0
4
–
–
SEL_0
See Table 6
0
3
–
–
Hardware/Software Frequency Select
2
–
–
SEL_3
1–0
–
–
Bit 1Bit 0Function (See Table 7 for function details)
00Normal Operation
01(Reserved)
10Spread Spectrum On
11All Outputs Three-stated
7
–
–
(Reserved)
–
–
0
6
–
–
(Reserved)
–
–
0
5
–
–
(Reserved)
–
–
0
4
–
–
(Reserved)
–
–
0
3
40
SDRAM_F
Low
Active
1
2
–
–
–
–
0
1
43
CPU1
Clock Output Disable
Low
Active
1
0
44
CPU_F
Clock Output Disable
Low
Active
1
Hardware
Software
See Table 6
0
0
00
Data Byte 1
Document #: 38-07153 Rev. *B
Clock Output Disable
(Reserved)
Page 6 of 14
W144
Data Byte 2
7
–
–
(Reserved)
6
7
PCI_F
5
–
–
4
13
PCI5
3
12
PCI4
Clock Output Disable
Low
Active
1
2
11
PCI3
Clock Output Disable
Low
Active
1
1
10
PCI2
Clock Output Disable
Low
Active
1
0
8
PCI1
Clock Output Disable
Low
Active
1
7
–
–
(Reserved)
–
–
0
6
–
–
(Reserved)
–
–
0
5
26
48MHz
Clock Output Disable
Low
Active
1
4
25
24MHz
Clock Output Disable
Low
Active
1
3
–
–
–
–
0
2
21, 20,
18, 17
SDRAM8:11
Clock Output Disable
Low
Active
1
1
32, 31,
29, 28
SDRAM4:7
Clock Output Disable
Low
Active
1
0
38, 37,
35, 34
SDRAM0:3
Clock Output Disable
Low
Active
1
Clock Output Disable
(Reserved)
Clock Output Disable
–
–
0
Low
Active
1
–
–
0
Low
Active
1
Data Byte 3
(Reserved)
Data Byte 4
7
–
–
(Reserved)
–
–
0
6
–
–
(Reserved)
–
–
0
5
–
–
(Reserved)
–
–
0
4
–
–
(Reserved)
–
–
0
3
–
–
(Reserved)
–
–
0
2
–
–
(Reserved)
–
–
0
1
–
–
(Reserved)
–
–
0
0
–
–
(Reserved)
–
–
0
7
–
–
(Reserved)
–
–
0
6
–
–
(Reserved)
–
–
0
(Reserved)
Data Byte 5
5
–
–
4
47
IOAPIC
3
–
–
(Reserved)
(Reserved)
Clock Output Disable
–
–
0
Low
Active
1
–
–
0
2
–
–
–
–
0
1
46
REF1
Clock Output Disable
Low
Active
1
0
2
REF0
Clock Output Disable
Low
Active
1
7
–
–
(Reserved)
–
–
0
6
–
–
(Reserved)
–
–
0
5
–
–
(Reserved)
–
–
0
4
–
–
(Reserved)
–
–
0
3
–
–
(Reserved)
–
–
0
Data Byte 6
Document #: 38-07153 Rev. *B
Page 7 of 14
W144
Data Byte 6 (continued)
2
–
–
(Reserved)
–
–
0
1
–
–
(Reserved)
–
–
0
0
–
–
(Reserved)
–
–
0
7
–
–
(Reserved)
–
–
0
6
–
–
(Reserved)
–
–
0
5
–
–
(Reserved)
–
–
0
4
–
–
(Reserved)
–
–
0
3
–
–
(Reserved)
–
–
0
2
–
–
(Reserved)
–
–
0
1
–
–
(Reserved)
–
–
0
0
–
–
(Reserved)
–
–
0
Data Byte 7
Table 6. Additional Frequency Selections through Serial Data Interface Data
Bytes[2]
Input Conditions
Output Frequency
Data Byte 0, Bit 3 = 1
Bit 2
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
CPU, SDRAM Clocks
(MHz)
PCI Clocks
(MHz)
1
1
1
1
133.6
33.4 (CPU/4)
1
1
1
0
124
31 (CPU/4)
1
1
0
1
150
37.5 (CPU/4)
1
1
0
0
140
35 (CPU/4)
1
0
1
1
105
35 (CPU/3)
1
0
1
0
110
36.7 (CPU/3)
1
0
0
1
115
39.3 (CPU/3)
1
0
0
0
120
40 (CPU/3)
0
1
1
1
100.2
33.4 (CPU/3)
0
1
1
0
133
44.3 (CPU/3)
0
1
0
1
112
37.3 (CPU/3)
0
1
0
0
103
34.3 (CPU/3)
0
0
1
1
66.8
33.4 (CPU/2)
0
0
1
0
83.3
41.7 (CPU/2)
0
0
0
1
75
37.5 (CPU/2)
0
0
0
0
124
41.3 (CPU/3)
Table 7. Select Function for Data Byte 0, Bits 0:1
Input Conditions
Data Byte 0
Output Conditions
Bit 1
Bit 0
CPU_F,
CPU1
PCI_F,
PCI1:5
REF0:1,
IOAPIC
48MHZ
24MHZ
Normal Operation
0
0
Note 1
Note 1
14.318 MHz
48 MHz
24 MHz
Spread Spectrum
1
0
±0.5%
±0.5%
14.318 MHz
48 MHz
24 MHz
Three-state
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Function
Note:
2. CPU and PCI frequency selections are listed in Table 1 and Table 6.
Document #: 38-07153 Rev. *B
Page 8 of 14
W144
Absolute Maximum Conditions[3]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
Parameter
rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Rating
Unit
VDD, VIN
Voltage on any pin with respect to GND
Description
–0.5 to +7.0
V
TSTG
Storage Temperature
–65 to +150
°C
TB
Ambient Temperature under Bias
–55 to +125
°C
TA
Operating Temperature
0 to +70
°C
ESDPROT
Input ESD Protection
2 (min)
kV
DC Electrical Characteristics TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD
3.3V Supply Current
CPU_F, CPU1 = 100.2 MHz
Outputs Loaded[4]
–
260
–
mA
IDD
2.5V Supply Current
CPU_F, CPU1 = 100.2 MHz
Outputs Loaded[4]
–
25
–
mA
Logic Inputs
VIL
Input Low Voltage
GND –
0.3
–
0.8
V
VIH
Input High Voltage
2.0
–
VDDQ3 +
0.3
V
IIL
Input Low Current[5]
–
–
–25
µA
IIH
Input High
Current[5]
–
–
10
µA
IIL
Input Low Current (SEL100/66#)
–
–
–5
µA
IIH
Input High Current (SEL100/66#)
–
–
+5
µA
Clock Outputs
VOL
Output Low Voltage
IOL = 1 mA
–
–
50
mV
VOH
Output High Voltage
IOH = 1 mA
3.1
–
–
V
VOH
Output High Voltage
CPU_F,1,
IOAPIC
IOH = –1 mA
2.2
–
–
V
IOL
Output Low Current
CPU_F, CPU1 VOL = 1.25V
27
57
97
mA
PCI_F, PCI1:5 VOL = 1.5V
20.5
53
139
mA
IOH
Output High Current
IOAPIC
VOL = 1.25V
40
85
140
mA
REF0:1
VOL = 1.5V
25
37
76
mA
48MHz
VOL = 1.5V
25
37
76
mA
24MHz
VOL = 1.5V
25
37
76
mA
CPU_F, CPU1 VOH = 1.25V
25
55
97
mA
PCI_F, PCI1:5 VOH = 1.5V
31
55
139
mA
IOAPIC
VOH = 1.25V
40
87
155
mA
REF0:1
VOH = 1.5V
27
44
94
mA
48MHz
VOH = 1.5V
27
44
94
mA
24MHz
VOH = 1.5V
25
37
76
mA
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. All clock outputs loaded with 6" 60Ω traces with 22-pF capacitors.
5. W144 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.
Document #: 38-07153 Rev. *B
Page 9 of 14
W144
DC Electrical Characteristics TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
–
1.65
–
V
–
14
–
pF
Pin X2 unconnected
–
28
–
pF
Except X1 and X2
–
–
5
pF
Crystal Oscillator
VTH
X1 Input threshold Voltage[6]
CLOAD
Load Capacitance, Imposed on
External Crystal[7]
CIN,X1
X1 Input Capacitance[8]
VDDQ3 = 3.3V
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
COUT
Output Pin Capacitance
–
–
6
pF
LIN
Input Pin Inductance
–
–
7
nH
AC Electrical Characteristics
TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%;
fXTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated
operating conditions using the stated lump capacitive load at
the clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU_F, CPU1 (Lump Capacitance Test Load = 20 pF)
CPU = 66.6 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
CPU = 100.2 MHz
Max. Min. Typ. Max. Unit
tP
Period
Measured on rising edge at 1.25
15
–
15.5
9.98
–
10.5
ns
tH
High Time
Duration of clock cycle above 2.0V
5.6
–
–
3.3
–
–
ns
tL
Low Time
Duration of clock cycle below 0.4V
5.3
–
–
3.1
–
–
ns
tR
Output Rise Edge Rate Measured from 0.4V to 2.0V
1.5
–
4
1.5
–
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1.5
–
4
1.5
–
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at
1.25V
45
–
55
45
–
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V.
Maximum difference of cycle time
between two adjacent cycles.
–
–
200
–
–
200
ps
tSK
Output Skew
Measured on rising edge at 1.25V
–
–
250
250
ps
fST
Frequency Stabilization Assumes full supply voltage reached
from Power-up (cold
within 1 ms from power-up. Short cycles
start)
exist prior to frequency stabilization.
–
–
3
–
–
3
ms
Zo
AC Output Impedance
–
20
–
–
20
–
Ω
Average value during switching
transition. Used for determining series
termination value.
Notes:
6. X1 input threshold voltage (typical) is VDDQ3/2.
7. The W144 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;
this includes typical stray capacitance of short PCB traces to crystal.
8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Document #: 38-07153 Rev. *B
Page 10 of 14
W144
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
CPU = 66.6 MHz
Parameter
Description
Test Condition/Comments
CPU = 100.2 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
tP
Period
Measured on rising edge at 1.5V
30
–
–
30
–
–
ns
tH
High Time
Duration of clock cycle above 2.4V,
at min. edge rate (1.5V/ns)
5.6
–
–
3.3
–
–
ns
tL
Low Time
Duration of clock cycle below 0.4V,
at min. edge rate (1.5V/ns
5.3
–
–
3.1
–
–
ns
tR
Output Rise Edge
Rate
Measured from 0.4V to 2.4V
1.5
–
4
1.5
–
4
V/ns
1.5
–
4
1.5
–
4
V/ns
1
–
5
1
–
5
ns
tF
Output Fall Edge Rate Measured from 2.4V to 0.4V
tPLH
Prop Delay LH
tPHL
Prop Delay HL
Input edge rate faster than 1 V/ns
1
–
5
1
–
5
ns
tD
Duty Cycle
Measured on rising and falling edge
at 1.5V,at min. edge rate (1.5 V/ns)
45
–
55
45
–
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V.
Maximum difference of cycle time
between two adjacent cycles.
–
–
250
–
–
250
ps
Input edge rate faster than 1V/ns
tSK
Output Skew
Measured on rising edge at 1.5V
–
–
250
–
–
250
ps
tO
CPU to PCI Clock
Skew
Covers all CPU/PCI outputs.
Measured on rising edge at 1.5V.
CPU leads PCI output.
1.5
–
4
1.5
–
4
ns
fST
Frequency
Stabilization from
Power-up (cold start)
Assumes full supply voltage
reached within 1 ms from power-up.
Short cycles exist prior to frequency
stabilization.
–
–
3
–
–
3
ms
Zo
AC Output
Impedance
Average value during switching
transition. Used for determining
series termination value.
–
30
–
–
30
–
Ω
PCI Clock Outputs, PCI_F and PCI1:5 (Lump Capacitance Test Load = 30 pF)
CPU = 66.6/100.2 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
tP
Period
Measured on rising edge at 1.5V
29.9
–
–
ns
tH
High Time
Duration of clock cycle above 2.4V
12.0
–
–
ns
tL
Low Time
Duration of clock cycle below 0.4V
12.0
–
–
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
–
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
–
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
–
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two
adjacent cycles.
–
–
250
ps
tSK
Output Skew
Measured on rising edge at 1.5V
–
–
500
ps
tO
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
1.5
–
4.0
ns
fST
Frequency Stabilization
Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior
to frequency stabilization.
–
–
3.0
ms
Zo
AC Output Impedance
–
30
–
Ω
Document #: 38-07153 Rev. *B
Average value during switching transition.
Used for determining series termination
value.
Page 11 of 14
W144
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100.2 MHz
Parameter
Description
Test Condition/Comments
Min.
f
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.0V
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
tD
Duty Cycle
Measured on rising and falling edge at 1.25V
45
fST
Frequency Stabilization
Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
–
Zo
AC Output Impedance
–
Average value during switching transition.
Used for determining series termination value.
Typ.
Max.
Unit
14.31818
1
MHz
–
4
V/ns
–
4
V/ns
–
55
%
–
1.5
ms
15
–
Ω
REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100.2 MHz
Parameter
Description
Test Condition/Comments
Min.
f
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization
from Power-up (cold
start)
Zo
AC Output Impedance
Typ.
Max.
14.318
Unit
MHz
–
2
V/ns
2
V/ns
45
–
55
%
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
–
–
3
ms
Average value during switching transition. Used for
determining series termination value.
–
40
–
Ω
–
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz
CPU = 66.6/100.2 MHz
Parameter
Description
Test Condition/Comments
Min.
Determined by PLL divider ratio (see p/q below)
Typ.
Max.
Unit
f
Frequency, Actual
fD
Deviation from 48 MHz (48.008 – 48)/48
p/q
PLL Ratio
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
0.5
–
2
V/ns
tF
Output Fall Edge Rate Measured from 2.4V to 0.4V
0.5
–
2
V/ns
tD
Duty Cycle
45
–
55
%
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
from Power-up (cold
power-up. Short cycles exist prior to frequency stabilistart)
zation.
–
–
3
ms
Zo
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
–
40
–
Ω
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured on rising and falling edge at 1.5V
–48.008–
MHz
+167
ppm
–57/17
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz
CPU = 66.6/100.2 MHz
Parameter
Description
Test Condition/Comments
Min.
Max.
Unit
Frequency, Actual
24.004
MHz
fD
p/q
Deviation from 24 MHz (24.004 – 24)/24
+167
ppm
PLL Ratio
57/34
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
0.5
–
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
–
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
–
55
%
Document #: 38-07153 Rev. *B
Determined by PLL divider ratio (see p/q below)
Typ.
f
(14.31818 MHz x 57/34 = 24.004 MHz)
Page 12 of 14
W144
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz (continued)
CPU = 66.6/100.2 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
from Power-up (cold
power-up. Short cycles exist prior to frequency stabilistart)
zation.
–
–
3
ms
Zo
AC Output Impedance
–
40
–
Ω
Average value during switching transition. Used for
determining series termination value.
Ordering Information
Ordering Code
Package Type
W144H
48-Pin SSOP (300-mil)
W144HT
48-Pin SSOP (300-mil) – Tape and Reel
Package Drawing and Dimension
48-Lead Shrunk Small Outline Package O48
51-85061-*C
Intel is a registered trademark of Intel Corporation. Purchase of I2C components from Cypress, or one of its sublicensed
Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as defined by Philips. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-07153 Rev. *B
Page 13 of 14
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W144
Document History PageDocument History Page
Document Title: W144 440BX AGPset Spread Spectrum Frequency Synthesizer
Document Number: 38-07153
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
110263
12/15/01
SZV
Change from Spec number: 38-00791 to 38-07153
*A
122800
12/14/02
RBI
Added Power-up Requirements to Operating Conditions information
*B
131400
01/20/04
RGL/TUJ
Document #: 38-07153 Rev. *B
Changed the frequency of FS(3:0), 1111 address(CPU_F,CPU1) from 133.3
MHz to 133.6 MHz, (PCI_F) from 33.3 MHz to 33.4 MHz in the
pin-selectable Frequency table and in Additional Frequency Selection
tables respectively.
Changed the frequency of FS(3:0), 0111 address(CPU_F,CPU1) from 100
MHz to 100.2 MHz, (PCI_F) from 33.3 MHz to 33.4 MHz in the Pin selectable
Frequency table and in Additional Frequency Selection tables respectively.
Changed the min. tP (period) parameter for 100.2 MHz frequency from 10.0
ns to 9.98 ns in the CPU Clock Outputs table.
hanged the min. tP (period) parameter for 100.2 MHz frequency from 30 ns
to 29.9 ns in the PCI Clock Outputs table.
Removed “PRELIMINARY”
Page 14 of 14