1W48C101-01 W48C101-01 Spread Spectrum BX System Frequency Generator Features CPU0:3 Clock Skew: ...................................................175 ps • Maximized EMI suppression using Cypress’s Spread Spectrum technology • Four copies of CPU output • Eight copies of PCI output (Synchronous w/CPU output) • Two copies of 14.318-MHz IOAPIC output • Two copies of 48-MHz USB output • Three buffered copies of 14.318-MHz reference input • Input is a 14.318-MHz XTAL or reference signal • Selectable 100-MHz or 66-MHz CPU outputs • Power management control input pins • Test mode and output three-state capability PCI_F, PCI1:7 Clock Skew: .........................................500 ps CPU to PCI Clock Skew: .............. 1.5 to 4.0 ns (CPU Leads) Logic inputs have 250-kΩ pull-up resistors except SEL100/66#. Table 1. Pin Selectable Frequency SEL 100/66# SEL1 SEL0 CPU PCI (MHz) (MHz) 0 0 0 HI-Z 0 0 1 0 1 0 0 1 1 1 0 0 Key Specifications 1 0 1 Supply Voltages: ....................................... VDDQ3 = 3.3V±5% VDDQ2 = 2.5V±5% 1 1 0 1 1 1 SPREAD#=0 HI-Z Don’t Care 66.6 33.3 ±0.9% Center 66.6 33.3 –1% Down 66.6 33.3 –0.5% Down X1/2 X1/6 Don’t Care 100 33.3 ±0.9% Center 100 33.3 –1% Down 100 33.3 –0.5% Down CPU0:3 Jitter (Cycle to Cycle): ................................... 200 ps Block Diagram Pin Configuration VDDQ3 REF0 X1 X2 REF1 XTAL OSC REF2 PLL Ref Freq VDDQ2 APIC0 APIC1 VDDQ2 CPU_STOP# CPU0 CPU1 Stop Clock Control SEL100/66# SEL0 SEL1 CPU2 PLL 1 CPU3 ÷2/÷3 REF0 REF1 GND X1 X2 GND PCI_F PCI1 VDDQ3 PCI2 PCI3 GND PCI4 PCI5 VDDQ3 PCI6 PCI7 GND VDDQ3 GND VDDQ3 48MHz 48MHz GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ3 REF2 VDDQ2 APIC0 APIC1 GND NC VDDQ2 CPU0 CPU1 GND VDDQ2 CPU2 CPU3 GND VDDQ3 GND PCI_STOP# CPU_STOP# PWR_DWN# SPREAD# SEL0 SEL1 SEL100/66# VDDQ3 SPREAD# PCI_F PCI1 Stop Clock Control PCI2 PCI3 PCI_STOP# PCI4 PCI5 PCI6 Power Down Control PWR_DWN# PCI7 VDDQ3 48MHz PLL2 48MHz Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 May 17, 2001, rev. *A W48C101-01 Pin Definitions Pin No. Pin Type CPU0:3 40, 39, 36, 35 O CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI1:7 8, 10, 11, 13, 14, 16, 17 O PCI Bus Clock Outputs 1 through 7: These seven PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. PCI_F 7 O Fixed PCI Clock Output: Unlike PCI1:7 outputs, this output is not controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. CPU_STOP# 30 I CPU_STOP# Input: When brought LOW, clock outputs CPU0:3 are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, clock outputs CPU0:3 start beginning with a full clock cycle (2–3 CPU clock latency). PCI_STOP# 31 I PCI_STOP# Input: The PCI_STOP# input enables the PCI 1:7 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle. SPREAD# 28 I SPREAD# Input: When brought LOW this pin activates Spread Spectrum clocking. APIC0:1 45, 44 O I/O APIC Clock Outputs: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. 48MHz 22, 23 O 48-MHz Outputs: Fixed clock outputs at 48 MHz. Output voltage swing is controlled by voltage applied to VDDQ3. REF0:2 1, 2, 47 O Fixed 14.318-MHz Outputs 0 through 2: Used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. 25, 26, 27 I Frequency Selection Input: Selects power-up default CPU clock frequency as shown in Table 1 on page 1. X1 4 I Crystal Connection or External Reference Frequency Input: Connect to either a 14.318-MHz crystal or reference signal. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. PWR_DWN# 29 I Power Down Control: When this input is LOW, device goes into a low-power condition. All outputs are held LOW while in power-down. CPU and PCI clock outputs are stopped LOW after completing a full clock cycle (2–3 CPU clock cycle latency). When brought HIGH, CPU, SDRAM and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). VDDQ3 9, 15, 19, 21, 33, 48 P Power Connection: Connect to 3.3V supply. VDDQ2 37,41,46 P Power Connection: Power supply for CPU0:3 and APIC0:1 output buffers. Connect to 2.5V supply. 3, 6, 12, 18, 20, 24, 32, 34, 38, 43 G Ground Connection: Connect all ground pins to the common system ground plane. 42 - No Connect: Do not connect. Pin Name SEL100/66# SEL1:0 GND NC Pin Description 2 W48C101-01 Spread Spectrum Clocking Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is –0.5%, –1.0%, or ±0.9% of the selected frequency. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for SPREAD#. Highest ∆ nonSSC SSC δ of f nom f nom Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MIN (–0.5%) Figure 2. Typical Modulation Profile 3 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX (+0.5%) W48C101-01 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient Temperature under Bias –55 to +125 °C ESDPROT Input ESD Protection 2 (min.) kV DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDDQ3 3.3V Supply Current CPU0:3 = 100 MHz Outputs Loaded[1] 120 mA IDDQ2 2.5V Supply Current CPU0:3 = 100 MHz Outputs Loaded[1] 65 mA Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 VDD + 0.3 V IIL Input Low Current[2] –25 µA IIH Input High Current[2] 10 µA IIL Input Low Current (SEL100/66#) –5 µA IIH Input High Current (SEL100/66#) 5 µA 50 mV Clock Outputs VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA 3.1 VOH Output High Voltage CPU0:3, APIC0:1 IOH = –1 mA 2.2 IOL Output Low Current CPU0:3 VOL = 1.25V 45 65 100 mA PCI_F, PCI1:7 VOL = 1.5V 70 100 145 mA APIC0:1 VOL = 1.25V 60 90 140 mA REF0:2 VOL = 1.5V 45 65 100 mA 48MHz VOL = 1.5V 45 65 100 mA CPU0:3 VOL = 1.25V 45 65 100 mA IOH Output High Current V V PCI_F, PCI1:7 VOL = 1.5V 65 95 135 mA APIC0:1 VOL = 1.25V 55 80 115 mA REF0:2 VOL = 1.5V 45 65 100 mA 48MHz VOL = 1.5V 45 65 100 mA Notes: 1. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors. 2. W48C101-01 logic inputs have internal pull-up devices, except SEL100/66# (pull-ups not full CMOS level). 4 W48C101-01 DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% (continued) Parameter Description Test Condition Min. Typ. Max. Unit Crystal Oscillator VTH CLOAD CIN,X1 X1 Input Threshold Voltage[3] Load Capacitance, as seen by External Crystal X1 Input Capacitance[5] [4] Pin X2 unconnected 1.65 V 14 pF 28 pF Pin Capacitance/Inductance CIN Input Pin Capacitance COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH Except X1 and X2 5 pF AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) CPU = 66.6 MHz Parameter Description Test Condition/Comments CPU = 100 MHz Min. Typ. Max. Min. Typ. Max. Unit tP Period tH High Time Duration of clock cycle above 2.0V 5.2 3.0 ns tL Low Time Duration of clock cycle below 0.4V 5.0 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 200 200 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Measured on rising edge at 1.25V 15 15.5 20 10 10.5 20 Notes: 3. X1 input threshold voltage (typical) is VDD/2. 4. The W48C101-01 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 5 ns Ω W48C101-01 PCI Clock Outputs, PCI1:7 and PCI_F (Lump Capacitance Test Load = 30 pF CPU = 66.6/100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 1.5 Ω 15 APIC0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100MHz Parameter Description Test Condition/Comments Min. Frequency generated by crystal oscillator Typ. Max. 14.31818 Unit f Frequency, Actual MHz tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 55 % 1.5 ms Ω 15 REF0:2 Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter Description Test Condition/Comments f Frequency, Actual Frequency generated by crystal oscillator Min. Typ. Max. 14.318 Unit MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 6 25 Ω W48C101-01 48-MHz Clock Outputs (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz) CPU = 66.6/100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) 48.008 MHz fD Deviation from 48 MHz m/n PLL Ratio (48.008 – 48)/48 +167 ppm (14.31818 MHz x 57/17 = 48.008 MHz) 57/17 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Ordering Information Ordering Code W48C101 Freq. Mask Code Package Name -01 H Package Type 48-pin SSOP (300 mils) Document #: 38-00852-*A 7 25 Ω W48C101-01 Package Diagram 48-Pin Small Shrink Outline Package (SSOP, 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.