IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE 1-TO-19 DIFFERENTIAL CLOCK BUFFER IDTCV145 DESCRIPTION: FEATURES: The CV145 differential buffer complies with Intel DB1900G , and is designed to work in conjunction with the main clock of CK409, CK410/CK410M and CK410B etc., PLL is off in bypass mode and no clock detect. • Compliant with Intel DB1900G • DIF Clock Support − 19 differential clock output pairs @ 0.7 V − 150 ps skew performance across all outputs • OE pin Control of All Outputs • 3.3 V Operation • Gear Ratio supporting generation of clocks at a different frequency ratioed from the input. • Split outputs supporting options of 2 outputs @1:1 and remaining 17 pairs at an alternate gear • Pin level OE control of individual outputs • Multiple output frequency options up to 400Mhz as a gear ratio of input clocks of 100-400Mhz • Output is HCSL compatible • SMBus Programmable configurations • PLL Bypass Configurable • SMBus address configurable to allow multiple buffer control in a single control network • Programmable Bandwidth • Glitchfree transition between frequency states • Available in 72-pin VFQPFN package FUNCTIONAL BLOCK DIAGRAM OE_17_18# DIF_0 DIF_0# OE[16:5]# Output Control OE_01234# DIF_1 DIF_1# DIF_2 PD# DIF_2# DIF_3 DIF_3# SCL Output Buffer SM Bus Controller SDA DIF_4 DIF_4# DIF_5 SA_2/PLL_BYPASS# DIF_5# DIF_6 CLK_IN DIF_6# CLK_IN# DIF_18 HIGH_BW# PLL DIF_18# The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE JUNE 2006 1 © 2005 Integrated Device Technology, Inc. DSC-6753/14 IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE SA_2/ PLL/ BYPASS# CLK_IN# CLK_IN OE_17_18# DIF_18# DIF_18 DIF_17# DIF_17 VSS VDD DIF_16# DIF_16 OE_16# DIF_15# DIF_15 OE_15# DIF_14# DIF_14 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 PIN CONFIGURATION IREF 1 54 OE_14# VSS 2 53 DIF_13# PD# 3 52 DIF_13 HIGH_BW# 4 51 OE_13# FSA 5 50 DIF_12# DIF_0 6 49 DIF_12 DIF_0# 7 48 OE_12# 8 47 VDD 46 VSS DIF_1 DIF_1# 9 VSS 10 45 DIF_11# VDD 11 44 DIF_11 DIF_2 12 43 OE_11# DIF_2# 13 42 DIF_10# DIF_3 14 41 DIF_10 DIF_3# 15 40 OE_10# DIF_4 16 39 DIF_9# DIF_9 OE_9# 28 29 30 31 32 33 34 35 36 VSS OE_7# DIF_7 DIF_7# OE_8# DIF_8 DIF_8# SA_0 SA_1 25 DIF_6 27 24 OE_6# VDD 23 DIF_5# 26 22 DIF_5 DIF_6# 21 OE_5# 37 20 18 SDA OE_01234# 19 17 SCL DIF_4# 38 VFQFPN TOP VIEW 2 IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Min. OE FUNCTIONALITY Max. Unit VDDA 3.3V Core Supply Voltage 4.6 V VDDIN 3.3V Logic Input Supply Voltage GND - 0.5 4.6 V TSTG Storage Temperature TAMBIENT Ambient Operating Temperature TCASE Case Temperature ESD Prot Input ESD Protection –65 +150 °C 0 +70 °C +115 °C 2000 OE# - Pin 0 0 1 1 V OE# - SMBus bit 1 0 1 0 DIF Normal Tristate Tristate Tristate DIFF]# Normal Tristate Tristate Tristate PD FUNCTIONALITY Human Body Model NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PD# / VDDA 3.3V (Nom) GND Inputs CLK_IN / CLK_IN# Running X Outputs DIF DIF# Running Hi-Z PLL State ON OFF PIN DESCRIPTION Pin Name Type Pin # Description CLK_IN, CLK_IN# IN 70, 71 DIF_[16:0] & DIF_[16:0]# OUT 6 - 9, 12 - 17, 22, 23, 25, 26, 30, 31, 33, 34, 38, 39, 41, 42, 44, 45, 49, 50, 52, 53, 55, 56, 58, 59, 61, 62 0.7v Differential input DIF & DIF# [18:17] OUT 65 - 68 0.7 V Differential clock outputs, which can be configured to be 1:1 instead of geared. Default is geared same as 0-9 outputs. OE_[16:5]# IN 21, 24, 29, 32, 37, 40, 43, 48, 51, 54, 57, 60 3.3 V LVTTL active LOW input for enabling corresponding differential output clock. Clocks also can be disabled via SMBus registers OE _17_18# IN 69 3.3 V LVTTL active low input for enabling both DIF10 and 11differential output clocks. Clocks also can be disabled via SMBus registers individually. OE_01234# IN 18 3.3V LVTTL input 0.7 V Differential clock outputs, geared to a ratio of the input clock HIGH_BW# IN 4 3.3 V LVTTL input for selecting the PLL bandwidth. 0 = HIGH BW, 1 = LOW BW. SCL IN 19 SMBus slave clock input SDA I/O, OC 20 Open collector SMBus data IREF IN 1 A precision resistor is attached to this pin to set the differential output current SA_[1:0] IN 35, 36 SA_2/PLL_BYPASS# IN 72 3.3 V LVTTL input for PLLbypass and SMBus address FS_A IN 5 3.3V LVTTL input to establish a HIGH (>200Mhz) or LOW frequency(<200Mhz) range PD# IN 3 3.3 V LVTTL input to power up or power down the device (see PD Functionality table). 3.3V LVTTL input selecting the address. SA_[2:0] set device SMBus address. 3 IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE INDEX BLOCK WRITE PROTOCOL Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master INDEX BLOCK READ PROTOCOL Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37). Description Start See SMBus Address Mode table Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N (0 is not valid) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 # of bits 1 8 1 8 1 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave 38 39-46 47 48-55 1 8 1 8 Master Slave Master Slave Master Slave Master INDEX BYTE READ INDEX BYTE WRITE Description Start See SMBus Address Mode table Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start See SMBus Address Mode table Ack (Acknowledge) Byte count, N (block read back of N bytes) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop Setting bit[11:18] = starting address. After reading back the first data byte, master issues Stop bit. Setting bit[11:18] = starting address, bit[20:27] = 01h. 4 IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE GEAR RATIOS Select FSA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SMBus3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SMBus2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SMBus1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SMBus0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5 m 3 5 12 2 5 8 3 4 6 1 5 4 3 2 3 1 3 5 12 2 5 8 3 5 6 1 5 4 3 2 3 1 n 1 2 5 1 3 5 2 3 5 1 6 5 4 3 5 2 1 2 5 1 3 5 2 4 5 1 6 5 4 3 5 2 Gear n/m 0.333 0.400 0.417 0.500 0.600 0.625 0.667 0.750 0.833 1.000 1.200 1.250 1.333 1.500 1.667 2.000 0.333 0.400 0.417 0.500 0.600 0.625 0.667 0.800 0.833 1.000 1.200 1.250 1.333 1.500 1.667 2.000 IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE TARGETED INPUT AND OUTPUT FREQUENCIES Input (MHz) 200 267 160 333 200 400 200 133 400 133 167 333 200 267 400 167 200 200 333 267 Output (MHz) 200 133 320 167 400 200 133 200 133 167 133 133 267 200 160 200 167 333 200 167 m:n 1:1 2:1 1:2 2:1 1:2 2:1 3:2 2:3 3:1 4:5 5:4 5:2 3:4 4:3 5:2 5:6 6:5 3:5 5:3 8:5 SMBUS ADDRESS MODE SELECTION SA_[2:0] 000 001 010 011 100 101 110 111 Buffer Address D0h (write) D1h (read) D2h, D3h D4h, D5h D6h, D7h D8h, D9h DAh, DBh DCh, DDh Deh, DFh FUNCTIONALITY AT POWER-UP(1) FSA 1 1 1 1 0 0 0 0 Targeted CLK_IN (CPU FSB) 100MHz 133MHz 166MHz RESERVED 200MHz 266.66MHz 333.33MHz 400MHz DIF[9:0] Output 100MHz 133MHz 166MHz RESERVED 200MHz 266.66MHz 333.33MHz 400MHz DIF[11:10] Output 100MHz 133MHz 166MHz RESERVED 200MHz 266.66MHz 333.33MHz 400MHz NOTE: 1. FSA is a low-threshold input. Please see the VIL_FS and VIH_FS specifications in the DC OPERATING CHARACTERISTICS table. 6 IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE CONTROL REGISTERS BYTE 0 Bit Output(s) Affected 7 Group of 17 gear # DIF [16:0] Speed selection Group of 2 gear # DIF [18:17] Speed selection Reserved FSA latched input SMBus3 SMBus2 SMBus1 SMBus0 6 5 4 3 2 1 0 Description/Function 0 1 Type Power On GR selection 1:1 = In RW 1 GR selection 1:1 = In RW 1 RW RW RW RW RW RW 1 BYTE 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 DIF_7 DIF_6 DIF_5 DIF_4 DIF_3 DIF_2 DIF_1 DIF_0 Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 Description/Function 0 1 Type Power On Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable HIGH BW Bypass Tristate Tristate Tristate Tristate Tristate Tristate LOW BW PLL Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 BYTE 2 Bit Output(s) Affected 7 6 5 4 3 2 1 0 PLL_BW# adjust BYPASS# test mode / PLL DIF_13 DIF_12 DIF_11 DIF_10 DIF_9 DIF_8 BYTE 3 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Readback - OE#_9 Input Readback - OE#_8 Input Readback - OE#_7 Input Readback - OE#_6 Input Readback - OE#_5 Input Readback - OE#_01234 Input Readback - HIGHBW# Input Readback - SA2/PLL/BYPASS# Input Description / Function Depends on the state of the pin Latch value of pin at power-up Latch value of pin at power-up 7 0 1 Type R R R R R R R R Power On IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE BYTE 4 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Readback - OE#_17_18 Input Readback - OE#_16 Input Readback - OE#_15 Input Readback - OE#_14 Input Readback - OE#_13 Input Readback - OE#_12 Input Readback - OE#_11 Input Readback - OE#_10 Input Description / Function 0 1 Type Power On R R R R R R R R Depends on the state of the pin BYTE 5 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Description / Function 0 1 Type Power On R R R R R R R R 0 0 0 0 0 1 0 1 1 Type Power On Enable Enable Enable Enable Enable R R R RW RW RW RW RW 1 1 1 1 1 Revision ID Revision ID Revision ID Revision ID Vendor ID Vendor ID Vendor ID Vendor ID BYTE 6 - DEVICE ID BYTE 7 - BYTE COUNT BYTE 8 Bit Output(s) Affected Description / Function 7 6 5 4 3 2 1 0 Readback - FSA Input Reserved Reserved DIF_18 DIF_17 DIF_16 DIF_15 DIF_14 Latch Value of pin at power-up Output Enable Output Enable Output Enable Output Enable Output Enable 0 Tristate Tristate Tristate Tristate Tristate 8 IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE DC OPERATING CHARACTERISTICS Following Conditions Apply Unless Otherwise Specified: Operating Condition: VDD/VDDA = 3.3V ± 5% Symbol Test Conditions Min. Typ. Max. Unit VDDA 3.3 V Core Supply Voltage 3.3 V ±5% 3.135 - 3.465 V VDD 3.3 V I/O Supply Voltage 3.3 V ±5% 3.135 - 3.465 V IDD 3.3 V Supply Current 3.3 V ±5%, 0 to 70C - 450 600 mA 3.3 V Power Down Supply Current 3.3 V ±5%, 0 to 70C - 20 36 mA Vdd 2.0 - Vdd+0.3 V Vss-0.3 - 0.8 -5 1.5 0 - 5 5 6 7 70 V µA IDDPD Parameter VIH 3.3 V Input High Voltage VIL 3.3 V Input Low Voltage IIL Cin Cout Lpin Ta Input Leakage Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Ambient Temperature 0 < Vin < Vdd No Airflow pF pF nH °C OUTPUT RELATIONAL TIMING PARAMETERS Group CLK_IN, DIF [x:0] CLK_IN, DIF [x:0] DIF DIF DIF Parameter Input to Output Skew in PLL mode (1:1 only) Input to Output Skew in non PLL mode (1:1 only) DIFF[x:0] Pin-to-Pin Skew (output within same group) DIFF[x:0] Pin-to-Pin Skew (across all outputs) Accumulated Differential Phase Jitter Min. -500ps 2.5ns 0ps 0ps -100ps PLL BANDWIDTH AND PEAKING Group DIF DIF DIF DIF DIF Parameter PLL Peaking (HIGH_BW# = 0) PLL Peaking (HIGH_BW# = 1) PLL Bandwidth (HIGH_BW# = 0) PLL Bandwidth (HIGH_BW# = 1) Output phase jitter impact (PCIe: including BW 1.5-22Mhz) Output phase jitter impact (FBD/CSI: including BW 11-33Mhz) Min. 0 0 2 0.7 Typ. 1 1 3.8 0.9 Max. 2.5 2 4 1.4 Unit dB dB MHz MHz - 99 108 - 3 3 ps ps Rms 9 Typ. 0 4 115 115 0 Max. +500ps 4.5ns 125ps 150ps +100ps IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE DIF TIMING CHARACTERISTICS (NON SSC CLOCK INPUT) DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode) Symbol Laccuracy Tperiod Tabsmin Trise Tfall ∆Trise ∆Tfall Rise/Fall Matching Vhigh Vlow Vcross absolute Total ∆ Vcross Tccjitter Tccjitter Tccjitter Duty Cycle Vovs Vuds Vrb Parameter Long Accuracy Average Period Absolute Minimum Host CLK Period Rise Time Fall Time Rise Time Variation Fall Time Variation Voltage HIGH (typ 0.7 Volts) Voltage LOW (typ 0 Volts) Absolute Crossing Point Voltages Total Variation of Vcross Over All Edges PLL Mode Cycle-to-Cycle Jitter Fin = 100, 166,67, 200, 266.67, 333.33 MHz PLL Mode Cycle-to-Cycle Jitter Fin = 133.33, 400.00 MHz Bypass Mode Cycle-to-Cycle Jitter (Additive) Maximum Voltage (Overshoot) Minimum Voltage (Undershoot) Ringback Voltage CLK - 100Mhz, 133.3Mhz, 166.6Mhz, 200Mhz, 233.3Mhz, 266.6Mhz, 333Mhz, 400Mhz Min. Typ. Max. 0 -0.30% 0.30% -2.50% 125 700 125 700 75 75 20% 660 850 -300 150 250 550 140 Unit ppm ns ns ps ps ps ps mV mV mV mV - - 50 ps - - 75 ps 45 0.2 - 50 55 Vh + 0.3V -0.3 N/A ps % Volt DIF TIMING CHARACTERISTICS (SSC CLOCK INPUT) DIF 0.7 V AC Timing Characteristics (-0.5% Spread Spectrum Mode) Symbol Laccuracy Tperiod Tabsmin Trise Tfall ∆Trise ∆Tfall Rise/Fall Matching Vhigh Vlow Vcross absolute Vcross relative Total ∆ Vcross Tccjitter Tccjitter Tccjitter Duty Cycle Vovs Vuds Vrb Parameter Long Accuracy Average Period Absolute Minimum Host CLK Period Rise Time Fall Time Rise Time Variation Fall Time Variation Voltage HIGH (typ 0.7 Volts) Voltage LOW (typ 0 Volts) Absolute Crossing Point Voltages Relative Crossing Point Voltages Total Variation of Vcross Over All Edges PLL Mode Cycle-to-Cycle Jitter Fin = 100, 166,67, 200, 266.67, 333.33 MHz PLL Mode Cycle-to-Cycle Jitter Fin = 133.33, 400.00 MHz Bypass Mode Cycle-to-Cycle Jitter (Additive) Maximum Voltage (Overshoot) Minimum Voltage (Undershoot) Ringback Voltage 10 CLK - 100Mhz, 133.3Mhz, 166.6Mhz, 200Mhz, 233.3Mhz, 266.6Mhz, 333Mhz, 400Mhz Min. Typ. Max. --0 -0.30% 0.53% (period - 0.125ns) 125 700 125 700 75 75 20% 660 850 -300 150 250 550 Calc Calc 140 Unit ppm ns ns ps ps ps ps mV mV mV mV - - 50 ps - - 75 ps 45 Vx ± 0.2 - 50 55 Vh + 0.3V -0.3 N/A ps % Volt IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE BUFFER POWER-UP STATE MACHINE(1) State State0 State1 State2 State3 Description Power off After 3.3V supply is detected to rise above 1.8-2V, the buffer enters state1 and initiates a 0.2ms-0.3ms delay.The total power up latency from power on to all outputs active must be less than 1ms (assume SRC_IN is available) Buffer waits for a valid clock on the SRC_IN input and PD de-assertion. Only after SRC_IN and power valid, PD de-asserted with the current mirror stable, or PLL lock, the DIF outputs are enabled NOTE: 1. The total power up latency from power on to all outputs active must be less than 1ms (assuming a valid clock is present on CLK_IN input). If power is valid and PWRDWN is de-asserted but no input clocks are present on the CLK_IN input, DIF clocks must remain disabled. Only after valid input clocks are detected, valid power, PWRDWN# de-asserted with the PLL locked/stable and the DIF outputs enabled (doesn't apply to bypass mode). BUFFER POWER-UP STATE DIAGRAM No Input Clock S2 S1 Wait for input clock and PWRDWN# de-assertion Delay >0.25 ms PWRDWN# Asserted S0 S3 Power Off Normal Operation 11 IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION XXX IDTCV Device Type XX Package X Grade CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 Blank Commercial Temperature Range (0°C to +70°C) NL NLG Very Fine Pitch Quad Flat Pack VFQFPN - Green 145 1-to-19 Differential Clock Buffer for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 12 for Tech Support: [email protected] IDTCV145 1-TO-19 DIFFERENTIAL CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE REVISION HISTORY JUNE 08, 2006 Updated Electrical Characteristics pages (9-10). 13