MoBL® Clock M200/M500 Two-PLL Programmable Clock Generator for Portable Applications Two-PLL Programmable Clock Generator for Portable Applications Features Benefits ■ Device Operating Voltage Options: ❐ MoBL Clock M200 Family: 1.8 V ❐ MoBL Clock M500 Family: 2.5 V, 3.0 V, or 3.3 V ■ Selectable clock output voltages for both MoBL Clock M200 and M500: ❐ 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V ■ Fully integrated ultra low power phase-locked loops (PLLs) ■ Input reference clock frequency range: 1–48 MHz ■ Output clock frequency range: 3–50 MHz I2C™ ■ Suitable for cell phone, portable, and consumer electronics applications ■ Multiple high-performance PLLs allow synthesis of unrelated frequencies ■ Application compatibility in multiple output voltage levels ■ Optional Spread Spectrum capable PLLs with Lexmark or Linear profile for maximum EMI reduction ■ PLLs can be programmed for system frequency margin tests ■ Meets critical timing requirements in complex system designs ■ Three programmable output clocks ■ Programmable output drive strengths ■ ■ 150 ps typical cycle-to-cycle jitter ■ ■ Optional Spread Spectrum for EMI reduction ■ 16-pin (3 × 3 × 0.6 mm) QFN Package ■ Industrial temperature range Individually enable or disable each output using I2C Ease of output clock selection using programmable crossbar switches Logic Block Diagram VDD_CLK1 EXCLKIN VDD_CLK2 REF SEL VDD_CLK3 CLK1 PLL1 Crossbar Switch Output Dividers and MUX and Control Logic PLL2 (SS) CLK2 Drive Strength Control CLK3 SCL SDA I2C PD#/OE Cypress Semiconductor Corporation Document Number: 001-29139 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 25, 2010 [+] Feedback MoBL® Clock M200/M500 Contents Pinouts .............................................................................. 3 MoBL Clock M200 ....................................................... 3 MoBL Clock M500 ....................................................... 4 General Description ......................................................... 5 2 Configurable PLLs .................................................... 5 I2C Programming ........................................................ 5 Input Reference Clocks ............................................... 5 Output Power Supply Options ..................................... 5 Output Source Selection ............................................. 5 Spread Spectrum Control ............................................ 5 PD#/OE Mode ............................................................. 5 Keep Alive Mode ......................................................... 5 Output Drive Strength .................................................. 5 Generic Configuration and Custom Frequency ........... 5 I2C Serial Interface ........................................................... 6 Device Address ........................................................... 6 Data Valid .................................................................... 6 Data Frame ................................................................. 6 Acknowledge Pulse ..................................................... 6 Write Operations ............................................................... 6 Writing Individual Bytes ............................................... 6 Writing Multiple Bytes .................................................. 6 Document Number: 001-29139 Rev. *C Read Operations ............................................................... 6 Current Address Read ................................................. 6 Random Read ............................................................. 6 Sequential Read .......................................................... 6 Serial Programming Interface Timing ............................. 8 Serial I2C Programming Interface Timing Specifications ...................................................... 8 Absolute Maximum Conditions ....................................... 9 Recommended Operating Conditions ............................ 9 DC Electrical Specifications .......................................... 10 AC Electrical Specifications .......................................... 11 Test and Measurement Setup ........................................ 12 Voltage and Timing Definitions ..................................... 12 Possible Configurations ............................................. 13 Ordering Code Definitions ......................................... 14 Package Drawing and Dimensions ............................... 14 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC Solutions ......................................................... 17 Page 2 of 17 [+] Feedback MoBL® Clock M200/M500 Pinouts MoBL Clock M200 16 VSS 1 CLK1 2 15 14 VSS CLK3 VDD EXCLKIN Figure 1. Pin Diagram - 16 LD QFN 13 MoBL Clock M200 12 DNU 11 VDD_CLK3 VDD_CLK2 16 LD QFN PD#/OE 4 9 VSS 5 6 7 8 VSS 10 SDA 3 SCL VDD_CLK1 CLK2 Table 1. Pin Definitions - MoBL Clock M200 Family (VDD = 1.8 V Supply) Pin Number Name IO Description 1 VSS Power GND 2 CLK1 Output Programmable Clock Output. Output voltage depends on VDD_CLK1 voltage 3 VDD_CLK1 Power Power Supply for CLK1: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V 4 PD#/OE Input 5 VSS Power 6 SCL Input I2C-Bus Clock Line 7 SDA Input/Output I2C-Bus Data Line Multifunction Programmable pin: Output Enable or Power Down Modes GND 8 VSS Power GND 9 CLK2 Output Programmable Clock Output. Output voltage depends on VDD_CLK2 voltage 10 VDD_CLK2 Power Power Supply for CLK2: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V 11 VDD_CLK3 Power Power Supply for output CLK3: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V 12 DNU DNU Do Not Use this pin 13 VSS Power GND 14 CLK3 Output Programmable Clock Output. Output voltage depends on VDD_CLK3 voltage 15 VDD Power Power Supply: 1.8 V 16 EXCLKIN Input 1.8 V external Reference Clock Document Number: 001-29139 Rev. *C Page 3 of 17 [+] Feedback MoBL® Clock M200/M500 MoBL Clock M500 VSS 1 CLK1 2 EXCLKIN VDD CLK3 VSS Figure 2. Pin Diagram - 16 LD QFN 16 15 14 13 MoBL Clock M500 12 DNU 11 VDD_CLK3 VDD_CLK2 16 LD QFN 10 PD#/OE 4 9 6 SCL VSS 5 7 8 VSS 3 SDA VDD_CLK1 CLK2 Table 2. Pin Definitions - MoBL Clock M500 Family (VDD = 2.5 V, 3.0 V or 3.3 V Supply) Pin Number Name IO 1 VSS Power GND Description 2 CLK1 Output Programmable Clock Output. Output voltage depends on VDD_CLK1 voltage 3 VDD_CLK1 Power Power Supply for CLK1: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V 4 PD#/OE Input Multifunction Programmable pin: Output Enable or Power Down Modes 5 VSS Power 6 SCL Input I2C-Bus Clock Line 7 SDA Input/Output I2C-Bus Data Line GND 8 VSS Power GND 9 CLK2 Output Programmable Clock Output. Output voltage depends on VDD_CLK2 voltage 10 VDD_CLK2 Power Power Supply for CLK2: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V 11 VDD_CLK3 Power 12 DNU DNU Power Supply for output CLK3: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V Do Not Use this pin 13 VSS Power GND 14 CLK3 Output Programmable Clock Output. Output voltage depends on VDD_CLK3 voltage 15 VDD Power Power Supply: 2.5 V/3.0 V/3.3 V 16 EXCLKIN Input 2.5 V/3.0 V/3.3 V external Reference Clock Document Number: 001-29139 Rev. *C Page 4 of 17 [+] Feedback MoBL® Clock M200/M500 General Description 2 Configurable PLLs The MoBL® Clock M200/M500 family of products are two-PLL clock generator ICs designed for cell phone, portable, or consumer electronics applications. It can be used to generate two independent output frequencies ranging from 3 to 50 MHz from a single input reference clock. I2C Programming The MoBL® Clock M200 and M500 have a serial I2C interface that programs the configuration memory array to synthesize output frequencies by programmable output divider, spread characteristics, and drive strength. I2C can also be used for in-system control of these programmable features. PD#/OE Mode PD#/OE input (Pin 4) can be programmed to operate as either power down (PD#) or output enable (OE) mode. Note that power down shuts off the entire chip, resulting in minimum power consumption for the device. Setting this signal high brings the device in the operational mode with default register settings. The PD# turn-on time is limited by the turn-on time of the PLLs. Disabled outputs are first driven to a low state before turning off. When off, they are held low by internal weak resistors (~160 kohms) When this pin is programmed as Output Enable (OE), clock outputs can be enabled or disabled using OE (pin 4). Individual clock outputs can be programmed to be sensitive to this OE pin. Keep Alive Mode The input to the M200 and M500 are designed to use an external reference clock with a frequency range of 1 MHz to 48 MHz at the EXCLKIN pin. The voltage level for the input reference clock used must follow VDD voltage used for the device as shown in the DC and AC specifications. By activating the device in the Keep Alive Mode, power down mode is changed to power saving mode, which disables all PLLs and outputs, but preserves the contents of the volatile registers. Thus, any configuration changes made via the I2C interface are preserved. By deactivating the Keep Alive Mode, I2C memory is not preserved during power down, but power consumption is reduced relative to the Keep Alive Mode. Output Power Supply Options Output Drive Strength There are three clock outputs CLK1, CLK2, and CLK3 driven by three separate output power supplies: VDD_CLK1, VDD_CLK2, and VDD_CLK3 respectively. Different voltage level for each of these power supplies can be used and they can be any of 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V giving user multiple choice of output clock voltage levels. The DC drive strength of the individual clock output can be programmed for different values. Table 3 shows the typical rise and fall times for different drive strength settings. Input Reference Clocks Output Source Selection These devices have three clock outputs, CLK1, CLK2 and CLK3. There are three available clock sources for these outputs. These clock sources are: PLL1, PLL2, or EXCLKIN. Output clock source selection is done using three out of three crossbar switch. Thus, any one of these three available clock sources can be arbitrarily selected for the clock outputs. This gives user a flexibility to have up to two independent clocks and a reference clock output. Spread Spectrum Control The PLL2 has spread spectrum capability for EMI reduction in the system. The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the PLL. The spread spectrum feature can be turned on or off by I2C device programming. It can be factory programmed to either center spread range from ±0.125% to ±2.50%, or down spread range from –0.25% to –5.0%, with Lexmark or Linear modulation profile. Document Number: 001-29139 Rev. *C Table 3. Output Drive Strength Output Drive Strength Rise/Fall Time (ns) (Typical Value) Low 6.8 Mid Low 3.4 Mid High 2.0 High 1.0 Generic Configuration and Custom Frequency The device is available with Factory Specific programmed frequencies as shown in the Ordering Information page. This factory specific programmed part can be used for the device evaluation purposes. The MoBL® Clock can be custom programmed to any desired frequencies and listed features. For customer specific programming and I2C programmable memory bitmap definitions, please contact local Cypress Field Application Engineer (FAE) or sales representative. Page 5 of 17 [+] Feedback MoBL® Clock M200/M500 I2C Serial Interface To enhance the flexibility and function of the clock synthesizer, a two-signal I2C serial interface is provided. This interface is used to write (and optionally read) control registers that control various device functions such as enabling individual clock output buffers. The registers initialize to their default setting upon power up and therefore, use of this interface is optional. Clock device registers are normally changed upon system initialization. Any data written via I2C is volatile and is not retained when the device is powered down. The I2C interface uses two signals, SDA and SCL, that operates up to 400 kbits/s in Read or Write mode. The SDA and SCL timing and data transfer sequence is shown in Figure 3 on page 7. The basic Write serial format is as follows: Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in MA+2; ACK; etc. until STOP Bit. The basic serial format is illustrated in Figure 4 on page 7. eight bits must contain the data word intended for storage. After the receiving the data word, the slave responds with another acknowledge bit (ack = 0/LOW), and the master must end the write sequence with a STOP condition. Writing Multiple Bytes To write multiple bytes at a time, the master must not end the write sequence with a STOP condition, but instead sends multiple contiguous bytes of data to be stored. After each byte, the slave responds with an acknowledge bit, the same as after the first byte, and accepts data until the acknowledge bit is responded to by the STOP condition. When receiving multiple bytes, the MoBL Clock M2xx/M5xx internally increments the register address. Read Operations Read operations are initiated the same way as Write operations except that the R/W bit of the slave address is set to ‘1’ (HIGH). There are three basic read operations: current address read, random read, and sequential read. Device Address Current Address Read The device serial interface address is 69H. The device address is combined with a read/write bit as the LSB and is sent after each start bit. The MoBL Clock M2xx/M5xx have an onboard address counter that retains ‘1’ more than the address of the last word accessed. If the last word written or read was word ‘n’, then a current address read operation returns the value stored in location ‘n+1’. When the MoBL Clock M2xx/M5xx receives the slave address with the R/W bit set to a ‘1’, it issues an acknowledge and transmits the 8-bit word. The master device does not acknowledge the transfer, but generates a STOP condition, which causes the MoBL Clock M2xx/M5xx to stop transmission. Data Valid Data is valid when the clock is HIGH, and can only be transitioned when the clock is LOW, as illustrated in Figure 5 on page 7. Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 6 on page 8. Start Sequence – SDA going LOW when SCL is HIGH indicates a Start Frame. Every time a start signal is supplied, the next 8-bit data must be the device address (seven bits) and a R/W bit, followed by register address (eight bits) and register data (eight bits). Stop Sequence – SDA going HIGH when SCL is HIGH indicates a Stop Frame. A Stop Frame frees the bus to write to another part on the same bus or to write to another random register address. Acknowledge Pulse During Write Mode, the MoBL Clock M2xx/M5xx responds with an Acknowledge pulse after every eight bits. This is done by pulling the SDA line LOW during the N*9th clock cycle, as illustrated in Figure 7 on page 8 (N = the number of bytes transmitted). During Read Mode, the master generates the acknowledge pulse after reading the data packet. Write Operations Writing Individual Bytes A valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from the slave (ack = 0/LOW). The next Document Number: 001-29139 Rev. *C Random Read Through random read operations, the master may access any memory location. To perform this type of read operation, first set the word address. To do this, send the address to the MoBL Clock M2xx/M5xx as part of a write operation. After the word address is sent, the master generates a START condition following the acknowledge. This terminates the write operation before any data is stored in the address, but not before the internal address pointer is set. Next, the master reissues the control byte with the R/W byte set to ‘1’. The MoBL Clock M2xx/M5xx then issues an acknowledge and transmits the 8-bit word. The master device does not acknowledge the transfer, but generates a STOP condition, which causes the MoBL Clock M200/M500 to stop transmission. Sequential Read Sequential read operations follow the same process as random reads except that the master issues an acknowledge instead of a STOP condition after transmission of the first 8-bit data word. This action increments the internal address pointer, and subsequently outputs the next 8-bit data word. By continuing to issue acknowledges instead of STOP conditions, the master serially reads the entire contents of the slave device memory. When the internal address pointer points to the FFH register, after the next increment, the pointer points to the 00H register. Page 6 of 17 [+] Feedback MoBL® Clock M200/M500 Figure 3. Data Transfer Sequence on the Serial Bus SCL SDA Address or Acknowledge Valid START Condition STOP Condition Data may be changed Figure 4. Data Frame Architecture SDA Write Multiple Contiguous Registers 1 Bit 1 Bit Slave R/W = 0 ACK 7-bit Device Address 1 Bit Slave ACK 8-bit Register Address (XXH) 1 Bit Slave ACK 8-bit Register Data (XXH) 1 Bit Slave ACK 8-bit Register Data (XXH+1) 1 Bit Slave ACK 8-bit Register Data (XXH+2) 1 Bit Slave ACK 8-bit Register Data (FFH) 1 Bit Slave ACK 8-bit Register Data (00H) Stop Signal Start Signal SDA Read Current Address Read Start Signal SDA Read Multiple Contiguous Registers 1 Bit Slave ACK 1 Bit 1 Bit Slave ACK R/W = 1 7-bit Device Address 1 Bit Slave ACK 1 Bit Master ACK 8-bit Register Data Stop Signal 1 Bit 1 Bit Slave ACK R/W = 0 7-bit Device Address 1 Bit Slave ACK 8-bit Register Address (XXH) 1 Bit Master ACK 7-bit Device Address +R/W=1 1 Bit Master ACK 8-bit Register Data (XXH) 1 Bit Master ACK 8-bit Register Data (XXH+1) 8-bit Register Data (FFH) 1 Bit Master ACK 1 Bit Master ACK 1 Bit Master ACK 8-bit Register Data (00H) Stop Signal Start Signal Repeated Start bit Figure 5. Data Valid and Data Transition Periods Data Valid Transition to next Bit SDA tDH VIH SCL Document Number: 001-29139 Rev. *C VIL tSU CLKHIGH CLKLOW Page 7 of 17 [+] Feedback MoBL® Clock M200/M500 Serial Programming Interface Timing Figure 6. Start and Stop Frame SDA Transition to next Bit START SCL STOP Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data) SDA + START DA6 SCL DA5 DA0 + R/W ACK RA7 RA6 RA1 + RA0 ACK + + D7 D6 D1 D0 ACK STOP + Serial I2C Programming Interface Timing Specifications Parameter fSCL Description Frequency of SCL Min Max Unit – 400 kHz Start Mode Time from SDA LOW to SCL LOW 0.6 – s CLKLOW SCL LOW Period 1.3 – s CLKHIGH SCL HIGH Period 0.6 – s tSU Data Transition to SCL HIGH 250 – ns tDH Data Hold (SCL LOW to data transition) 0 – ns Rise Time of SCL and SDA – 300 ns Fall Time of SCL and SDA – 300 ns Stop Mode Time from SCL HIGH to SDA HIGH 0.6 – s Stop Mode to Start Mode 1.3 – s Document Number: 001-29139 Rev. *C Page 8 of 17 [+] Feedback MoBL® Clock M200/M500 Absolute Maximum Conditions Parameter Description Condition Min Max Unit VDD Supply Voltage for MoBL Clock M5xx –0.5 4.4 V VDD Supply Voltage for MoBL Clock M2xx –0.5 2.8 V VDD_CLKX Supply Voltage for MoBL Clock M2xx/M5xx –0.5 4.4 V VIN Input Voltage for MoBL Clock M5xx Relative to VSS –0.5 VDD + 0.5 V VIN Input Voltage for MoBL Clock M2xx Relative to VSS –0.5 2.2 V TS Temperature, Storage Non Functional –65 +150 °C ESDHBM ESD Protection (Human Body Model) JEDEC EIA/JESD22-A114-E 2000 – V UL-94 Flammability Rating V-0 @1/8 in. 10 ppm MSL Moisture Sensitivity Level – 3 Recommended Operating Conditions The Recommended Operating Conditions table for MoBL Clock M2xx/M5xx family. Parameter Description Min Typ Max Unit VDD VDD Operating voltage for MoBL Clock M5xx 2.25 – 3.60 V VDD VDD Operating voltage for MoBL Clock M2xx 1.65 1.80 1.95 V VDD_CLKX Output Driver Voltage for MoBL Clock M2xx/M5xx 1.43 – 3.60 V TAI Industrial Ambient Temperature –40 – 85 °C CLOAD Maximum Load Capacitance – – 15 pF tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms Document Number: 001-29139 Rev. *C Page 9 of 17 [+] Feedback MoBL® Clock M200/M500 DC Electrical Specifications The DC Electrical Specification table for MoBL Clock M2xx/M5xx family (VDD_CLKX = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V). Parameter VOL Description Output Low Voltage Conditions IOL = 2 mA, drive strength = [00] Min Typ Max Unit – – 0.4 V VDD_CLKX – 0.4 – – V – – 0.4 V IOL = 3 mA, drive strength = [01] IOL = 7 mA, drive strength = [10] IOL = 12 mA, drive strength = [11] VOH Output High Voltage IOH = –2 mA, drive strength = [00] IOH = –3 mA, drive strength = [01] IOH = –7 mA, drive strength = [10] IOH = –12 mA, drive strength = [11] VOLSD Output Low Voltage, SDA IOL = 4 mA VIL1 Input Low Voltage of PD#/OE, SDA and SCL pins – – 0.2 × VDD V VIL2 Input Low Voltage of EXCLKIN pin – – 0.1 × VDD V VIH1 Input High Voltage of PD#/OE, SDA and SCL pins 0.8 × VDD – – V VIH2 Input High Voltage of EXCLKIN for MoBL Clock M5xx 0.9 × VDD – – V VIH3 Input High Voltage of EXCLKIN pin MoBL Clock M2xx 0.9 × VDD – 2.2 V IIH Input High Current, PD#/OE VIH = VDD – – 10 µA IIL Input Low Current, PD#/OE VIL = 0 V – – 10 µA RDN Pull Down Resistor of clocks (CLK1-CLK3) in off-state Clock outputs in off-state by setting PD# = Low 100 160 250 k IDD[1, 2] Supply Current All outputs running, CLOAD = 0 – 15 – mA IDDS[1] Standby Current PD# = Low, I2C circuit not in Keep Alive Mode – 3 – µA CIN[2] Input Capacitance SCL, SDA, and PD#/OE inputs – – 7 pF Notes 1. This parameter is configuration dependent. The specified value is for the drive level setting of [1,1]. 2. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. Document Number: 001-29139 Rev. *C Page 10 of 17 [+] Feedback MoBL® Clock M200/M500 AC Electrical Specifications The AC Electrical Specifications table for M2xx/M5xx (VDD_CLKX = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V) family. Parameter Description Conditions Min Typ Max Unit FCLK Clock Output Frequency All clock outputs 3 – 50 MHz FREF Driven Reference Frequency EXCLKIN Clock 1 – 48 MHz DC Output Clock Duty Cycle Duty Cycle as defined in Figure 9 on page 12 t1/t2, 50% of VDD_CLKX 45 50 55 % TRF1[4] Output Clock Rise/Fall Time Measured from 20% to 80% of VDD_CLKX, as shown in Figure 10 on page 12, CLOAD = 15 pF, drive strength [00] – 6.8 10.0 ns TRF2[4] Output Clock Rise/Fall Time Measured from 20% to 80% of VDD_CLKX, as shown in Figure 10 on page 12, CLOAD = 15 pF, drive strength [01] – 3.4 5.0 ns TRF3[4] Output Clock Rise/Fall Time Measured from 20% to 80% of VDD_CLKX, as shown in Figure 10 on page 12, CLOAD = 15 pF, drive strength [10] – 2.0 3.0 ns TRF4[4] Output Clock Rise/Fall Time Measured from 20% to 80% of VDD_CLKX, as shown in Figure 10 on page 12, CLOAD = 15 pF, drive strength [11] – 1.0 1.5 ns TCCJ[3, 4] Cycle-to-cycle Jitter EXCLKIN = CLKx = 48 MHz, CLOAD = 15 pF, 2 PLLs and 1 output for each PLL enabled, drive strength = [11] – 150 – ps TLOCK[4] PLL Lock Time – 1 3 ms Notes 3. This parameter is configuration dependent. The specified value is for the drive level setting of [1,1]. 4. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. Document Number: 001-29139 Rev. *C Page 11 of 17 [+] Feedback MoBL® Clock M200/M500 Test and Measurement Setup Figure 8. Test and Measurement Setup VDD 0 . 1 F Outputs CLOAD DUT GND Voltage and Timing Definitions Figure 9. Duty Cycle Definition t1 t2 VDD_CLKX 50% of V Clock Output DD_CLKX 0V Figure 10. Rise Time = TRF, Fall Time = TRF TRF TRF V DD_CLKX 80% of V Clock Output Document Number: 001-29139 Rev. *C DD_CLKX 20% of VDD_CLKX 0V Page 12 of 17 [+] Feedback MoBL® Clock M200/M500 Ordering Information Part Number [5] Frequency Configuration Other Programmable Features Package Production Flow Pb-Free M200LFXI Factory Generic Configuration With EXCLKIN = 19.2 MHz CLK1 = 48.0 MHz CLK2 = 27.0 MHz VDD = 1.8 V 16-pin QFN Industrial, –40 °C to 85 °C VDD_CLKx = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V Power Down = Enabled Keep Alive = Disabled Spread Spectrum = Disabled Output Drive Strength = [11] M200LFXIT Factory Generic Configuration With EXCLKIN = 19.2 MHz CLK1 = 48.0 MHz CLK2 = 27.0 MHz 16-pin QFN- Industrial, –40 °C to 85 °C VDD = 1.8 V VDD_CLKx = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V Tape & Reel Power Down = Enabled Keep Alive = Disabled Spread Spectrum = Disabled Output Drive Strength = [11] M500LFXI Factory Generic Configuration With EXCLKIN = 19.2 MHz CLK1 = 48.0 MHz CLK2 = 27.0 MHz VDD = 2.5 V/3.0 V/3.3 V 16-pin QFN Industrial, –40 °C to 85 °C VDD_CLKx = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V Power Down = Enabled Keep Alive = Disabled Spread Spectrum = Disabled Output Drive Strength = [11] M500LFXIT Factory Generic Configuration With EXCLKIN = 19.2 MHz CLK1 = 48.0 MHz CLK2 = 27.0 MHz 16-pin QFN- Industrial, –40 °C to 85 °C VDD = 2.5 V/3.0 V/3.3 V VDD_CLKx = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V Tape & Reel Power Down = Enabled Keep Alive = Disabled Spread Spectrum = Disabled Output Drive Strength = [11] All product offerings are factory programmed customer specific devices with customized part numbers. The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE of Sales Representative for more information. Possible Configurations Part Number [5] Frequency Configuration Other Programmable Features Package Production Flow M2xxLFXI Customer Specific Configuration VDD = 1.8 V 16-pin QFN Industrial, –40°C to 85°C VDD_CLKx = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V M2xxLFXIT Customer Specific Configuration VDD = 1.8 V 16-pin QFN- Industrial, –40°C to 85°C VDD_CLKx = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V Tape & Reel M5xxLFXI Customer Specific Configuration VDD = 2.5 V/3.0 V/3.3 V 16-pin QFN Industrial, –40°C to 85°C VDD_CLKx = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V M5xxLFXIT Customer Specific Configuration VDD = 2.5 V/3.0 V/3.3 V 16-pin QFN- Industrial, –40°C to 85°C VDD_CLKx = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V Tape & Reel Note 5. xx indicates factory programmed parts based on customer specific configuration. For more details, contact your local Cypress FAE or Sales Representative Document Number: 001-29139 Rev. *C Page 13 of 17 [+] Feedback MoBL® Clock M200/M500 Ordering Code Definitions MXXX LF X I T T = Tape and Reel; blank = Tube Temperature Range: I = industrial X = Pb-free package Package: 16-pin QFN Configuration: Factory Generic Configuration: MXXX = M200 / M500 Package Drawing and Dimensions Figure 11. 16-Lead Chip On Lead 3 × 3 mm QFN Package 001-09116 *E Document Number: 001-29139 Rev. *C Page 14 of 17 [+] Feedback MoBL® Clock M200/M500 Acronyms Acronym Description EMI electromagnetic interference FAE field application engineer OE output enable PLL phase locked loop QFN quad flat no leads Document Conventions Units of Measure Symbol °C Unit of Measure degree Celsius k kilo ohms kHz kilo Hertz MHz Mega Hertz µA micro Amperes mA milli Amperes ms milli seconds mm milli meter ns nano seconds ohms % percent pF pico Farads ppm parts per million ps pico seconds V volts Document Number: 001-29139 Rev. *C Page 15 of 17 [+] Feedback MoBL® Clock M200/M500 Document History Page Document Title: MoBL® Clock M200/M500 Two-PLL Programmable Clock Generator for Portable Applications Document Number: 001-29139 REV. ECN NO. Issue Date ** 1535744 See ECN *A 2748211 08/10/09 TSAI Posting to external web. *B 2899297 03/25/10 CXQ Moved ‘xx’ parts to Possible Configurations table. Updated Package Diagram *C 3095377 11/25/2010 BASH Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits and updated in new template. Document Number: 001-29139 Rev. *C Orig. of Change Description of Change RGL/AESA New Data Sheet Page 16 of 17 [+] Feedback MoBL® Clock M200/M500 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing PSoC cypress.com/go/image cypress.com/go/psoc Touch Sensing USB Controllers Wireless/RF cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2007-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-29139 Rev. *C 2 Revised November 25, 2010 Page 17 of 17 2 Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. MoBL is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback