DS4813 00

RT4813
High Efficiency Boost Converter
Features
General Description

The RT4813 allows systems to take advantage of new
battery chemistries that can supply significant energy
when the battery voltage is lower than the required
voltage for system power ICs. By combining built-in
power transistors, synchronous rectification, and low
supply current; this IC provides a compact solution for
systems using advanced Li-Ion battery chemistries.






The RT4813 is a boost regulator designed to provide a

minimum output voltage from a single-cell Li-Ion battery,
even when the battery voltage is below system
minimum. In boost mode, output voltage regulation is
guaranteed to a maximum load current of 3.1A.
Quiescent current in Shutdown Mode is less than 1A,
which maximizes battery life.

CMCOT Topology and Small Output Ripple when
VIN Close VOUT Voltage
Operates from a Single Li-ion Cell : 1.8V to 5.5V
Adjustable Output Voltage : 1.8V to 5.5V
PSM Operation
Up to 96% Efficiency
Input Over Current Limit
Input / Output Over Voltage Protection
Programmable Average Output Current Limit
Range : 3100mA to 1225mA
Internal Compensation

Output Discharge
Output Short Protection

True Load Disconnect

Applications
Ordering Information

RT4813

Package Type
QUF : UQFN-9L 2x2 (FC) (U-Type)
Single-Cell Li-Ion, LiFePO4 Smart-Phones
Portable Equipment
Marking Information
3V : Product Code
W : Date Code
Lead Plating System
G : Green (Halogen Free and Pb Free)
3VW
Note :
Richtek products are :

RoHS compliant and compatible with the current
requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering
processes.
Simplified Application Circuit
L1
VIN
RT4813
SW
C1
R1
R2
SCL
SDA
DS4813-00
April 2016
EN
EN
GND
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C3
FB
VIN
C2
I2C Control
VOUT
VOUT
R3
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RT4813
Pin Configurations
SCL
(TOP VIEW)
8
VIN
2
7
FB
SW
3
6
GND
PGND
4
5
SDA
EN
1
VOUT
9
UQFN-9L 2x2 (FC)
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
EN
Enable Input (1 enabled, 0 disabled), Must Not be Left Floating.
2
VOUT
Boost Converter Output.
3
SW
Switching Node.
4
PGND
Power Ground.
5
SDA
I2C Interface Data Input.
6
GND
Analog Ground.
7
FB
Voltage Feedback.
8
VIN
Power Input. Input capacitor CIN must be placed as close to IC as possible.
9
SCL
I2C Interface Clock Input.
Functional Block Diagram
VOUT
VIN
SDA
SCL
OCP
Gate
DRV
Digital
CTRL
PWM
CTRL
EN
SW
AMP
-
FB
+
OSC
OTP
PGND
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2
UVLO
VREF
GND
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RT4813
Operation
RT4813 combined built-in power transistors, synchronous
rectification, and low supply current, it provides a compact
solution for system using advanced Li-Ion battery
chemistries.
In boost mode, output voltage regulation is guaranteed to
a maximum load current of 3.1.A. Quiescent current in
Shutdown mode is less than 1A, which maximizes
battery life.
Mode
Startup and Shutdown State
When VIN is rising and through the LIN state, it will
enter the Startup state. If EN is pulled low, any function
is turned-off in shutdown mode.
Soft-Start State
It starts to switch in Soft-start state. After the LIN state,
output voltage is rising with the internal reference
voltage.
Depiction
Condition
LIN 1
Linear startup 1
VIN > VOUT
Fault State
LIN 2
Linear startup 2
VIN > VOUT
Soft-Start
Boost soft-start
VOUT < VOUT(MIN)
As the Figure 1 shown, it will enter to the Fault state as
below,
Boost
Boost mode
VOUT = VOUT(MIN)

LIN
The timeout of LIN2 is over the 1024s.
It will be the high impedance between the input and
LIN State
When VIN is rising, it enters the LIN State. There are
two parts for the LIN state. It provides maximum current
for 1A to charge the COUT in LIN1, and the other one is
for 2A in LIN2. By the way, the EN is pulled high and
VIN > UVLO.
As the figure shown, if the timeout is over the
specification, it will enter the Fault mode.
Timeout > 512μs
Timeout
< 1024μs
Boost
mode
The converter senses the current signal when the
high-side P-MOSFET turns on. As a result, the OCP is
cycle by-cycle current limitation. If the OCP occurs, the
converter holds off the next on pulse until inductor
OTP
LIN 1
Soft-Start
OCP
current drops below the OCP limit.
EN = 1,
Vin > UVLO
Timeout < 512μs
output when the fault is triggered. A restart will be start
after 20ms.
LIN 2
Timeout > 1024μs
The converter has an over-temperature protection.
When the junction temperature is higher than the
thermal shutdown rising threshold, the system will be
latched and the output voltage will no longer be
regulated until the junction temperature drops under
the falling threshold.
Fault
State
Figure 1. RT4813 State Chart
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RT4813
Absolute Maximum Ratings
(Note 1)

VIN, VINA to GND----------------------------------------------------------------------------------------------------- 0.2V to 6V

VOUT to GND ---------------------------------------------------------------------------------------------------------- 6V

Power Dissipation, PD @ TA = 25C
UQFN-9L 2x2 (FC) ---------------------------------------------------------------------------------------------------- 0.89W

Package Thermal Resistance
(Note 2)
UQFN-9L 2x2 (FC), JA ---------------------------------------------------------------------------------------------- 111.5C/W
UQFN-9L 2x2 (FC), JC---------------------------------------------------------------------------------------------- 19.6 C/W

Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260C

Junction Temperature ------------------------------------------------------------------------------------------------ 150C

Storage Temperature Range --------------------------------------------------------------------------------------- 65C to 150C

ESD Susceptibility
(Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Model) ------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 4)

Input Voltage Range -------------------------------------------------------------------------------------------------- 1.8V to 5.5V

Output Voltage Range ----------------------------------------------------------------------------------------------- 1.8V to 5.5V

Ambient Temperature Range--------------------------------------------------------------------------------------- 40C to 85C

Junction Temperature Range -------------------------------------------------------------------------------------- 40C to 125C
Electrical Characteristics
(VIN = 3.6V, TA = 25C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Under Voltage Lockout
Rising Threshold
VUVLOR
1.6
1.7
1.8
V
Under Voltage Lockout
Falling Threshold
VUVLOF
1.5
1.6
1.7
V
FB Voltage
VFB
CCM
0.495
0.5
0.505
V
VOUT Voltage (I2C)
VOUT
CCM
1
0
1
%
Shutdown Current
ISHDN
EN = 0V,
--
0.1
2
A
Close loop, no load
--
120
--
A
--
1
--
A
--
0.5
--
MHz
--
6
--
A
Quiescent Current
Pre-Charge Current
IPre
Switching Frequency
f SW
Valley Current Limit
IOC
VOUT  VIN > 1V, CCM
High Side Switch RON
VIN = VINA = 5V
--
43
55
m
Low Side Switch RON
VIN = VINA = 5V
--
26
35
m
FB Pin Input Leakage
IFB
1
--
1
A
Leakage of SW
ISW
--
--
5
A
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RT4813
Parameter
Symbol
Test Conditions
CCM, VIN = 2.7V to 4.5V,
VOUT = 5V, IOUT = 500mA
CCM, IOUT < 3.1A, VIN = 3.6V,
VOUT = 5V
Min
Typ
Max
Unit
--
0.5
--
%
--
0.5
--
%
Line Regulation
VOUT, LINE
Load Regulation
VOUT, LOAD
Output Over Voltage
Protection
VOVP
--
6
--
V
Low-Level
VIL
--
--
0.4
V
High-Level
VIH
1.2
--
--
V
--
0.1
1
A
TSD
--
160
C
TSD
--
30
C
EN Input
Voltage
EN Sink Current
Thermal Shutdown
Thermal Shutdown
Hysteresis
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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RT4813
Typical Application Circuit
L1
VIN
RT4813
3
SW
VOUT
C1
22μF x 2
8 VIN
C2
1μF
FB
2
7
R1
909k
C3
22μF x 2
R2
100k
VIN
R4
10k
R5
10k
2
I C control
9
5
EN
SCL
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1
EN
R3
1M
SDA
GND
6
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VOUT
PGND
4
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RT4813
Typical Operating Characteristics
Efficiency vs. Output Curent
Output Voltage Ripple
100
90
VIN = 4.2V
Efficiency (%)
80
VIN = 3.7V
70
VIN = 3.3V
60
VIN = 2.5V
50
LX
(2V/Div)
VIN = 1.8V
40
VOUT_ac
(50mV/Div)
30
20
VOUT = 5V, L = 1.5μH (TDK SPM6530),
10
VIN = 2.5V, VOUT = 5V, IOUT = 0mA
L = 1.5H (TDK SPM6530), COUT = 22F x 2
COUT = 22μF x 2, Load = 1mA to 3A
0
0
500
1000
1500
2000
2500
3000
Time (10s/Div)
Output Current (mA)
Output Voltage Ripple
Output Voltage Ripple
LX
(2V/Div)
LX
(2V/Div)
VOUT_ac
(50mV/Div)
VOUT_ac
(50mV/Div)
VIN = 3.6V, VOUT = 5V, IOUT = 0mA
L = 1.5H (TDK SPM6530), COUT = 22F x 2
VIN = 4.2V, VOUT = 5V, IOUT = 0mA
L = 1.5H (TDK SPM6530), COUT = 22F x 2
Time (10s/Div)
Time (10s/Div)
Output Voltage Ripple
Output Voltage Ripple
VIN = 2.5V, VOUT = 5V, IOUT = 1000mA
LX
(2V/Div)
VIN = 3.6V, VOUT = 5V, IOUT = 1000mA
L = 1.5H (TDK SPM6530), COUT = 22F x 2
LX
(2V/Div)
VOUT_ac
(20mV/Div)
VOUT_ac
(20mV/Div)
L = 1.5H (TDK SPM6530), COUT = 22F x 2
Time (1s/Div)
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RT4813
Load Transient Response
Output Voltage Ripple
VIN = 4.2V, VOUT = 5V, IOUT = 1000mA
L = 1.5H (TDK SPM6530), COUT = 22F x 2
LX
(2V/Div)
VIN = 2.5V, VOUT = 5V, IOUT = 1.5A to 3A
L = 1.5H (TDK SPM6530), COUT = 22F x 2
IOUT
(1A/Div)
VOUT_ac
(20mV/Div)
VOUT_ac
(500mV/Div)
Slew rate = 100mA/μs
Time (1s/Div)
Time (250s/Div)
Load Transient Response
Load Transient Response
VIN = 4.2V, VOUT = 5V, IOUT = 1.5A to 3A
L = 1.5H (TDK SPM6530), COUT = 22F x 2
VIN = 3.7V, VOUT = 5V, IOUT = 1.5A to 3A
L = 1.5H (TDK SPM6530), COUT = 22F x 2
IOUT
(1A/Div)
IOUT
(1A/Div)
VOUT_ac
(500mV/Div)
VOUT_ac
(500mV/Diiv)
Slew rate = 100mA/μs
Slew rate = 100mA/μs
Time (250s/Div)
Time (250s/Div)
Load Transient Response
Load Transient Response
VIN = 2.5V, VOUT = 5V, IOUT = 50mA to 150mA
L = 1.5H, COUT = 22F x 2
VIN = 3.7V, VOUT = 5V, IOUT = 50mA to 150mA
L = 1.5H, COUT = 22F x 2
IOUT
(1A/Div)
IOUT
(1A/Div)
VOUT_ac
(500mV/Diiv)
VOUT_ac
(500mV/Diiv)
Slew rate = 5mA/μs
Time (250s/Div)
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Slew rate = 5mA/μs
Time (250s/Div)
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RT4813
Load Transient Response
VIN = 4.2V, VOUT = 5V, IOUT = 50mA to 150mA
L = 1.5H, COUT = 22F x 2
IOUT
(1A/Div)
VOUT_ac
(500mV/Diiv)
Slew rate = 5mA/μs
Time (250s/Div)
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RT4813
I2C Interface
RT4813 I2C slave address = 0111001 (7 bits). I2C interface supports fast mode (bit rate up to 400kb/s). The write or
read bit stream (N ≥ 1) is shown below :
Read N bytes from RT4813
Slave Address
Register Address
S
0
A
R/W
Slave Address
MSB
A Sr
1
Data 2
A
Data for Address = m
LSB
MSB
Data N
LSB
A
A
Register Address
S
0
A
R/W
MSB
Data 1
LSB
A
Assume Address = m
P
Data for Address = m + N - 1
Data for Address = m + 1
Write N bytes to RT4813
Slave Address
LSB
A
Assume Address = m
MSB
Data 1
MSB
Data 2
LSB
A
Data for Address = m
MSB
A
Data for Address = m + 1
Data N
LSB
A P
Data for Address = m + N - 1
Driven by Master,
Driven by Slave (RT4813),
P Stop,
S Start,
Sr Repeat Start
I2C Waveform Information
SDA
tLOW
tF
tSU,DAT
tR
tF
tHD,STA
tR
tSP
tBUF
SCL
tHD,STA
S
tHD,DAT
tHIGH
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tSU,STA
tSU,STO
Sr
P
S
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RT4813
I2C Register
Function Register Address
Meaning
Config
0X01
b[6]
b[5]
Reversed ILIM_OFF
b[4]
b[3]
IPCHG
b[2]
b[0]
(LSB)
b[1]
DRV_SEL<2:0>
SSFM
Default
0
0
0
1
1
1
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
b[3]
b[2]
b[1]
b[0]
(LSB)
ILIM_OFF
IPCHG
DRV_SEL<2:0>
SSFM
Function Register Address
Charger
0X03
Control 3
b[7]
(MSB)
Meaning
Default
Read/Write
ILIM_SS<7:4>
Boost valley current limit setting
0 : Boost current limit enable (default)
1 : Boost current limit disable
Pre-charge current setting.
00 : 0.5A
01 : 1A (default)
10 : 1.5A
11 : 2A
LG driver driving capability
000 : Slowest
:
:
111 : Fastest (default)
Spread spectrum setting.
0 : Spread spectrum disable (default)
1 : Spread spectrum enable
b[7]
(MSB)
b[6]
b[5]
b[4]
ILIM_SS<7:4>
ILIM_AVG<3:0>
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Soft-start period boost current limit setting. The default current is 1500mA.
Code
Current
Code
Current Code Current
Code
Current
1500mA
0000
0100
1500mA 1000 2500mA 1100
4500mA
(default)
0001
1500mA
0101
1500mA 1001 3000mA 1101
5000mA
0010
1500mA
0110
1500mA
1010
3500mA
1110
5500mA
0011
1500mA
0111
2000mA
1011
4000mA
1111
6000mA
Average Output Current limit setting. The default current is 3000mA.
Code
ILIM_AVG<3:0>
Code
Current
Code
Current
Code
Current
0100
2420mA
1000
1740mA
1100
1060mA
0001
Current
3100mA
(Default)
2930mA
0101
2250mA
1001
1570mA
1101
890mA
0010
2760mA
0110
2080mA
1010
1400mA
1110
720mA
0011
2590mA
0111
1910mA
1011
1230mA
1111
550mA
0000
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RT4813
Function Register Address
Meaning
OPTION 0X04
Default
Read/Write
FSW
EN_IAVGCL
EN_Discharge
b[7]
(MSB)
b[6]
b[4]
b[3]
Reversed Reversed Reversed Reversed
0
0
0
0
R/W
R/W
R/W
R/W
Boost frequency setting.
00 : 2MHz
01 : Do not allowed
10 : 1MHz
11 : 500kHz (default)
Enable average output current limit
0 : Disable
1 : Enable (default)
Enable discharge
0 : Disable
1 : Enable (default)
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b[5]
b[2]
b[0]
(LSB)
b[1]
EN
EN
_IAVGCL _Discharge
FSW
1
1
1
1
R/W
R/W
R/W
R/W
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RT4813
Application Information
Enable
Power Save Mode
The device can be enabled or disabled by the EN pin.
When the EN pin is higher than the threshold of
logic-high, the device starts operating with soft-start.
Once the EN pin is set at low, the device will be shut
down. In shutdown mode, the converter stops
switching, internal control circuitry is turned off, and
the load is disconnected from the input. This also
means that the output voltage can drop below the
input voltage during shutdown.
PSM is the way to improve efficiency at light load.
Soft-Start State
After the successful completion of the LIN state (VOUT
≥ VIN  300mV), the regulator begins switching with
boost valley-current limited value 3500mA.
When the output voltage is lower than a set threshold
voltage, the converter will operate in PSM.
It raises the output voltage with several pulses until
the loop exits PSM.
Under-Voltage Lockout
The under-voltage lockout circuit prevents the device
from operating incorrectly at low input voltages. It
prevents the converter from turning on the power
switches under undefined conditions and prevents the
battery from deep discharge. VIN voltage must be
greater than 1.65V to enable the converter. During
During Soft-Start state, VOUT is ramped up by Boost
internal loop. If VOUT fails to reach target value during
the Soft-Start period for more than 2ms, a fault
condition is declared.
operation, if VIN voltage drops below 1.55V, the
converter is disabled until the supply exceeds the
UVLO rising threshold. The RT4813 automatically
restarts if the input voltage recovers to the input
voltage UVLO high level.
Output Voltage Setting
Thermal Shutdown
The output voltage is adjustable by an external
resistive divider. The resistive divider must be
connected between VOUT, FB and GND. When the
output voltage is regulated properly, the typical value
of the voltage at the FB pin is 500mV. Output voltage
can be calculated by equation as below :
The device has a built-in temperature sensor which
monitors the internal junction temperature. If the
V

R1  R2   OUT  1
V
 FB

designed to avoid unstable operation at IC
temperatures near the over temperature threshold.
temperature exceeds the threshold, the device stops
operating. As soon as the IC temperature has
decreased below the threshold with a hysteresis, it
starts operating again. The built-in hysteresis is
Inductor Selection
The recommended nominal inductance value is
1.5H
It is recommended to use inductor with dc saturation
current ≥ 5000mA
Table 1. List of Inductors
Manufacturer
Series
Dimensions (in mm)
Saturation Current (mA)
TDK
SPM6530T
7.1 x 6.5 x 3.0
11500
Taiyo Yuden
NRS5040T
5.15 x 5.15 x 4.2
6400
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RT4813
Input Capacitor Selection
Output Discharge Function
At least two capacitor and capacitance is 22F with
rating voltage is 16V for DC bias input capacitor is
recommended to improve transient behavior of the
regulator and EMI behavior of the total power supply
circuit for LX. And at least a 1F ceramic capacitor
placed as close as possible to the VIN and GND pins
With the EN pin set to low, the VOUT pin is internally
connected to GND for 10ms by an internal discharge
N-MOSFET switch. After the 10ms, IC will be
true-shut down.
of the IC is recommended.
proper power up of the system.
Output Capacitor Selection
Valley Current Limit
At least 22F x 2 capacitors is recommended to
improve VOUT ripple.
RT4813 employs a valley-current limit detection
scheme to sense inductor current during the off-time.
When the loading current is increased such that the
loading is above the valley current limit threshold, the
off-time is increased until the current is decreased to
valley-current threshold. Next on-time begins after
current is decreased to valley-current threshold.
On-time is decided by (VOUT VIN) / VOUT ratio. The
Output voltage ripple is inversely proportional to
COUT.
Output capacitor is selected according to output ripple
which is calculated as :
VRIPPLE(P P)  tON 
ILOAD
COUT
This feature prevents residual charge voltages on
capacitor connected to VOUT pins, which may impact
output voltage decreases when further loading
current increase. The current limit function is
and

V 
tON  tSW  D  tSW   1  IN 
V
OUT 

therefore :
implemented by the scheme, refer to Figure 2.

V
COUT  tSW   1  IN
V
OUT

and
RT4813 features the average output current limit to
protect the output terminal. When the load current is
over the limit, output current will be clamped.
tSW 
Average Output Current Limit

ILOAD

V
RIPPLE(P P)

1
fSW
The maximum VRIPPLE occurs at minimum input
voltage and maximum output load.
IIN (DC)
Valley Current Limit
f
Inductor Current
IL
IL =
IIN (DC)
VIN D

L
f
Figure 2. Inductor Currents In Current Limit Operation
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
is a registered trademark of Richtek Technology Corporation.
DS4813-00
April 2016
RT4813
Thermal Considerations
Layout Consideration
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
The PCB layout is an important step to maintain the
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature.
The maximum power dissipation can be calculated by
the following formula :
PD(MAX) = (TJ(MAX)  TA) / JA
high performance of RT4813.
Both the high current and the fast switching nodes
demand full attention to the PCB layout to save the
robustness of the RT4813 through the PCB layout.
Improper layout might show the symptoms of poor line
or load regulation, ground and output voltage shifts,
where TJ(MAX) is the maximum junction temperature,
TA is the ambient temperature, and JA is the junction to
ambient thermal resistance.
stability issues, unsatisfying EMI behavior or worsened
efficiency. For the best performance of the RT4813, the
following PCB layout guidelines must be strictly
followed.
For recommended operating condition specifications,

dependent. For UQFN-9L 2x2 (FC) package, the
thermal resistance, JA, is 111.5C/W on a standard
JEDEC 51-7 four-layer thermal test board. The
maximum power dissipation at TA = 25C can be
calculated by the following formula :
Input/Output capacitors must be placed as close as
possible to the Input/Output pins.

SW should be connected to Inductor by wide and
short trace, keep sensitive components away from
this trace.

The feedback divider should be placed as close as
possible to the FB pin.
PD(MAX) = (125C  25C) / (111.5C/W) = 0.89W for
UQFN-9L 2x2 (FC) package
thermal resistance, JA. The derating curve in Figure 3
allows the designer to see the effect of rising ambient
GND
GND
Cin
The maximum power dissipation depends on the
operating ambient temperature for fixed TJ(MAX) and
temperature on the maximum power dissipation.
Cout
Maximum Power Dissipation (W)1
1.0
L
Four-Layer PCB
0.9
Cout
0.8
Vout
0.7
Cin
the maximum junction temperature is 125C. The
junction to ambient thermal resistance, JA, is layout
Vin
0.6
0.5
Figure 4. PCB Layout Guide
0.4
0.3
0.2
0.1
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 3. Derating Curve of Maximum Power
Dissipation
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS4813-00
April 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT4813
Outline Dimension
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min.
Max.
Min.
Max.
A
0.500
0.600
0.020
0.024
A1
0.000
0.050
0.000
0.002
A3
0.100
0.175
0.004
0.007
b
0.130
0.230
0.005
0.009
b1
0.200
0.300
0.008
0.012
D
1.950
2.050
0.077
0.081
E
1.950
2.050
0.077
0.081
e
0.500
0.020
L
0.350
0.450
0.014
0.018
L1
1.250
1.350
0.049
0.053
U-Type 9L QFN 2x2 (FC) Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and
reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
www.richtek.com
16
is a registered trademark of Richtek Technology Corporation.
DS4813-00
April 2016