Datasheet

THC63LVDF84C_Rev.1.20_E
THC63LVDF84C
24bit Color LVDS Receiver (Falling Edge Strobe Output)
General Description
Features
The THC63LVDF84C receiver supports wide
temperature range as -40 to +85C, and wide
frequency range as 8 to 112MHz.
The THC63LVDF84C converts the four LVDS data
streams back into 24bits of LVCMOS data with
falling edge clock. At a transmit clock frequency of
112MHz, 24bits of RGB data and 4bits of timing and
control data (HSYNC, VSYNC, DE, etc.) are
transmitted at an effective rate of 3.1Gbps.
･1:7 LVDS to LVCMOS Deserializer
･Operating Temperature Range : -40 to +85C
･No Special Start-up Sequence Required
･Spread Spectrum Clocking Tolerant up to 100kHz
Frequency Modulation and +/-2.5% Deviations
･Pixel Clock Range: 8 to 112MHz
･56pin TSSOP Package
･Power Down Mode
･Falling Edge Strobe Output
･EU RoHS Compliant
Application
･Medium and Small Size Panel
･Security Camera
･Multi Function Printer
･Machine Vision (Frame Grabber Board)
･Medical Equipment Monitor
Recommended LVDS Transmitter ICs
･THC63LVDM83D
･THC63LVDM87
Block Diagram
THC63LVDF84C
RB +/LVDS Inputs
(56 to 784Mbps/ch) RC +/RD +/-
RCLK +/(8 to 112MHz)
7
LVDS to LVCMOS
1:7 Deserializer
RA +/-
PLL
7
7
7
RA0-6
RB0-6
LVCMOS Outputs
RC0-6
RD0-6
CLKOUT
(8 to 112MHz)
/PDWN
Figure 1. Block Diagram
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Pin Diagram
RC3
RD6
RC4
GND
RC5
RC6
RD0
LVDS GND
RARA+
RBRB+
LVDS VCC
LVDS GND
RCRC+
RCLKRCLK+
RDRD+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLKOUT
RA0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VCC
RC2
RC1
RC0
GND
RB6
RD5
RD4
VCC
RB5
RB4
RB3
GND
RB2
RD3
RD2
VCC
RB1
RB0
RA6
GND
RA5
RD1
RA4
RA3
VCC
RA2
RA1
Figure 2. Pin Diagram
Pin Description
Pin Name
RA+, RARB+, RBRC+, RCRD+, RD-
Pin #
10, 9
12, 11
16, 15
20, 19
Direction
Type
Description
LVDS Data Inputs
Input
RCLK+,
RCLK-
18, 17
RA0 ~ RA6
RB0 ~ RB6
RC0 ~ RC6
RD0 ~ RD6
CLKOUT
27, 29, 30, 32, 33, 35, 37
38, 39, 43, 45, 46, 47, 51
53, 54, 55, 1, 3, 5, 6
7, 34, 41, 42, 49, 50, 2
26
Output
/PDWN
25
Input
VCC
31, 40, 48, 56
GND
4, 28, 36, 44, 52
LVDS VCC
LVDS GND
PLL VCC
PLL GND
13
8, 14, 21
23
22, 24
LVDS
LVDS Clock Inputs
Pixel Data Outputs
LVCMOS
-
Power
Pixel Clock Output
H : Normal Operation
L : Power Down (All outputs are pulled to
ground)
Power Supply Pins for LVCMOS outputs
and digital circuitry
Ground Pins for LVCMOS outputs and
digital circuitry
Power Supply Pins for LVDS inputs
Ground Pins for LVDS inputs
Power Supply Pins for PLL circuitry
Ground Pins for PLL circuitry
Table 1. Pin Description
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Absolute Maximum Ratings
Parameter
Supply Voltage (VCC, LVDS VCC, PLL VCC)
LVCMOS Input Voltage
LVCMOS Output Voltage
LVDS Input Pin
Junction Temperature
Storage Temperature
Reflow Peak Temperature
Reflow Peak Temperature Time
Maximum Power Dissipation @+25C
Min
-0.3
-0.3
-0.3
-0.3
-55
-
Max
+4.0
VCC + 0.3
VCC + 0.3
VCC + 0.3
+125
+150
+260
10
1.9
Unit
V
V
V
V
C
C
C
sec
W
Max
3.6
+85
112
Unit
V
C
MHz
Table 2. Absolute Maximum Ratings
Recommended Operating Conditions
Symbol
VCC33
Ta
PCLK
Parameter
All Supply Voltage(VCC, LVDS VCC, PLL VCC)
Operating Ambient Temperature
RCLK and CLKOUT Clock Frequency
Min
3.0
-40
8
Typ
+25
-
Table 3. Recommended Operating Conditions
“Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics Table4, 5, 6, 7” specify conditions for device operation.
“Absolute Maximum Rating” value also includes behavior of overshooting and undershooting.
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Equivalent LVDS Input Schematic Diagram
Output
Control
LVDS VCC
LVDS VCC
CMP
LVDS VCC
LVDS +
AMP
LVDS -
Figure 3. LVDS Input Schematic Diagram
Output Control
/PDWN
H
H
H
L
RCLK +/- Input
Valid Clock
Invalid Clock
Open or Hi-z
Don’t Care
LVCMOS Output
Active Clock & Data
Unfixed Clock & Data
All Low
All Low
Table 4. LVCMOS Output Data Control
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Power Consumption
Over recommended operating supply and temperature range unless otherwise specified
Symbol
Parameter
IRCCG
LVDS Receiver Operating Current
Gray Scale Pattern 16 (Fig.4)
IRCCW
IRCCS
LVDS Receiver Operating Current
Worst Case Pattern(Fig.5)
LVDS Receiver
Power Down Current
Conditions
CL=8pF, PCLK=65MHz,
VCC33=3.3V
CL=8pF, PCLK=112MHz,
VCC33=3.3V
CL=8pF, PCLK=65MHz,
VCC33=3.3V
CL=8pF, PCLK=112MHz,
VCC33=3.3V
/PDWN=L
Typ*
Max
Unit
55
70
mA
90
110
mA
90
110
mA
130
160
mA
-
500
µA
*Typ values are at the conditions of Ta = +25ºC
Table 5. Power Consumption
16 Grayscale Pattern
CLKOUT
RA3, RB4, RC5
RA2, RB3, RC4
RA1, RB2, RC3
RA0, RB1, RC2
TA4-6, TB0/5/6
TC0/1/6, TD0-2
Steady State Low
TD3-6
Steady State High
Figure 4. 16 Grayscale Pattern
Worst Case Pattern
CLKOUT
Rx0-6
X=A,B,C,D
Figure 5. Worst Case Pattern
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Electrical Characteristics
LVDS Receiver DC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Symbol
VTH
VTL
IIN
Parameter
Differential Input High
Threshold
Differential Input Low
Threshold
Conditions
Min
Typ*
Max
Unit
-
-
100
mV
-100
-
-
mV
-
-
30
A
RL=100Ω, VIC=+1.2V
VIN=+2.4 / 0V
LVDS VCC=3.6V
Input Current
Table 6. LVDS Receiver DC Specifications
LVCMOS DC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Symbol
VIH
VIL
Parameter
High Level Input Voltage
Low Level Input Voltage
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IIN
Input Current
Conditions
IOH=-4mA (Data)
IOH=-8mA (Clock)
IOL=4mA (Data)
IOL=8mA (Clock)
GND  VIN  VCC
Min
2.0
GND
Typ
-
Max
VCC
0.8
Unit
V
V
2.4
-
-
V
-
-
0.4
V
-
-
10
A
Table 7. LVCMOS DC Specifications
LVCMOS Output Load Limitation
The output load is limited so that the junction temperature does not exceed 125C.
25.0
Output Load [pF]
20.0
15.0
10.0
5.0
Ta= 70 ℃
Ta= 85 ℃
0.0
8
28
48
68
88
108
CLKOUT [MHz]
Figure 6. LVCMOS Output Load Limitation
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Switching Characteristics
Over recommended operating supply and temperature range unless otherwise specified
Symbol
tRCP
tRCH
tRCL
tRCD
tRS
tRH
tTLH
tTHL
tSK
tRIP1
tRIP0
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2
tRPLL
Parameter
RCLK and CLKOUT Transition Time
LVCMOS CLKOUT High Time
LVCMOS CLKOUT Low Time
RCLK IN to CLKOUT Delay
LVCMOS Data Setup to CLKOUT
LVCMOS Data Hold from CLKOUT
LVCMOS Low to High Transition Time
LVCMOS High to Low Transition Time
PCLK=65MHz
LVDS Receiver Skew Margin
PCLK=112MHz
LVDS Input Data Position0
LVDS Input Data Position1
LVDS Input Data Position2
LVDS Input Data Position3
LVDS Input Data Position4
LVDS Input Data Position5
LVDS Input Data Position6
Phase Lock Loop Set
Min
8.92
0.35×T - 0.3
0.45×T - 1.6
-0.55
-0.25
- tSK
T/7- tSK
2T/7- tSK
3T/7- tSK
4T/7- tSK
5T/7- tSK
6T/7- tSK
-
Typ*
T
T/2
T/2
(3/14+3)×T
0.7
0.7
0.0
T/7
2T/7
3T/7
4T/7
5T/7
6T/7
-
Max
125
1.0
1.0
0.55
0.25
+ tSK
T/7+ tSK
2T/7+ tSK
3T/7+ tSK
4T/7+ tSK
5T/7+ tSK
6T/7+ tSK
10.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
*Typ values are at the conditions of VCC33=3.3V and Ta = +25ºC
Table 8. LVCMOS & LVDS Receiver AC Specifications
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AC Timing Diagrams
LVDS Input
tRCP
RCLK+
Note:Vdiff=(RCLK+)-(RCLK-)
Vdiff = 0V　(Differential)
Vdiff = 0V　RA+/-
RA6
RA5
RA4
RA3
RA2
RA1
RA0
RB+/-
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RC+/-
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RD+/-
RD6
RD5
RD4
RD3
RD2
RD1
RD0
Previous Cycle
Current Cycle
Next Cycle
tRIP1
tRIP0
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2
Figure 7. LVDS Input Data Position
LVCMOS Output
80％
80％
CL=8pF
20％
20％
tTLH
tTHL
Figure 8. LVCMOS Output Load and Transition Time
tRCP
tRCH
CLKOUT
VCC/2
tRCL
VCC/2
tRS
RA0-RA6
RB0-RB6
RC0-RC6
RD0-RD6
VCC/2
VCC/2
tRH
Valid Data
VCC/2
Figure 9. LVCMOS Output Setup and Hold Time
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Input to Output Delay
Note:Vdiff=(RCLK+)-(RCLK-)
Vdiff = 0V
RCLK+
tRCD
VCC/2
CLKOUT
Figure 10.Input Clock to Output Clock Delay Time
Phase Lock Loop Set Time
3.0V
VCC33
RCLK+/-
/PDWN
VCC/2
tRPLL
CLKOUT
VCC/2
Figure 11. PLL Lock Loop Set Time
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Application note
Display Data Mapping Example
VESA format
JEIDA format
Transmitter
Pin
6bit(18bpp) 8bit(24bpp) 6bit(18bpp) 8bit(24bpp)
TA0
R0
R0
R2
R2
TA1
R1
R1
R3
R3
TA2
R2
R2
R4
R4
TA3
R3
R3
R5
R5
TA4
R4
R4
R6
R6
TA5
R5
R5
R7
R7
TA6
G0
G0
G2
G2
TB0
G1
G1
G3
G3
TB1
G2
G2
G4
G4
TB2
G3
G3
G5
G5
TB3
G4
G4
G6
G6
TB4
G5
G5
G7
G7
TB5
B0
B0
B2
B2
TB6
B1
B1
B3
B3
TC0
B2
B2
B4
B4
TC1
B3
B3
B5
B5
TC2
B4
B4
B6
B6
TC3
B5
B5
B7
B7
TC4
Hsync
Hsync
Hsync
Hsync
TC5
Vsync
Vsync
Vsync
Vsync
TC6
DE
DE
DE
DE
TD0
R6
R0
TD1
R7
R1
TD2
G6
G0
TD3
G7
G1
TD4
B6
B0
TD5
B7
B1
TD6
N/A
N/A
Note : Use TA to TC channels and open TD channel for 6bit application.
Receiver
Pin
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RD0
RD1
RD2
RD3
RD4
RD5
RD6
Table 9. Data Mapping for VESA & JEIDA RGB Color format
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System Connection Example
VCC33
PCB(Transmitter)
PCB(Receiver)
VCC33
Ferrite Bead
Ferrite Bead
Ferrite Bead
Ferrite Bead
THC63LVDM83D
THC63LVDF(R)84C
0.01uF
VCC
0.1uF 0.01uF
LVDS VCC
LVDS VCC
0.01uF
0.1uF
0.1uF
0.01uF
GND
GND
LVDS GND
CLKIN
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
HSYNC
VSYNC
DE
R0
R1
G0
G1
B0
B1
CLKIN
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD6
0.1uF
VCC
LVDS GND
PLL VCC
PLL VCC
0.01uF
0.1uF
0.1uF
0.01uF
PLL GND
PLL GND
TA-
RA100ohm
TA+
RA+
TB-
RB100ohm
TB+
RB+
TC-
RC100ohm
TC+
RC+
TCLK-
CLKOUT
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RD0
RD1
RD2
RD3
RD4
RD5
RD6
CLKOUT
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
HSYNC
VSYNC
DE
R0
R1
G0
G1
B0
B1
OPEN
RCLK100ohm
TCLK+
/PDWN
RCLK+
/PDWN
/PDWN
TD-
VCC33
/PDWN
RD100ohm
TD+
RD+
RS
100ohm pair Cable
or
PCB trace
R/F
GND
GND
Figure 12. Connection Example with JEIDA Format
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Notes
1) Cable Connection and Disconnection
Do not connect and disconnect the LVDS cable, when the power is supplied to the system.
2) GND Connection
Connect each GND of the PCB which LVDS-Tx and THC63LVDF84C on it. It is better for EMI reduction
to place GND cable as close to LVDS cable as possible.
3) Multi Drop Connection
Multi drop connection is not recommended.
RCLK+
LVDS-Tx
THC63LVDF84C
RCLKTHC63LVDF84C
Figure 13. Multi Drop Connection
4) Asynchronous use
Asynchronous using such as following systems is not recommended.
CLKOUT
RCLK+
LVDS-Tx
DATA
IC
CLKOUT
RCLK-
CLKOUT
THC63LVDF84C
IC
RCLK+
LVDS-Tx
DATA
RCLK-
THC63LVDF84C
RCLK+
RCLKIC
DATA
CLKOUT
THC63LVDF84C
DATA
IC
RCLK+
RCLK-
DATA
THC63LVDF84C
DATA
Figure 14. Asynchronous Use
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Package
Figure 15. Package Diagram
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Reference Land Pattern
Figure 16. Reference of Land Pattern
The recommendation mounting method of THine device is reflow soldering.
The reference pattern is using the calculation result on condition of reflow soldering.
Notes
This land pattern design is a calculated value based on JEITA ET-7501.
Please take into consideration in an actual substrate design about enough the ease of mounting, the intensity of
connection, the density of mounting, and the solder paste used, etc… The optimal land pattern size changes
with these parameters. Please use the value shown by the land pattern as reference data.
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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply
to the customer's design. We are not responsible for possible errors and omissions in this material. Please
note if errors or omissions should be found in this material, we may not be able to correct them immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties
the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we
will be exempted from the responsibility unless it directly relates to the production process or functions of
the product.
5. Product Application
5.1 Application of this product is intended for and limited to the following applications: audio-video
device, office automation device, communication device, consumer electronics, smartphone, feature
phone, and amusement machine device. This product must not be used for applications that require
extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear
power control device, combustion chamber device, medical device related to critical care, or any kind
of safety device.
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a
product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in
this data sheet. THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product other
than the Specified Product for it not conforming to the aforementioned demands and specifications.
5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent
that the user and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a
certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to
have sufficiently redundant or error preventive design applied to the use of the product so as not to have our
product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems
necessary to support warranty for performance of this product. Except where mandated by applicable
law or deemed necessary by THine based on the user’s request, testing of all functions and
performance of the product is not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or
malfunction, if pins of the product are shorted by such as foreign substance. The damageｓ may cause a
smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection
devices, such as fuses.
THine Electronics, Inc.
[email protected]
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