THC63LVD103D_Rev.4.00_E THC63LVD103D 160MHz 30bit COLOR LVDS TRANSMITTER General Description Features The THC63LVD103D transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to 1080p(60Hz) . The THC63LVD103D converts 35bits of CMOS/TTL data into four LVDS data streams. The transmitter can be programmed for rising edge or falling edge clock through a dedicated pin. At a transmit clock frequency of 160MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC, DE, CONT1) are transmitted at an effective rate of 1120Mbps per LVDS channel. ･Compatible with TIA/EIA-644 LVDS Standard ･7:1 LVDS Transmitter ･Operating Temperature Range : 0 to +70°C ･No Special Start-up Sequence Required ･Spread Spectrum Clocking Tolerant up to 100kHz Frequency Modulation and +/-2.5% Deviations. ･Wide Dot Clock Range: 8 to 160MHz Suited for TV Signal : NTSC(12.27MHz) - 1080p(148.5MHz) PC Signal : QVGA(8MHz) - WUXGA(154MHz) ･64pin TQFP Package ･1.2V to 3.3V LVCMOS/ inputs are supported. ･LVDS swing is reducible as 200mV by RS-pin to reduce EMI and power consumption. ･PLL requires no external components. ･Power Down Mode. ･Input clock triggering edge is selectable by R/F-pin ･EU RoHS Compliant. Application ･Medium and Small Size Panel ･Tablet PC / Notebook PC ･Security Camera / Industrial Camera ･Multi Function Printer ･Industrial Equipment ･Medical Equipment Monitor Block Diagram Figure 1. Block Diagram Copyright©2014 THine Electronics, Inc. 1 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E Pin Diagram Figure 2. Pin Diagram Copyright©2014 THine Electronics, Inc. 2 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E Pin Description Pin Name TA+, TATB+, TBTC+, TCTD+, TDTE+, TETCLK+, TCLKTA0 ~ TA6 TB0 ~ TB6 TC0 ~ TC6 TD0 ~ TD6 TE0 ~ TE6 /PDWN Pin # 30, 31 28, 29 24, 25 20, 21 18, 19 22, 23 33, 34, 35, 36, 37, 38, 40 41, 42, 44, 45, 46, 48, 49 50, 52, 53, 54, 55, 57, 58 59, 61, 62, 63, 64, 1, 3 4, 5, 6, 8, 9, 11, 16 13 RS 43 R/F 60 CLKIN VCC 12 51, 7 GND 2, 10, 39, 47, 56 LVDS VCC LVDS GND PLL VCC PLL GND 27 17, 26, 32 15 14 Direction Type Output LVDS Description LVDS Data Out LVDS Clock Out Pixel Data Input H : Normal Operation L : Power Down (All outputs are Hi-Z) LVDS Swing Mode, VREF Select See Fig.8, 9 Input LVCMOS /TTL Power - LVDS Small Swing Swing Input Support VCC 350mV N/A 0.6 ~ 1.4V 350mV RS=VREF GND 200mV N/A VREF : is Input Reference Voltage Input Clock Triggering Edge Select H : Rising Edge L : Falling Edge Input Clock Power Supply Pins for LVCMOS/TLL Inputs and Digital Circuitry. Ground Pins for LVCMOS/TTL Inputs and Digital Circuitry. Power Supply Pins for LVDS Outputs. Ground Pins for LVDS Outputs. Power Supply Pin for PLL Circuitry. Ground Supply Pin for PLL Circuitry. RS Table 1. Pin Description Copyright©2014 THine Electronics, Inc. 3 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E Absolute Maximum Ratings Parameter Supply Voltage (VCC) LVCMOS/TTL Input Voltage LVCMOS/TTL Output Voltage LVDS Output Pin Output Current Junction Temperature Storage Temperature Reflow Peak Temperature Reflow Peak Temperature Time Maximum Power Dissipation @+25°C Min -0.3 -0.3 -0.3 -0.3 Max +4.0 VCC + 0.3 VCC + 0.3 VCC + 0.3 -55 - +125 +150 +260 10 1.8 Unit V V V V mA °C °C °C sec W Table 2. Absolute Maximum Ratings Recommended Operating Conditions Symbol Ta - Parameter Min Typ All Supply Voltage 3.0 3.3 Operating Ambient Temperature 0 25 Clock Frequency 8 Table 3. Recommended Operating Conditions Max 3.6 +70 160 Unit V °C MHz “Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics Table4, 5, 6, 7” specify conditions for device operation. “Absolute Maximum Rating” value also includes behavior of overshooting and undershooting. Equivalent LVDS Output Schematic Diagram 3.5mA IN_N LVDS_OutN LVDS_OutP IN_P Figure 3. LVDS Output Schematic Diagram Copyright©2014 THine Electronics, Inc. 4 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E Power Consumption Over recommended operating supply and temperature range unless otherwise specified Parameter Conditions Typ* Max Unit Symbol RL=100Ω, CL=5pF, f=85MHz, RS=VCC 69 75 mA RL=100Ω, CL=5pF, f=135MHz, RS=VCC 87 93 mA RL=100Ω, CL=5pF, f=160MHz, RS=VCC 97 104 mA LVDS Transmitter RL=100Ω, CL=5pF, f=85MHz, RS=GND Operating Current RL=100Ω, CL=5pF, f=160MHz, RS=GND Worst Case Pattern (Fig.5) RL=100Ω, CL=5pF, f=160MHz, RS=GND LVDS Transmitter ITCCS /PDWN=L, All Inputs=L or H Power Down Current *Typ values are at the conditions of VCC=3.3V and Ta = +25ºC Table 4. Power Consumption 55 61 mA 73 79 mA 83 89 mA - 10 µA ITCCW LVDS Transmitter Operating Current Worst Case Pattern (Fig.5) Worst Case Pattern CLKIN Tx0-6 x=A,B,C,D Figure 4. Worst Case Pattern Copyright©2014 THine Electronics, Inc. 5 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E Electrical Characteristics LVCMOS/TTL DC Specifications Over recommended operating supply and temperature range unless otherwise specified Parameter Conditions Min Typ* Max Unit High Level Input Voltage RS=VCC or GND 2.0 VCC V Low Level Input Voltage RS=VCC or GND GND 0.8 V Small Swing Voltage 1.2 2.8 V Input Reference Voltage Small Swing (RS=VDDQ/2) VDDQ/2 Small Swing High Level VDDQ/2 VREF= VDDQ/2 V Input Voltage +100mV 2 VSL Small Swing Low Level VDDQ/2 VREF= VDDQ/2 V Input Voltage -100mV IINC Input Current ±10 μA GND ≤ VIN ≤ VCC *Typ values are at the conditions of VCC=3.3V and Ta = +25ºC Notes : 1 VDDQ voltage defines the max voltage of small swing inputs at RS=VREF. It is not an actual input Symbol VIH VIL VDDQ1 VREF VSH2 voltage. 2 Small swing signals are applied to TA0-6, TB0-6, TC0-6, TD0-6 and CLKIN. Table 5. LV-CMOS/TTL DC Specifications LVDS Transmitter DC Specifications Over recommended operating supply and temperature range unless otherwise specified Parameter Conditions Min Typ* Max Unit Normal swing 250 350 450 mV RS=VCC VOD Differential Output Voltage RL=100Ω Reduced swing 100 200 300 mV RS=GND ∆VOD Change in VOD between 35 mV complementary output states RL=100Ω VOC Common Mode Voltage 1.125 1.25 1.375 V ∆VOC Change in VOC between 35 mV complementary output states IOS Output Short Circuit Current -24 mA VOUT=GND, RL=100Ω /PDWN=GND, IOZ Output TRI-STATE Current ±10 μA VOUT=GND to VCC *Typ values are at the conditions of VCC=3.3V and Ta = +25ºC Table 6. LVDS Transmitter DC Specifications Symbol Copyright©2014 THine Electronics, Inc. 6 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E LVCMOS/TTL & LVDS Transmitter AC Specifications Over recommended operating supply and temperature range unless otherwise specified Symbol Parameter Min Typ Max Unit tTCIT CLK IN Transition Time 5.0 ns tTCP CLK IN Period 6.25 T 125 ns tTCH CLK IN High Time 0.35T 0.5T 0.65T ns tTCL CLK IN Low Time 0.35T 0.5T 0.65T ns tTCD CLK IN to TCLK+/- Delay 3T ns tTS LVCMOS/TTL Data Setup to CLK IN 2.0 ns tTH LVCMOS/TTL Data Hold from CLK IN 0.0 ns tLVT LVDS Transition Time 0.6 1.5 ns tTOP1 Output Data Position0 (T=6.25ns ~ 20ns) -0.15 0.0 +0.15 ns tTop0 Output Data Position1 (T=6.25ns ~ 20ns) T/7-0.15 T/7 T/7+0.15 ns tTop6 Output Data Position2 (T=6.25ns ~ 20ns) 2T/7-0.15 2T/7 2T/7+0.15 ns tTop5 Output Data Position3 (T=6.25ns ~ 20ns) 3T/7-0.15 3T/7 3T/7+0.15 ns tTop4 Output Data Position4 (T=6.25ns ~ 20ns) 4T/7-0.15 4T/7 4T/7+0.15 ns tTop3 Output Data Position5 (T=6.25ns ~ 20ns) 5T/7-0.15 5T/7 5T/7+0.15 ns tTop2 Output Data Position6 (T=6.25ns ~ 20ns) 6T/7-0.15 6T/7 6T/7+0.15 ns tTPLL Phase Lock Loop Set 10.0 ms *Typ values are at the conditions of VCC=3.3V and Ta = +25ºC Table 7. LVCMOS/TTL & LVDS Transmitter AC Specifications LVCMOS/TTL Input 90% CLK IN 90% 10% 10% t TCIT t TCIT Figure 5. CLKIN Transmission Time LVDS Output LVDS Output Load Figure 6. LVDS Output Load and Transmission Time Copyright©2014 THine Electronics, Inc. 7 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E AC Timing Diagrams LVCMOS/TTL Inputs tTCP tTCH V DDQ RS VCC 0.6 ~ 1.4V GND VOD 350mV 200mV CLKIN GND tTCL tTH tTS V DDQ Tx0-Tx6 GND tTCD TCLK+ VOC TCLK- Note : CLKIN : Solis line denotes the setting of R/F=GND Dashed line denotes the setting of R/F = VCC Figure 7. LVCOMS/TTL Inputs and LVDS Clock Output Timing 1 Small Swing Inputs RS VREF VCC --0.6 ~ 1.4V VDDQ/2 GND --- tTCP tTCH V DDQ CLKIN VDDQ /2 V DDQ /2 V REF VDDQ /2 GND tTCL tTS tTH V DDQ VDDQ /2 Tx0-Tx6 V DDQ /2 V REF GND tTCD TCLK+ VOC TCLK- Note : CLKIN : Solid line denotes the setting of R/F=GND Dashed line denotes the setting of R/F = VCC Figure 8. LVCMOS/TTL Inputs and LVDS Output Timing 2 Copyright©2014 THine Electronics, Inc. 8 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E LVDS Output Data Position TCLK+/(Differential) Vdiff = 0V Vdiff = 0V TA+/- TA6 TA5 TA4 TA3 TA2 TA1 TA0 TB+/- TB6 TB5 TB4 TB3 TB2 TB1 TB0 TC+/- TC6 TC5 TC4 TC3 TC2 TC1 TC0 TD+/- TD6 TD5 TD4 TD3 TD2 TD1 TD0 Previous Cycle Next Cycle t TOP1 t TOP0 t TOP6 t TOP5 t TOP4 t TOP3 t TOP2 Figure 9. LVDS Output Data Position Phase Lock Loop Set Time Figure 10. PLL Lock Loop Set Time Copyright©2014 THine Electronics, Inc. 9 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E Spread Spectrum Clocking Tolerant Difference of Jitter PLL Jitter Tolerance 103D vs 103 Difference of PLL Tolerance THC63LVD103D 10 9 CLK freqency 8 fclk δf Βf / fclk (+/-%) 7 6 1/fmod Modulation period 5 t 4 3 fclk :Input CLK Frequency 2 fmod:SS modulation frequency 1 δf 0 10 500 103D fclk=25MHz 50 100100 103D fclk=50MHz :SS amplitude 1000 103D fclk=135MHz Figure 11. Spread Spectrum Clocking Tolerant The graph indicates the range that the IC works normally under SS clock input operation. The results are measured with a typical sample on condition of +25Cº and 3.3V, therefore these values are for reference and do not guarantee the performance of a product under other circumstance. Copyright©2014 THine Electronics, Inc. 10 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E LVDS Data Timing Diagram Figure 12. LVDS Data Timing Diagram THC63LVD103D Pixel Data Mapping for JEIDA Format (6bit, 8bit and 10bit Application) TA0 TA1 TA2 TA3 TA4 TA5 TA6 6bit R4 R5 R6 R7 R8 R9 G4 8bit R4 R5 R6 R7 R8 R9 G4 8bit R4 R5 R6 R7 R8 R9 G4 TB0 TB1 TB2 TB3 TB4 TB5 TB6 G5 G6 G7 G8 G9 B4 B5 G5 G6 G7 G8 G9 B4 B5 G5 G6 G7 G8 G9 B4 B5 TC0 TC1 TC2 TC3 TC4 TC5 TC6 B6 B7 B8 B9 Hsync Vsync DE TD0 TD1 TD2 TD3 TD4 TD5 TD6 - B6 B7 B8 B9 Hsync Vsync DE R2 R3 G2 G3 B2 B3 N/A B6 B7 B8 B9 Hsync Vsync DE R2 R3 G2 G3 B2 B3 N/A TE0 TE1 TE2 TE3 TE4 TE5 TE6 - - R0 R1 G0 G1 B0 B1 N/A Note : Use TA to TC channels and open TD channel for 6bit application. Use TA to TD channels and open TE channel for 8bit application. Table 8. Data Mapping for JEIDA Format Copyright©2014 THine Electronics, Inc. 11 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E THC63LVD103D Pixel Data Mapping for VESA Format (6bit, 8bit and 10bit Application) TA0 TA1 TA2 TA3 TA4 TA5 TA6 6bit R0 R1 R2 R3 R4 R5 G0 8bit R0 R1 R2 R3 R4 R5 G0 8bit R0 R1 R2 R3 R4 R5 G0 TB0 TB1 TB2 TB3 TB4 TB5 TB6 G1 G2 G3 G4 G5 B0 B1 G1 G2 G3 G4 G5 B0 B1 G1 G2 G3 G4 G5 B0 B1 TC0 TC1 TC2 TC3 TC4 TC5 TC6 B2 B3 B4 B5 Hsync Vsync DE TD0 TD1 TD2 TD3 TD4 TD5 TD6 - B2 B3 B4 B5 Hsync Vsync DE R6 R7 G6 G7 B6 B7 N/A B2 B3 B4 B5 Hsync Vsync DE R6 R7 G6 G7 B6 B7 N/A TE0 TE1 TE2 TE3 TE4 TE5 TE6 - - R8 R9 G8 G9 B8 B9 N/A Note : Use TA to TC channels and open TD channel for 6bit application. Use TA to TD channels and open TE channel for 8bit application. Table 9. Data Mapping for VESA Format Copyright©2014 THine Electronics, Inc. 12 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E Normal Connection with JEIDA Format Example THC63LVD103D : Falling Edge / Normal Swing Figure 13. Typical Connection Diagram Copyright©2014 THine Electronics, Inc. 13 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E Notes 1) Cable Connection and Disconnection Do not connect and disconnect the LVDS cable, when the power is supplied to the system. 2) GND Connection Connect each GND of the PCB which THC63LVDM83D and LVDS-Rx on it. reduction to place GND cable as close to LVDS cable as possible. It is better for EMI 3) Multi Drop Connection Multi drop connection is not recommended. TCLK+ THC63LVD103D LVDS-RX TCLKLVDS-RX Figure 14. Multi Drop Connection 4) Asynchronous use Asynchronous using such as following systems is not recommended. CLKOUT CLKOUT TCLK+ DATA THC63LVD103D IC CLKOUT TCLK- LVDS-RX IC TCLK+ DATA THC63LVD103D TCLK- CLKOUT DATA LVDS-RX DATA TCLK+ DATA THC63LVD103D IC CLKOUT TCLKTCLK+ DATA THC63LVD103D IC TCLK- Figure 15. Asynchronous Use Copyright©2014 THine Electronics, Inc. 14 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E Package Figure 16. Package Diagram Copyright©2014 THine Electronics, Inc. 15 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E Reference Land Pattern CY1= 13.34 HD = e= 12.000 0.500 D= 10.00 Packgae Land Pattern Ttyp.= 0.60 Gmin= 10.40 1.1 5 b= 0. 200 Zmax= 12. 70 Xmax= 0.3 70 Zmax/2 Unit mm Figure 17. Reference of Land Pattern The recommendation mounting method of THine device is reflow soldering. The reference pattern is using the calculation result on condition of reflow soldering. Notes This land pattern design is a calculated value based on JEITA ET-7501. Please take into consideration in an actual substrate design about enough the ease of mounting, the intensity of connection, the density of mounting, and the solder paste used, etc… The optimal land pattern size changes with these parameters. Please use the value shown by the land pattern as reference data. Copyright©2014 THine Electronics, Inc. 16 THine Electronics, Inc. THC63LVD103D_Rev.4.00_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. This product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the product. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. [email protected] Copyright©2014 THine Electronics, Inc. 17 THine Electronics, Inc.