FEATURES Voltage feedback amplifier Ideal for ADSL and ADSL2+ central office (CO) and customer premises equipment (CPE) applications Enables high current differential applications Low power operation Single- or dual-supply operation from 10 V (± 5 V) up to 24 V (± 12 V) 5.5 mA total quiescent supply current for full power ADSL and ADSL2+ CO applications Adjustable supply current to minimize power consumption High output voltage and current drive 400 mA peak output drive current 44 V p-p differential output voltage Low distortion −70 dBc MTPR, 26 kHz to 1.1 MHz −65 dBc MTPR, 1.1 MHz to 2.2 MHz High speed: 260 V/μs differential slew rate FUNCTIONAL BLOCK DIAGRAM VCC INP AD8390A OUTN VCC 56kΩ 56kΩ VCOM 56kΩ VEE 56kΩ OUTP INN VEE 07094-002 Data Sheet Low Power, High Output Current Differential Amplifier AD8390A Figure 1. APPLICATIONS ADSL/ADSL2+ CO and CPE line drivers xDSL line drivers High current differential amplifiers GENERAL DESCRIPTION The AD8390A is a high output current, low power consumption differential amplifier. It is particularly well suited for the central office (CO) driver interface in digital subscriber line systems such as ADSL and ADSL2+. In full bias operation, the driver delivers 20.4 dBm output power into low resistance loads while compensating for hybrid and transformer insertion losses and back termination resistors. The AD8390A is available in a thermally enhanced LFCSP package (16-lead LFCSP). Significant control and flexibility in bias current have been designed into the AD8390A. Four power modes are selectable via two digital inputs, PD0 and PD1, providing three levels of driver bias and one power-down state. In addition, the IADJ pin is available for fine quiescent current trimming to tailor the performance of the AD8390A. The low power consumption, high output current, high output voltage swing, and robust thermal packaging enable the AD8390A to be used as the central office line driver in ADSL, ADSL2+, and proprietary xDSL systems, as well as in other high current applications requiring a differential amplifier. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2013 Analog Devices, Inc. All rights reserved. AD8390A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits........................................................................................8 Applications ....................................................................................... 1 Theory of Operation .........................................................................9 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 10 General Description ......................................................................... 1 Supplies, Grounding, and Layout ............................................. 10 Revision History ............................................................................... 2 VCOM Pin .................................................................................. 10 Specifications..................................................................................... 3 Power Management.................................................................... 10 Absolute Maximum Ratings ............................................................ 4 ADSL and ADSL2+ Applications ............................................. 11 Thermal Resistance ...................................................................... 4 Lightning and AC Power Fault ................................................. 11 Maximum Power Dissipation ..................................................... 4 Outline Dimensions ....................................................................... 12 ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 12 Pin Configuration and Function Descriptions ............................. 5 Typical Performance Characteristics ............................................. 6 REVISION HISTORY 2/13—Revision B: Initial Version Rev. B | Page 2 of 12 Data Sheet AD8390A SPECIFICATIONS VS = ±12 V or VS = 24 V, RL = 100 Ω, G = 10, PD(1:0) = (1,1), IADJ = NC, VCOM = NC (bypassed with 0.1 μF capacitor), TA = 25°C, unless otherwise noted. Refer to the basic test circuit in Figure 14. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth Large Signal Bandwidth Peaking Slew Rate NOISE/DISTORTION PERFORMANCE Multitone Power Ratio (26 kHz to 1.1 MHz) Multitone Power Ratio (1.1 MHz to 2.2 MHz) Voltage Noise (RTI) INPUT CHARACTERISTICS RTI Offset Voltage (VOS,DM(RTI)) ±Input Bias Current Input Offset Current Input Resistance Input Capacitance Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Differential Output Voltage Swing Output Balance Error Linear Output Current Output Impedance Output Common-Mode Offset POWER SUPPLY Operating Range (Dual Supply) Operating Range (Single Supply) Total Quiescent Current, IADJ = VEE Total Quiescent Current, IADJ = NC Power Supply Rejection Ratio (PSRR) PD(1:0) = 0 (Low Logic State) PD(1:0) = 1 (High Logic State) VCOM Input Voltage Range Input Resistance VCOM Accuracy Conditions Min Typ VOUT = 0.2 V p-p, RF = 10 kΩ VOUT = 4 V p-p VOUT = 0.2 V p-p VOUT = 4 V p-p 38 35 45 38 0.1 260 MHz MHz dB V/µs –70 dBc –65 dBc 5 nV/√Hz ZLINE = 100 Ω, PLINE = 20.4 dBm, crest factor (CF) = 5.4 ZLINE = 100 Ω, PLINE = 20.4 dBm, crest factor (CF) = 5.4 f = 10 kHz VINP − VINN, VCOM = midsupply VINP – VINN, VCOM = NC –3.0 –3.0 –0.35 (∆VOS,DM(RTI))/(∆VIN,CM) 58 ∆VOUT (∆VOS,CM)/∆VOUT RL = 10 Ω, fC = 100 kHz fC = 2 MHz (VOUTP + VOUTN)/2, VCOM = midsupply (VOUTP + VOUTN)/2, VCOM = NC 42.8 –75 –75 72 +3.0 +3.0 –7.0 +0.35 mV mV µA µA kΩ pF dB 44 60 400 0.1 ±35 ±35 44.6 V dB mA Ω mV mV 5.5 4.0 2.6 0.56 10.0 6.7 3.8 0.67 94 +75 +75 ±12 24 6.5 5.0 3.5 1.0 11.0 8.0 5.0 1.0 0.8 1.6 −11.0 ∆VOUT,CM/∆VCOM Rev. B | Page 3 of 12 0.995 Unit ±1.0 ±1.0 –4.0 ±0.05 400 2 69 ±5 10 PD(1:0) = (1,1) PD(1:0) = (1,0) PD(1:0) = (0,1) PD(1:0) = (0,0) PD(1:0) = (1,1) PD(1:0) = (1,0) PD(1:0) = (0,1) PD(1:0) = (0,0) ∆VOS,DM/∆VS, ∆VS = ±1 V, VCOM = midsupply Max +10.0 28 1.0 1.005 V V mA mA mA mA mA mA mA mA dB V V V kΩ V/V AD8390A Data Sheet ABSOLUTE MAXIMUM RATINGS 3.5 Table 2. TJ = 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified in still air with exposed pad soldered to 4-layer JEDEC test board. θJC is specified at the exposed pad. Table 3. Thermal Resistance Package Type 16-Lead LFCSP (CP-16-4) θJA 30.4 θJC 16 Unit °C/W 2.5 2.0 1.5 1.0 0.5 0 –25 –15 –5 5 15 25 35 45 55 65 75 AMBIENT TEMPERATURE (°C) 85 07094-003 Rating 26 V VEE < VCOM < VCC See Figure 2 150°C –40°C to +85°C –65°C to +150°C 300°C MAXIMUM POWER DISSIPATION (W) Parameter Supply Voltage (VCC − VEE) VCOM Package Power Dissipation Maximum Junction Temperature (TJ MAX) Operating Temperature Range (TA) Storage Temperature Range Lead Temperature (Soldering, 10 sec) 3.0 Figure 2. Maximum Power Dissipation vs. Temperature The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming that the load RL is referenced to midsupply, the total drive power is VS/2 × IOUT, part of which is dissipated in the package and part in the load (VOUT × IOUT). RMS output voltages should be considered. If RL is referenced to VEE as in single-supply operation, the total power is VS × IOUT. In single-supply operation with RL referenced to VEE, the worst case is VOUT = VS/2. MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the AD8390A is limited by its junction temperature on the die. The maximum safe junction temperature of plastic encapsulated devices, as determined by the glass transition temperature of the plastic, is 150°C. Exceeding this limit temporarily may cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. Exceeding this limit for an extended period can result in device failure. Airflow increases heat dissipation, effectively reducing θJA. In addition, more copper in direct contact with the package leads from PCB traces, through holes, ground, and power planes reduces θJA. ESD CAUTION Figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature. θJA values are approximations. Rev. B | Page 4 of 12 Data Sheet AD8390A 12 OUTN 11 VEE 10 VCC 9 OUTP 14 NC NOTES 1. NC = NO CONNECT. 2. NO ELECTRICAL CONNECTION. CONNECT THE EXPOSED PAD TO A SOLID EXTERNAL PLANE WITH LOW THERMAL RESISTANCE. 07094-004 NC 8 IADJ 7 TOP VIEW (Not to Scale) NC 5 INN 4 AD8390A DGND 6 PD0 3 13 NC 16 NC PIN 1 INDICATOR INP 1 PD1 2 15 VCOM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic INP PD1 PD0 INN NC DGND IADJ NC OUTP VCC VEE OUTN NC NC VCOM NC EPAD Description Amplifier Noninverting Input. Power Mode Control. Power Mode Control. Amplifier Inverting Input. No Connection. Ground. Bias Current Adjustment. No Connection. Amplifier Noninverting Output. Positive Power Supply. Negative Power Supply. Amplifier Inverting Output. No Connection. No Connection. Common-Mode Voltage. No Connection. Exposed pad. No electrical connection. Connect the exposed pad to a solid external plane with low thermal resistance. Rev. B | Page 5 of 12 AD8390A Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VS = ±12 V, RL = 100 Ω, G = 10, PD(1:0) = (1,1), IADJ = NC, VCOM = NC (bypassed with 0.1 μF capacitor), TA = 25°C, unless otherwise noted. Refer to the basic test circuit in Figure 14. 44 DIFFERENTIAL DC OUTPUT SWING (V p-p) 25 PD(1:0) = (1,1) IADJ = NC PD(1:0) = (1,0) IADJ = NC PD(1:0) = (0,1) IADJ = NC 10 PD(1:0) = (1,1) IADJ = VEE 5 PD(1:0) = (1,0) IADJ = VEE 0 PD(1:0) = (0,1) IADJ = VEE –5 0.1 1 10 FREQUENCY (MHz) 100 40 38 36 34 20 07094-006 GAIN (dB) 15 42 30 50 60 70 80 90 100 110 LOAD (Ω) Figure 4. Differential Small Signal Frequency Response; VS = ±12 V, Gain = 10, VOUT = 200 mV p-p Figure 7. Differential DC Output Swing vs. RL; VS = ±12 V, PD(1:0) = (1,1), RIADJ = NC 10 25 20 PD(1:0) = (1,0) IADJ = NC PD(1:0) = (0,1) IADJ = NC 10 PD(1:0) = (1,1) IADJ = VEE 5 PD(1:0) = (1,0) IADJ = VEE 0 8 QUIESCENT CURRENT (mA) PD(1:0) = (1,1) IADJ = NC 15 GAIN (dB) 40 07094-009 20 6 PD(1:0) = (1,1) PD(1:0) = (1,0) 4 PD(1:0) = (0,1) 2 1 10 FREQUENCY (MHz) 100 0 0.01 07094-007 –5 0.1 1 10 100 1000 RADJ (kΩ) Figure 8. Quiescent Current vs. IADJ Resistor; VS = ±12 V Figure 5. Differential Large Signal Frequency Response; VS = ±12 V, Gain = 10, VOUT = 4 V p-p 6 1000 1.5 PD PULSE PD(1:0) = (1,1) 800 4 1.0 2 0.5 0 0 VPD (V) 600 PD(1:0) = (0,1) 400 VOUT (V) PD(1:0) = (1,0) –0.5 –2 OUTPUT –1.0 –4 0 12 14 16 18 OUTPUT POWER (dBm) 20 22 –6 0 1 2 3 4 5 6 TIME (µs) 7 8 9 Figure 9. Power-Down to Power-Up Time; PD(1:0) = (1,1) to PD(1:0) = (0,0) to PD(1:0) = (1,1) Figure 6. Internal Power Dissipation vs. Output Power; Transformer Turns Ratio = 1:1.4 Rev. B | Page 6 of 12 –1.5 10 07094-011 200 07094-008 INTERNAL POWER DISSIPATION (mW) 0.1 07094-010 PD(1:0) = (0,1) IADJ = VEE Data Sheet AD8390A –30 0 VS = ±12V G = 10 RL = 100Ω PD(1:0) = (0,0) –10 –20 –45 –50 –30 –40 –55 –50 –60 –60 –65 1 10 100 FREQUENCY (MHz) –70 0.01 0.1 1 FREQUENCY (MHz) 10 100 07094-014 CMRR (dB) –40 07094-019 FEEDTHROUGH (dB) –35 Figure 12. CMRR vs. Frequency; VIN = 200 mV p-p, Gain = 10, IADJ = NC Figure 10. Signal Feedthrough 7 0 6 –20 5 4 GAIN (dB) PSR+ –60 –80 3 2 1 0 PSR– –1 –100 –120 0.01 0.1 1 FREQUENCY (MHz) 10 100 –3 0.01 0.1 1 FREQUENCY (MHz) 10 100 07094-015 –2 07094-013 PSRR (dB) –40 Figure 13. Gain with VCOM Driven vs. Frequency; VCOM = 200 mV p-p Figure 11. PSRR vs. Frequency; PD(1:0) = (1,1) Rev. B | Page 7 of 12 AD8390A Data Sheet TEST CIRCUITS 52.3Ω RF = 10kΩ RG = 1kΩ AD8390A VIN RL, DM = 100Ω VOUT, DM 52.3Ω RF = 10kΩ Figure 14. Basic Test Circuit Rev. B | Page 8 of 12 07094-005 RG = 1kΩ Data Sheet AD8390A THEORY OF OPERATION RF VCC AD8390A A VCC RG + OUTN VIN, DM 56kΩ 56kΩ – OUTP RF + Figure 16. Basic Application Circuit 56kΩ 56kΩ The high open-loop gain of the AD8390A and the negative feedback minimize the differential and common-mode error voltages. OUTP VEE 07094-016 B – RL, DM VOUT, DM INN VCOM INN OUTN VCOM RG C VEE INP 07094-017 INP Figure 15. Functional Block Diagram The AD8390A is a true differential amplifier with commonmode feedback. The AD8390A is functionally equivalent to three amplifiers, as shown in Figure 15. Amplifier A and Amplifier B form a standard dual amplifier in an inverting configuration. Amplifier C maintains the common-mode voltage VCOM at the output. With the differential and common-mode error voltages assumed to be 0, the differential-mode gain and input impedance of the basic application circuit shown in Figure 16 are as follows: With VCOM left unconnected, the outputs are internally biased to midsupply. VCOM can be driven externally to set the dc output common-mode voltage. Rev. B | Page 9 of 12 VOUT ,DM V IN ,DM RF RG R IN ,DM 2 RG AD8390A Data Sheet APPLICATIONS INFORMATION SUPPLIES, GROUNDING, AND LAYOUT POWER MANAGEMENT The AD8390A can be powered from either single or dual supplies, with the total supply voltage ranging from 10 V to 24 V. For optimum performance, use well-regulated low ripple supplies. The AD8390A offers significant versatility for maximizing efficiency while maintaining optimal levels of performance. As with all high speed amplifiers, pay close attention to supply decoupling, grounding, and overall board layout. Provide low frequency supply decoupling with 10 µF tantalum capacitors from each supply to ground. In addition, decouple all supply pins with 0.1 µF quality ceramic chip capacitors placed as close as possible to the driver. Use an internal low impedance ground plane to provide a common ground point for all driver and decoupling capacitor ground requirements. Whenever possible, use separate ground planes for analog and digital circuitry. Follow high speed layout techniques to minimize parasitic capacitance around the inverting inputs. Some practical examples of these techniques are keeping feedback traces as short as possible and clearing away ground plane in the area of the inverting inputs. Keep input and output traces as short as possible and as far apart from each other as practical to minimize crosstalk. Keep all differential signal traces as symmetrical as possible. VCOM PIN By design, the VCOM pin is internally biased at midsupply, eliminating the need for external resistors. However, the designer may set VCOM to other voltage levels with an external low impedance source. When the VCOM pin is left unconnected, decouple it with a 0.1 µF capacitor to ground, placed in close proximity to the AD8390A. Optimizing driver efficiency while delivering the required signal level is accomplished with two on-chip power management features: two PD pins to select one of four bias modes and an IADJ pin for fine bias adjustments. PD(1:0) Pins Two CMOS-compatible logic pins, PD1 and PD0, select one of three active power levels and a power-down mode. The digital ground pin (DGND) is the logic ground reference for the PD(1:0) pins. PD(1:0) = (0,0) is the power-down mode. The PD pins are internally connected to DGND via termination resistors. When the PD pins are left unconnected, the AD8390A is in power-down mode. The AD8390A exhibits a low output impedance in the three active modes. The output impedance in the power-down mode is high but undefined and may not be suitable for systems that rely on a high impedance OFF state, such as multiplexing. IADJ Pin The IADJ pin provides bias current fine-tuning. With the IADJ pin unconnected, the bias currents are internally set to 10 mA, 6.7 mA, and 3.8 mA for the three active modes. With the IADJ pin connected to the negative supply (VEE), the bias currents are reduced by approximately 50%. A resistor, RADJ, connected between the IADJ pin and the negative supply, provides fine bias adjustment as shown in Figure 8. Table 5. PD and IADJ Selection Guide With dual equal supplies, connect the VCOM pin directly to ground to bias the outputs at midsupply, eliminating the need for the external decoupling capacitor. PD1 1 1 0 0 1 1 0 0 Rev. B | Page 10 of 12 PD0 1 0 1 0 1 0 1 0 RADJ (Ω) ∞ ∞ ∞ ∞ 0 0 0 0 IQ (mA) 10.0 6.7 3.8 0.67 5.5 4.0 2.6 0.56 Data Sheet AD8390A ADSL AND ADSL2+ APPLICATIONS In a typical ADSL/ADSL2+ application, a differential line driver drives the signal from the analog front end (AFE) onto the twisted pair telephone line. Referring to the typical circuit representation in Figure 17, the differential input appears at VIN+ and VIN− from the AFE. The differential output is transformer-coupled to the telephone line at tip and ring. The common-mode operating point, generally midway between the supplies, is set through VCOM. In ADSL/ADSL2+ applications, it is common practice to conserve power by using positive feedback (R3 in Figure 17) to synthesize the output resistance, lowering the required value of the line matching resistors, RM. +IN 10µF R3 0.1µF R1 –OUT RM 1:N VCOM –IN IADJ 0.1µF RADJ +OUT + – RM R3 R2 07094-018 VEE 0.1µF 10µF Figure 17. ADSL/ADSL2+ Application Circuit The differential input impedance to the circuit is 2 × R1. R1 is chosen by the designer to match system requirements. The synthesized value of the back termination resistor is given by the following equation. RM = k × R2 is given by R2 = R3 1− k With RM, R3, and R2 calculated, the closest 1% resistors are chosen and the gain rechecked with the following equation: R2 × R3 R1 [R M + R2(k + 1) − R3] Note that decreasing the value of the back termination resistors attenuates the receive signal by approximately 1/k. Advances in low noise receive amplifiers permit the use of k values as small as 0.1. RL VOUT, DM R1 where AV is the voltage gain. Table 6 compares the results of the exact values, the simplified approximation, and the closest 1% resistor value calculations. In this example, R1 = 1.0 kΩ, AV = 10, and k = 0.1. PD1 PD0 0.1µF R3 ≅ R1 × 2 × k × AV AV = R2 VCC Assuming low values for back termination resistor RM, R3 is approximated as RL 2× N 2 where RL is the line impedance, and N is the turns ratio of the transformer. The factor k defines the relationship between the negative and positive feedback resistors and is given by R3 k =1 − R2 Commonly used values for k are between 0.1 and 0.25. Values less than 0.1 can lead to instability and are not recommended. The line impedance, turns ratio, and k factor specify the output voltage and current required from the AD8390A. To accommodate higher crest factors or lower supply rails, the turns ratio, N, may need to be increased. Because higher turns ratios and smaller k factors both attenuate the receive signal, a large increase in N may require an increase in k to maintain the desired noise performance. Any particular design process requires that these trade-offs be addressed. Table 6. Resistor Selection Component R1 (Ω) R2 (Ω) R3 (Ω) RM (Ω) Actual AV Actual k Exact Value 1000 2246.95 2022.25 5 10.000 0.1 Approximate Calculation 1000 2222.22 2000 5 9.889 0.1 Standard 1% Resistor Value 1000 2210 2000 4.99 10.138 0.095 LIGHTNING AND AC POWER FAULT When the AD8390A is an ADSL/ADSL2+ line driver, it is transformer-coupled to the twisted pair telephone line. In this environment, the AD8390A is subject to large line transients resulting from events such as lightning strikes or downed power lines. Additional circuitry is required to protect the AD8390A from damage due to these events. Rev. B | Page 11 of 12 AD8390A Data Sheet OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.60 MAX 1.95 REF 0.60 MAX 13 1 12 3.75 BSC SQ 0.65 BSC 2.25 2.10 SQ 1.95 EXPOSED PAD 9 TOP VIEW 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.75 0.60 0.50 0.80 MAX 0.65 TYP 0.35 0.30 0.25 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 4 8 5 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGC 02-26-2013-B PIN 1 INDICATOR PIN 1 INDICATOR 16 Figure 18. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD8390AACPZ-R2 AD8390AACPZ-RL AD8390AACPZ-R7 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead LFCSP_VQ, 250 Piece Reel 16-Lead LFCSP_VQ, 13” Tape and Reel 16-Lead LFCSP_VQ, 7” Tape and Reel Z = RoHS Compliant Part. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07094-0-2/13(B) Rev. B | Page 12 of 12 Package Option CP-16-4 CP-16-4 CP-16-4