Low Cost, Dual, High Current Output Line Driver with Shutdown ADA4310-1 PIN CONFIGURATIONS 10 OUT B NC 2 9 –IN B OUT A 3 8 +IN B –IN A 4 7 PD1 +IN A 5 6 PD0 NC = NO CONNECT 13 OUT B 14 +VS 16 OUT A 15 NC Figure 1. Thermally Enhanced, 10-Lead MINI_SO_EP 10 +IN B GND 4 9 PD1 NC = NO CONNECT –VS 7 +IN A 3 PD0 8 11 −IN B NC 5 −IN A 2 06027-002 12 NC NC 1 APPLICATIONS Home networking line drivers Twisted pair line drivers Power line communications Video line drivers ARB line drivers I/Q channel amplifiers +VS 1 NC 6 High speed −3 dB bandwidth: 190 MHz, G = +5 Slew rate: 820 V/μs, RLOAD = 50 Ω Wide output swing 20.4 V p-p differential, RLOAD of 100 Ω from 12 V supply High output current Low distortion −95 dBc typical at 1 MHz, VOUT = 2 V p-p, G = +5, RLOAD = 50 Ω −69 dBc typical at 10 MHz, VOUT = 2 V p-p, G = +5, RLOAD = 50 Ω Power management and shutdown Control inputs CMOS level compatible Shutdown quiescent current 0.65 mA/amplifier Adjustable low quiescent current: 3.9 mA to 7.6 mA per amp 06027-001 FEATURES Figure 2. Thermally Enhanced, 4 mm × 4 mm 16-Lead LFCSP_VQ GENERAL DESCRIPTION The ADA4310-1 incorporates a power management function that provides shutdown capabilities and/or the ability to optimize the amplifiers quiescent current. The CMOScompatible, power-down control pins (PD1 and PD0) enable the ADA4310-1 to operate in four different modes: full power, medium power, low power, and complete power down. In the power-down mode, quiescent current drops to only 0.65 mA/amplifier, while the amplifier output goes to a high impedance state. The ADA4310-1 is available in a thermally enhanced, 10-lead MSOP with an exposed paddle for improved thermal conduction and in a thermally enhanced, 4 mm × 4 mm 16-lead LFCSP. The ADA4310-1 is rated to work in the extended industrial temperature range of −40°C to +85°C. 1/2 ADA4310-1 VMID1 1/2 ADA4310-1 VCC – VEE 1V = MID 2 06027-003 The ADA4310-1 is comprised of two high speed, current feedback operational amplifiers. The high output current, high bandwidth, and fast slew rate make it an excellent choice for broadband applications requiring high linearity performance while driving low impedance loads. Figure 3. Typical PLC Driver Application Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADA4310-1 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 10 Applications....................................................................................... 1 Application Information................................................................ 11 Pin Configurations ........................................................................... 1 Feedback Resistor Selection...................................................... 11 General Description ......................................................................... 1 Power Control Modes of Operation ........................................ 11 Revision History ............................................................................... 2 Exposed Thermal Pad Connections ........................................ 11 Specifications..................................................................................... 3 Power Line Application ............................................................. 11 Absolute Maximum Ratings............................................................ 5 Board Layout............................................................................... 12 Thermal Resistance ...................................................................... 5 Power Supply Bypassing ............................................................ 12 ESD Caution.................................................................................. 5 Outline Dimensions ....................................................................... 13 Pin Configurations and Function Descriptions ........................... 6 Ordering Guide .......................................................................... 13 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADA4310-1 SPECIFICATIONS VS = 12 V, ±6 V (@ TA = 25°C, G = +5, RL = 100 Ω, unless otherwise noted). Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Slew Rate NOISE/DISTORTION PERFORMANCE Distortion (Worst Harmonic) Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Bias Current Noninverting Input Inverting Input Open-Loop Transimpedance Common-Mode Rejection INPUT CHARACTERISTICS Input Resistance OUTPUT CHARACTERISTICS Single-Ended +Swing Single-Ended −Swing Single-Ended +Swing Single-Ended −Swing Differential Swing POWER SUPPLY Operating Range (Dual Supply) Operating Range (Single Supply) Supply Current Test Conditions/Comments Min G = +5, VOUT = 0.1 V p-p, PD1 = 0, PD0 = 0 PD1 = 0, PD0 = 1 PD1 = 1, PD0 = 0 G = +5, VOUT = 2 V p-p, RLOAD = 50 Ω, PD1 = 0, PD0 = 0 PD1 = 0, PD0 = 1 PD1 = 1, PD0 = 0 Typ Max Unit 190 140 100 820 790 750 MHz MHz MHz V/μs V/μs V/μs −95 −88 −77 dBc dBc dBc −69 −57 −47 dBc dBc dBc −50 −42 −35 2.85 21.8 dBc dBc dBc nV/√Hz pA/√Hz 1 mV −2 6 μA μA RLOAD = 50 Ω RLOAD = 100 Ω 14 35 −62 MΩ MΩ dB f < 100 kHz 500 kΩ RLOAD = 50 Ω RLOAD = 50 Ω RLOAD = 100 Ω RLOAD = 100 Ω RLOAD = 100 Ω +5.08 −5.12 +5.14 −5.17 20.4 VP VP VP VP V p-p fC = 1 MHz, VOUT = 2 V p-p, RLOAD = 50 Ω PD1 = 0, PD0 = 0 PD1 = 0, PD0 = 1 PD1 = 1, PD0 = 0 fC = 10 MHz, VOUT = 2 V p-p, RLOAD = 50 Ω PD1 = 0, PD0 = 0 PD1 = 0, PD0 = 1 PD1 = 1, PD0 = 0 fC = 20 MHz, VOUT = 2 V p-p, RLOAD = 50 Ω PD1 = 0, PD0 = 0 PD1 = 0, PD0 = 1 PD1 = 1, PD0 = 0 f = 100 kHz f = 100 kHz ±2.5 +5 PD1 = 0, PD0 = 0 PD1 = 0, PD0 = 1 PD1 = 1, PD0 = 0 PD1 = 1, PD0 = 1 ±6 +12 7.6 5.6 3.9 0.65 Rev. 0 | Page 3 of 16 V V mA/amp mA/amp mA/amp mA/amp ADA4310-1 Parameter POWER DOWN PINS PD1, PD0 Threshold PD1, PD0 = 0 Pin Bias Current PD1, PD0 = 1 Pin Bias Current Enable/Disable Time Power Supply Rejection Ratio Test Conditions/Comments Min Typ Referenced to GND PD1 or PD0 = 0 V PD1 or PD0 = 3 V 1.5 −0.2 70 Positive/Negative −70/−60 Max 0.04/2 Rev. 0 | Page 4 of 16 Unit V μA μA μs dB ADA4310-1 ABSOLUTE MAXIMUM RATINGS Table 2. Maximum Power Dissipation Parameter Supply Voltage 10-Lead MINI_SO_EP 16-Lead LFCSP_VQ Power Dissipation Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 12 V ±6V (TJMAX − TA)/θJA −65°C to +125°C −40°C to +85°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 10-lead MINI_SO_EP (44°C/W) and for the 16-lead LFCSP_VQ (63°C/W) on a JEDEC standard 4-layer board. θJA values are approximations. 5.0 θJA is specified for the worst-case conditions, that is, θJA is specified for device soldered in circuit board for surface-mount packages. Table 3. θJA 44 63 Unit °C/W °C/W MAXIMUM POWER DISSIPATION (W) 4.5 THERMAL RESISTANCE Package Type 10-Lead MINI_SO_EP 16-Lead LFCSP_VQ The maximum safe power dissipation for the ADA4310-1 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a junction temperature of 150°C for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. 4.0 3.5 MINI_SO_EP-10 3.0 2.5 LFCSP_VQ-16 2.0 1.5 1.0 0 –35 –15 5 25 45 AMBIENT TEMPERATURE (°C) 65 85 06027-016 0.5 Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 16 ADA4310-1 –IN A 4 7 PD1 +IN A 5 6 PD0 NC = NO CONNECT +IN A 3 10 +IN B GND 4 9 PD1 NC = NO CONNECT Figure 5. 10-Lead MSOP Pin Configuration 06027-002 +IN B –VS 7 –IN B 8 11 −IN B PD0 8 9 14 +VS 13 OUT B 16 OUT A NC 2 OUT A 3 12 NC NC 1 −IN A 2 NC 5 OUT B NC 6 10 06027-001 +VS 1 15 NC PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. 16-Lead LFCSP Pin Configuration Table 4. 10-Lead MSOP Pin Function Description Table 5. 16-Lead LFCSP Pin Function Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 (Exposed Paddle) Pin No. 1, 5, 6, 12, 15 2 3 4 7 8 9 10 11 13 14 16 17 (Exposed Paddle) Mnemonic +VS NC OUT A −IN A +IN A PD0 PD1 +IN B −IN B OUT B GND Description Positive Power Supply Input No Connection Amplifier A Output Amplifier A Inverting Input Amplifier A Noninverting Input Power Dissipation Control Power Dissipation Control Amplifier B Noninverting Input Amplifier B Inverting Input Amplifier B Output Ground (Electrical Connection Required) Rev. 0 | Page 6 of 16 Mnemonic NC −IN A +IN A GND −VS PD0 PD1 +IN B −IN B OUT B +VS OUT A GND Description No Connection Amplifier A Inverting Input Amplifier A Noninverting Input Ground Negative Power Supply Input Power Dissipation Control Power Dissipation Control Amplifier B Noninverting Input Amplifier B Inverting Input Amplifier B Output Positive Power Supply Input Amplifier A Output Ground ADA4310-1 TYPICAL PERFORMANCE CHARACTERISTICS –20 VOUT = 100mV p-p RL = 50Ω PD1, PD0 = 0, 0 9 –30 G = +2 HARMONIC DISTORTION (dBc) NORMALIZED GAIN (dB) 6 3 G = +5 0 –3 G = +10 –6 G = +20 –9 –12 –40 –50 –60 –70 1000 06027-022 –110 100 100 Figure 10. Harmonic Distortion vs. Frequency PD1, PD0 = 0, 0 VOLTAGE NOISE (nV/√Hz) 17 14 11 GAIN (dB) 10 100 VOUT = 100mV p-p G = +5 RL = 50Ω 20 1 FREQUENCY (MHz) Figure 7. Small Signal Frequency Response for Various Closed-Loop Gains 23 PD1, PD0 = 0, 0 –90 –120 0.1 FREQUENCY (MHz) PD1, PD0 = 0, 1 –100 –18 10 PD1, PD0 = 1, 0 –80 –15 1 HD2 HD3 VOUT = 2V p-p RL = 50Ω G = +5 06027-023 12 PD1, PD0 = 0, 1 8 5 PD1, PD0 = 1, 0 2 –1 10 –4 –7 10 100 1000 FREQUENCY (MHz) 1 10 RL = 100Ω –45 1000 –90 10k 100k 1M 10M 100M 1G Figure 11. Voltage Noise vs. Frequency 0° 10000 1k FREQUENCY (Hz) Figure 8. Small Signal Frequency Response for Various Modes 100000 100 06027-012 1 06027-021 –10 0.20 0.15 G = +5 RL = 50Ω 10ns/DIV 10 –180 1 –225 OUTPUT (V) –135 PHASE (Degrees) 100 0.05 0 –0.05 –0.10 0.1 0.0001 0.001 0.01 0.1 1 10 100 –270 1000 FREQUENCY (MHz) Figure 9. Open-Loop Transimpedance Gain and Phase vs. Frequency 06027-020 –0.15 06027-013 MAGNITUDE (kΩ) 0.10 –0.20 Figure 12. Small Signal Transient Response Rev. 0 | Page 7 of 16 ADA4310-1 –40 PD1, PD0 = (0, 0) RL = 100Ω PD1, PD0 = (1,1) –10 –60 FEEDTHROUGH (dB) –20 –30 –40 –50 –80 –100 0.1 1 10 100 1000 FREQUENCY (MHz) –120 1 10 PD1, PD0 = (1,1) 100 –20 –30 OUTPUT IMPEDANCE (kΩ) +PSR –40 –PSR –50 –60 10 1 0.1 0.01 0.1 1 10 100 1000 FREQUENCY (MHz) 0.001 0.01 06027-006 –80 0.01 1 10 100 FREQUENCY (MHz) Figure 17. Output Impedance vs. Frequency (Disabled) Figure 14. Power Supply Rejection(PSR) vs. Frequency 100 0.1 2.5 PD1, PD0 = (0, 0) 2.0 10ns/DIV VOUT 10 VOLTAGE (V) 1.5 1 VPD0, VPD1 1.0 0.5 0.1 1 10 100 1000 FREQUENCY (MHz) 06027-009 0 0.01 0.1 06027-011 POWER SUPPLY REJECTION (dB) 1000 –70 OUTPUT IMPEDANCE (Ω) 1000 Figure 16. Off-Isolation vs. Frequency G = +5 PD1, PD0 = (0, 0) RL = 100Ω –10 1000 FREQUENCY (MHz) Figure 13. Common-Mode Rejection(CMR) vs. Frequency 0 100 06027-010 –70 0.01 06027-008 –60 06027-007 COMMON-MODE REJECTION (dB) 0 –0.5 Figure 18. Power-Down Turn On/Turn Off Figure 15. Closed-Loop Output Impedance vs. Frequency Rev. 0 | Page 8 of 16 ADA4310-1 0 –40 –60 –80 –100 –120 0.1 1 10 FREQUENCY (MHz) 100 1000 06027-014 CROSSTALK (dB) –20 Figure 19. Crosstalk Rev. 0 | Page 9 of 16 ADA4310-1 THEORY OF OPERATION The ADA4310-1 is a current feedback amplifier with high output current capability. With a current feedback amplifier, the current into the inverting input is the feedback signal, and the open-loop behavior is that of a transimpedance, dVO/dIIN or TZ. The open-loop transimpedance is analogous to the open-loop voltage gain of a voltage feedback amplifier. Figure 20 shows a simplified model of a current feedback amplifier. Because RIN is proportional to 1/gm, the equivalent voltage gain is just TZ × gm, where gm is the transconductance of the input stage. Basic analysis of the follower with gain circuit yields Because G × RIN << RF for low gains, a current feedback amplifier has relatively constant bandwidth vs. gain, the 3 dB point being set when |TZ| = RF. Of course, for a real amplifier there are additional poles that contribute excess phase, and there is a value for RF below which the amplifier is unstable. Tolerance for peaking and desired flatness determines the optimum RF in each application. RF RG VO TZ ( s ) = G× VIN TZ ( s ) + G × RIN + RF RIN IIN where: VOUT RF RG 06027-017 VIN G = 1+ RIN = TZ RN Figure 20. Simplified Block Diagram 1 ≈ 50 Ω gm Rev. 0 | Page 10 of 16 ADA4310-1 APPLICATION INFORMATION 1 RF (Ω) 499 499 1k 499 499 RG (Ω) 499 124 249 55.4 26.1 −3 dB SS BW (MHz) 230 190 125 160 115 Applications (that is, powerline AV modems) requiring greater than 10 dBm peak power should consider using an external line driver, such as the ADA4310-1. Figure 21 shows an example interface between the TxDAC® output and ADA4310-1 biased for single-supply operation. The TxDAC’s peak-to-peak differential output voltage swing should be limited to 2 V p-p, with the ADA4310-1’s gain configured to realize the additional voltage gain required by the application. A low-pass filter should be considered to filter the DAC images inherent in the signal reconstruction process. In addition, dc blocking capacitors are required to level-shift the TxDAC’s output signal to the common-mode level of the ADA4310-1 (that is, AVDD/2). 0.1µF REFIO Gain +2 +5 +5 +10 +20 POWER LINE APPLICATION Conditions: VS = ±6 V, TA = 25°C, RL = 50 Ω, PD1, PD0 = 0,0. RSET POWER CONTROL MODES OF OPERATION The ADA4310-1 features four power modes: full power, ¾ power, ½ power, and shutdown. The power modes are controlled by two logic pins, PD0 and PD1. The power-down control pins are compatible with standard 3 V and 5 V CMOS logic. Table 7 shows the various power modes and associated logic states. In the power-down mode, the output of the amplifier goes into a high-impedance state. Table 7. Power Modes PD1 Low Low High High PD0 Low High Low High Power Mode Full Power ¾ Power ½ Power Power Down Total Supply Current (mA) 15.2 11.2 7.8 1.3 Output Impedance Low Low Low High EXPOSED THERMAL PAD CONNECTIONS The exposed thermal pad on the 10-lead MSOP package is both the reference for the PD pins and the only electrical connection for the negative supply voltage. Therefore, in the 10-lead MSOP package, the ADA4310-1 can only be used on a single supply. The exposed thermal pad MUST be connected to ground. Failure to do so will render the part inoperable. The 4 mm × 4 mm 16-lead LFCSP package has dedicated pins for both the positive and negative supplies, and it can be used in either single supply or dual supply applications. There is no electrical connection for the exposed thermal pad. Although the pad could theoretically be connected to any potential, it is still typically connected to ground. Rev. 0 | Page 11 of 16 1/2 OPTIONAL LCLPF ADA4310-1 IOUTP+ AVDD/2 TxDAC IOUTP– 0dB TO –7.5dB 1/2 ADA4310-1 Figure 21. TxDAC Output Directly via Center-Tap Transformer 06027-019 Table 6. Recommended Values and Frequency Performance1 A requirement for both packages is that the thermal pad be connected to a solid plane with low thermal resistance, ensuring adequate heat transfer away from the die and into the board. TxDISABLE The feedback resistor has a direct impact on the closed-loop bandwidth and stability of the current feedback op amp. Reducing the resistance below the recommended value can make the amplifier response peak and even become unstable. Increasing the size of the feedback resistor beyond the recommended value reduces the closed-loop bandwidth. Table 6 provides a convenient reference for quickly determining the feedback and gain resistor values, and the corresponding bandwidth, for common gain configurations. The recommended value of feedback resistor for the ADA4310-1 is 499 Ω. REFADJ FEEDBACK RESISTOR SELECTION ADA4310-1 BOARD LAYOUT POWER SUPPLY BYPASSING As is the case with all high speed applications, careful attention to printed circuit board layout details prevents associated board parasitics from becoming problematic. Proper RF design technique is mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance return path. Removing the ground plane on all layers from the area near the input and output pins reduces stray capacitance, particularly in the area of the inverting inputs. Signal lines connecting the feedback and gain resistors should be as short as possible to minimize the inductance and stray capacitance associated with these traces. Termination resistors and loads should be located as close as possible to their respective inputs and outputs. Input and output traces should be kept as far apart as possible to minimize coupling (crosstalk) though the board. Wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize balanced performance. When running differential signals over a long distance, the traces on the PCB should be close. This reduces the radiated energy and makes the circuit less susceptible to RF interference. Adherence to stripline design techniques for long signal traces (greater than about 1 inch) is recommended. The ADA4310-1 operates on supplies, from +5 V to ±6 V. The ADA4310-1 circuit should be powered with a well-regulated power supply. Careful attention must be paid to decoupling the power supply. High quality capacitors with low equivalent series resistance (ESR), such as multilayer ceramic capacitors (MLCCs), should be used to minimize supply voltage ripple and power dissipation. In addition, 0.1 μF MLCC decoupling capacitors should be located no more than ⅛-inch away from each of the power supply pins. A large, usually tantalum, 10 μF capacitor is required to provide good decoupling for lower frequency signals and to supply current for fast, large signal changes at the ADA4310-1 outputs. Bypassing capacitors should be laid out in such a manner to keep return currents away from the inputs of the amplifiers. This minimizes any voltage drops that can develop due to ground currents flowing through the ground plane. A large ground plane also provides a low impedance path for the return currents. For more information on high speed board layout, go to www.analog.com and A Practical Guide to High-Speed PrintedCircuit-Board Layout. Rev. 0 | Page 12 of 16 ADA4310-1 OUTLINE DIMENSIONS 3.00 BSC EXPOSED PAD 6 10 TOP VIEW 3.00 BSC 1 4.90 BSC 2.50 SQ 0.75 5 PIN 1 BOTTOM VIEW 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.33 0.17 SEATING PLANE 0.80 0.60 0.40 8° 0° 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA-T Figure 22. 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] (RH-10) Dimensions shown in millimeters 4.00 BSC SQ 0.60 MAX 0.60 MAX PIN 1 INDICATOR 0.65 BSC TOP VIEW 12° MAX 0.75 0.60 0.50 13 12 16 PIN 1 INDICATOR 1 2.25 2.10 SQ 1.95 EXPOSED PAD 9 8 5 4 0.25 MIN 1.95 BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.35 0.30 0.25 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC 010606-0 1.00 0.85 0.80 3.75 BSC SQ (BOTTOM VIEW) Figure 23. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters ORDERING GUIDE Model ADA4310-1ARHZ-RL1 ADA4310-1ARHZ-R71 ADA4310-1ARHZ1 ADA4310-1ACPZ-RL1 ADA4310-1ACPZ-R21 ADA4310-1ACPZ-R71 1 Temperature Package −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Z = Pb-free part. Rev. 0 | Page 13 of 16 Package Option RH-10 RH-10 RH-10 CP-16-4 CP-16-4 CP-16-4 Branding 0L 0L 0L ADA4310-1 NOTES Rev. 0 | Page 14 of 16 ADA4310-1 NOTES Rev. 0 | Page 15 of 16 ADA4310-1 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06027-0-10/06(0) Rev. 0 | Page 16 of 16