PAC5250

PRODUCT DATA SHEET
PAC5250
Power Application Controller TM
Multi-Mode Power ManagerTM
Configurable Analog Front EndTM
Application Specific Power DriversTM
ARM® CortexTM-M0 Controller Core
www.active-semi.com
Copyright © 2016 Active-Semi, Inc.
PAC5250
Power Application Controller
TABLE OF CONTENTS
1. General Description........................................................................................................................................... 7
2. PAC Family Applications.................................................................................................................................... 8
3. Product Selection Summary............................................................................................................................... 9
4. Ordering Information.......................................................................................................................................... 9
5. PAC5250 Features........................................................................................................................................... 10
6. Absolute Maximum Ratings.............................................................................................................................. 11
7. Architectural Block Diagram............................................................................................................................. 12
8. Pin Configuration.............................................................................................................................................. 13
8.1. PAC5250QF............................................................................................................................................. 13
9. Pin Description................................................................................................................................................. 14
10. Multi-Mode Power Manager (MMPM)............................................................................................................ 20
10.1. Features................................................................................................................................................. 20
10.2. Block Diagram........................................................................................................................................ 20
10.3. Functional Description............................................................................................................................ 20
10.3.1. Multi-Mode Switching Supply (MMSS) Controller...........................................................................20
10.3.2. Linear Regulators........................................................................................................................... 22
10.3.3. Power Up Sequence...................................................................................................................... 23
10.3.4. Hibernate Mode.............................................................................................................................. 23
10.3.5. Power and Temperature Monitor.................................................................................................... 24
10.3.6. Voltage Reference.......................................................................................................................... 24
10.4. Electrical Characteristics........................................................................................................................ 25
10.5. Typical Performance Characteristics...................................................................................................... 28
11. Configurable Analog Front End (CAFE).......................................................................................................... 29
11.1. Block Diagram........................................................................................................................................ 29
11.2. Functional Description............................................................................................................................ 30
11.2.1. Differential Programmable Gain Amplifier (DA)..............................................................................30
11.2.2. Single-Ended Programmable Gain Amplifier (AMP).......................................................................30
11.2.3. General Purpose Comparator (CMP)............................................................................................. 30
11.2.4. Phase Comparator (PHC).............................................................................................................. 30
11.2.5. Protection Comparator (PCMP)...................................................................................................... 30
11.2.6. Analog Output Buffer (BUF)............................................................................................................ 31
11.2.7. Analog Front End I/O (AIO)............................................................................................................ 31
11.2.8. Push Button (PBTN)....................................................................................................................... 31
11.2.9. HP DAC and LP DAC..................................................................................................................... 31
11.2.10. ADC Pre-Multiplexer..................................................................................................................... 31
11.2.11. Configurable Analog Signal Matrix (CASM)..................................................................................31
11.2.12. Configurable Digital Signal Matrix (CDSM)...................................................................................31
11.3. Electrical Characteristics........................................................................................................................ 33
11.4. Typical Performance Characteristics...................................................................................................... 37
12. Application Specific Power Drivers (ASPD).................................................................................................... 38
12.1. Features................................................................................................................................................. 38
12.2. Block Diagram........................................................................................................................................ 38
12.3. Functional Description............................................................................................................................ 38
12.3.1. Low-Side Gate Driver..................................................................................................................... 39
12.3.2. Ultra-High-Voltage Gate Driver....................................................................................................... 39
12.3.3. High-Side Switching Transients...................................................................................................... 39
12.3.4. Open-Drain Drivers........................................................................................................................ 40
12.3.5. Power Drivers Control.................................................................................................................... 40
12.3.6. Gate Driver Fault Protection........................................................................................................... 41
12.4. Electrical Characteristics........................................................................................................................ 42
12.5. Typical Performance Characteristics...................................................................................................... 44
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PAC5250
Power Application Controller
13. ADC with Auto-Sampling Sequencer.............................................................................................................. 46
13.1. Block Diagram........................................................................................................................................ 46
13.2. Functional Description............................................................................................................................ 46
13.2.1. ADC................................................................................................................................................ 46
13.2.2. Auto-Sampling Sequencer............................................................................................................. 46
13.2.3. EMUX Control................................................................................................................................ 47
13.3. Electrical Characteristics........................................................................................................................ 47
14. Memory System............................................................................................................................................. 48
14.1. Features................................................................................................................................................. 48
14.2. Block Diagram........................................................................................................................................ 48
14.3. Functional Description............................................................................................................................ 48
14.3.1. Program and Data FLASH............................................................................................................. 48
14.3.2. SRAM............................................................................................................................................. 48
14.4. Electrical Characteristics........................................................................................................................ 49
15. Clock Control System..................................................................................................................................... 50
15.1. Features................................................................................................................................................. 50
15.2. Block Diagram........................................................................................................................................ 50
15.3. Functional Description............................................................................................................................ 51
15.3.1. Free Running Clock (FRCLK)........................................................................................................ 51
15.3.2. Fast Clock (FCLK).......................................................................................................................... 51
15.3.3. High-Speed Clock (HCLK)............................................................................................................. 51
15.3.4. Auxiliary Clock (ACLK)................................................................................................................... 51
15.3.5. Clock Gating................................................................................................................................... 51
15.3.6. Ring Oscillator (ROSC).................................................................................................................. 51
15.3.7. Trimmed 4MHz RC Oscillator......................................................................................................... 51
15.3.8. Internal Slow RC Oscillator............................................................................................................ 51
15.3.9. Crystal Oscillator Driver................................................................................................................. 51
15.3.10. External Clock Input..................................................................................................................... 51
15.3.11. PLL............................................................................................................................................... 51
15.4. Electrical Characteristics........................................................................................................................ 52
16. ARM Cortex-M0 Microcontroller Core............................................................................................................ 53
16.1. Features................................................................................................................................................. 53
16.2. Block Diagram........................................................................................................................................ 53
16.3. Functional Description............................................................................................................................ 53
16.4. Electrical Characteristics........................................................................................................................ 54
16.5. Typical Performance Characteristics...................................................................................................... 54
17. I/O Controller.................................................................................................................................................. 55
17.1. Features................................................................................................................................................. 55
17.2. Block Diagram........................................................................................................................................ 55
17.3. Functional Description............................................................................................................................ 55
17.4. Electrical Characteristics........................................................................................................................ 56
18. Serial Interface............................................................................................................................................... 57
18.1. Block Diagram........................................................................................................................................ 57
18.2. Functional Description............................................................................................................................ 57
18.2.1. I2C Controller.................................................................................................................................. 57
18.3. UART Controller..................................................................................................................................... 58
18.4. SPI Controller......................................................................................................................................... 58
18.5. Dynamic Characteristics........................................................................................................................ 59
19. Timers............................................................................................................................................................ 62
19.1. Block Diagram........................................................................................................................................ 62
19.2. Functional Description............................................................................................................................ 63
19.2.1. Timer A........................................................................................................................................... 63
19.2.2. Timer B........................................................................................................................................... 63
19.2.3. Timer C.......................................................................................................................................... 63
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PAC5250
Power Application Controller
19.2.4. Timer D.......................................................................................................................................... 64
19.2.5. Watchdog Timer............................................................................................................................. 64
19.2.6. SOC Bus Watchdog Timer............................................................................................................. 64
19.2.7. Wake-Up Timer.............................................................................................................................. 64
19.2.8. Real-Time Clock............................................................................................................................. 64
20. Thermal Characteristics................................................................................................................................. 65
21. Application Examples..................................................................................................................................... 66
22. Package Outline and Dimensions.................................................................................................................. 68
22.1. TQFN1010-57 Package Outline and Dimensions..................................................................................68
23. Legal Information........................................................................................................................................... 70
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PAC5250
Power Application Controller
LIST OF TABLES
Table 1. Product Selection Summary..................................................................................................................... 9
Table 2. Ordering Information................................................................................................................................. 9
Table 3. Absolute Maximum Ratings.................................................................................................................... 11
Table 4. Multi-Mode Power Manager and System Pin Description.......................................................................14
Table 5. Configurable Analog Front End Pin Description......................................................................................15
Table 6. Application Specific Power Drivers Pin Description................................................................................16
Table 7. I/O Ports Pin Description........................................................................................................................ 17
Table 8. I/O Ports Pin Description (Continued)..................................................................................................... 18
Table 9. Multi-Mode Switching Supply Controller Electrical Characteristics.........................................................25
Table 10. Linear Regulators Electrical Characteristics......................................................................................... 27
Table 11. Power System Electrical Characteristics............................................................................................... 27
Table 12. Differential Programmable Gain Amplifier (DA) Electrical Characteristics............................................33
Table 13. Single-Ended Programmable Gain Amplifier (AMP) Electrical Characteristics.....................................33
Table 14. General Purpose Comparator (CMP) Electrical Characteristics...........................................................34
Table 15. Phase Comparator (PHC) Electrical Characteristics.............................................................................34
Table 16. Protection Comparator (PCMP) Electrical Characteristics....................................................................34
Table 17. Analog Output Buffer (BUF) Electrical Characteristics..........................................................................34
Table 18. Analog Front End I/O (AIO) Electrical Characteristics...........................................................................36
Table 19. Push Button (PBTN) Electrical Characteristics.....................................................................................36
Table 20. HP DAC and LP DAC Electrical Characteristics...................................................................................36
Table 21. Power Driver Resources by Part Number............................................................................................. 39
Table 22. Microcontroller Port and PWM to Power Driver Mapping......................................................................40
Table 23. Power Driver Delay Configuration......................................................................................................... 40
Table 24. Gate Drivers Electrical Characteristics................................................................................................. 42
Table 25. Open-Drain Drivers Electrical Characteristics.......................................................................................42
Table 26. Power Drivers Module Electrical Characteristics..................................................................................43
Table 27. ADC and Auto-Sampling Sequencer Electrical Characteristics.............................................................47
Table 28. Memory System Electrical Characteristics............................................................................................ 49
Table 29. Clock Control System Electrical Characteristics...................................................................................52
Table 30. Microcontroller and Clock Control System Electrical Characteristics....................................................54
Table 31. I/O Controller Electrical Characteristics................................................................................................56
Table 32. Serial Interface Dynamic Characteristics..............................................................................................59
Table 33. I2C Dynamic Characteristics................................................................................................................. 60
Table 34. Thermal Characteristics........................................................................................................................ 65
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PAC5250
Power Application Controller
LIST OF FIGURES
Figure 1-1. Power Application Controller................................................................................................................ 7
Figure 2-1. Simplified Application Diagram............................................................................................................ 8
Figure 7-1. Architectural Block Diagram............................................................................................................... 12
Figure 8-1. PAC5250QF Pin Configuration (TQFN1010-57 Package).................................................................13
Figure 9-1. Power Supply Bypass Capacitor Routing..........................................................................................19
Figure 10-1. Multi-Mode Power Manager............................................................................................................. 20
Figure 10-2. Buck Mode....................................................................................................................................... 21
Figure 10-3. Ultra-High-Voltage Buck Mode......................................................................................................... 21
Figure 10-4. AC/DC Flyback Mode....................................................................................................................... 22
Figure 10-5. Linear Regulators............................................................................................................................. 23
Figure 10-6. Power Up Sequence........................................................................................................................ 23
Figure 11-1. Configurable Analog Front End........................................................................................................ 29
Figure 12-1. Application Specific Power Drivers................................................................................................... 38
Figure 12-2. Typical Gate Driver Connections...................................................................................................... 39
Figure 12-3. High-Side Switching Transients and Optional Circuitry....................................................................40
Figure 13-1. ADC with Auto-Sampling Sequencer................................................................................................46
Figure 14-1. Memory System............................................................................................................................... 48
Figure 15-1. Clock Control System...................................................................................................................... 50
Figure 16-1. ARM Cortex-M0 Microcontroller Core.............................................................................................. 53
Figure 17-1. I/O controller.................................................................................................................................... 55
Figure 18-1. Serial Interface................................................................................................................................. 57
Figure 18-2. I2C Timing Diagram.......................................................................................................................... 61
Figure 19-1. Timers A, B, C, and D...................................................................................................................... 62
Figure 19-2. SOC Bus Watchdog and Wake-Up Timer........................................................................................63
Figure 19-3. Real-Time Clock and Watchdog Timer.............................................................................................63
Figure 21-1. 3-Phase Motor Using PAC5255 (Simplified Diagram)......................................................................66
Figure 21-2. Solar Micro-Inverter Using PAC5255 (Simplified Diagram)..............................................................66
Figure 21-3. Motor with LED Lighting Using PAC5255 (Simplified Diagram).......................................................67
Figure 22-1. TQFN1010-57.................................................................................................................................. 68
Table 22-1. Dimensions........................................................................................................................................ 68
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PAC5250
Power Application Controller
1. GENERAL DESCRIPTION
The PAC5250 belongs to Active-Semi's broad portfolio of full-featured Power Application Controller TM (PAC) products that
are highly optimized for controlling and powering next generation smart energy appliances, devices, and equipment. These
application controllers integrate a 50MHz ARM ® CortexTM-M0 32-bit microcontroller core with Active-Semi's proprietary
and patent-pending Multi-Mode Power ManagerTM, Configurable Analog Front EndTM, and Application Specific Power
DriversTM to form the most compact microcontroller-based power and general purpose application systems ranging from
digital power supply to motor control. The PAC52xx microcontroller features up to 32kB of embedded FLASH and 8kB of
SRAM memory, a high-speed 10-bit 1µs analog-to-digital converter (ADC) with dual auto-sampling sequencers,
5V/3.3V I/Os, flexible clock sources, timers, a versatile 14-channel PWM engine, and several serial interfaces.
The Multi-Mode Power Manager (MMPM) provides “all-in-one” efficient power management solution for multiple types
of power sources. It features a configurable multi-mode switching supply controller capable of operating in buck, flyback,
or boost mode, and up to four linear regulated voltage supplies. The Application Specific Power Drivers (ASPD) are highvoltage and ultra-high-voltage power drivers designed for each target set of control applications, including half bridge, Hbridge, 3-phase, intelligent power module (IPM), and general purpose driving. The Configurable Analog Front End (CAFE)
comprises differential programmable gain amplifiers, single-ended programmable gain amplifiers, comparators, digital-toanalog converters, and I/Os for programmable and inter-connectible signal sampling, feedback amplification, and sensor
monitoring of multiple analog input signals. Together, these modules and microcontroller enable a wide range of compact
applications with highly integrated power management, driving, feedback, and control for DC supply up to 52V and for line
AC supply.
Figure 1-1. Power Application Controller
SERIAL
INTERFACE
SPI, I22C, UART
PWM ENGINE
16-bit timers,
HW dead-time control,
10ns resolution control
50MHz ARM CORTEX-M0
MICROCONTROLLER CORE & MEMORY
1-cycle 32-bit multiplier,
24-bit RTC, 24-bit WDT, 24-bit SysTick, NVIC,
FLASH & SRAM
DATA ACQUISITION
& SEQUENCER
MULTI-MODE
POWER MANAGER
AC/DC, DC/DC,
linear regulators
APPLICATION
SPECIFIC POWER
DRIVERS
ultra-high voltage highside gate drivers,
low-side gate drivers,
MV open-drain drivers
CONFIGURABLE ANALOG FRONT END
3 differential PGAs,
4 single-ended PGAs,
10 Comparators,
2 DACs (10-bit & 8-bit),
Temperature monitor
10-bit 1µs ADC,
dual auto-sampling
sequencer
The PAC5250 is available in a 57-pin 10x10 TQFN package. The PAC family includes a range of part numbers optimized
to work with different targeted primary applications.
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Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
2. PAC FAMILY APPLICATIONS










General purpose high-voltage system controllers
Home appliances
Power tools
Motor controllers
LED lighting controllers
Uninterruptible power supply (UPS)
Solar micro-inverters
Wireless power controllers
Digital power controllers
Industrial applications
Figure 2-1. Simplified Application Diagram
PAC52xx
SPI/I2C/UART
PWM
ENGINE
MULTI-MODE
POWER
MANAGER
50MHz ARM CORTEX-M0
MICROCONTROLLER CORE
& MEMORY
APPLICATION
SPECIFIC
POWER
DRIVERS
SERIAL
INTERFACE
BUCK/
BOOST/
FLYBACK
M
MONITORING
SIGNALS
DATA
ACQUISITION
&
SEQUENCER
°C
CONFIGURABLE
ANALOG FRONT END
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Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
3. PRODUCT SELECTION SUMMARY
Table 1. Product Selection Summary
Int
+
Ext
50
32
8
25
SPI
I2C
UART
SWD
PRIMARY
APPLICATIO
N
XTAL
9
6 LS (1A/1A)
3 HS (0.25A/0.5A)
2 OD (23V/40mA)
INTERFACE
9
GPIO
2
SRAM (kB)
10
FLASH (kB)
4
MICROCONTROLLER
SPEED (MHz)
3
PROTECTFAULT
ADC CHANNEL
Y
PWM CHANNEL
DAC
5.252V
POWER DRIVER
COMPARATOR
57-pin
10x10
TQFN
PGA
PAC5250
DIFF-PGA
PIN
PKG
APPLICATION SPECIFIC
POWER DRIVERS
SWMULTI-MODE
PART
NUMBER
CONFIGURABLE
ANALOG FRONT
END
INPUT VOLTAGE
POWER
MANAGER
Y
UHV
3 half bridge,
3-phase control
Notes: DIFF-PGA = differential programmable gain amplifier, GD = gate driver, HS = high-side , LS = low-side, OD = open-drain driver,
PGA = programmable gain amplifier, UHV = ultra-high-voltage.
4. ORDERING INFORMATION
Table 2. Ordering Information
(1)
PART NUMBER(1)
TEMPERATURE RANGE
PACKAGE
PINS
PACKING
PAC5250QF
-40°C to 105°C
TQFN1010-57
57 + Exposed Pad
Tray
See Product Selection Summary for product features for each part number.
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PAC5250
Power Application Controller
5. PAC5250 FEATURES
 Proprietary Multi-Mode Power Manager
 Multi-mode switching supply controller configurable as high-voltage or ultra-high-voltage buck, AC/DC or
flyback
 DC supply up to 52V or line AC input
 4 linear regulators with power and hibernate management
 Power and temperature monitor, warning, and fault detection
 Proprietary Configurable Analog Front End
 10 analog front end I/O pins
 3 differential programmable gain amplifiers
 4 single-ended programmable gain amplifiers
 10 comparators
 2 DACs (10-bit and 8-bit)
 Proprietary Application Specific Power Drivers
 6 low-side and 3 600V high-side gate drivers
 1A/1A low-side, 0.25A/0.5A high-side, gate driving capability
 2 23V/40mA open-drain drivers
 Configurable delays and fast fault protection
 50MHz ARM Cortex-M0 32-bit microcontroller core
 Fast single cycle 32-bit x 32-bit multiplier
 24-bit SysTick timer
 Nested vectored interrupt controller (NVIC) with 20 external interrupts
 Wake-up interrupt controller allowing power-saving sleep modes
 Clock-gating allowing low power operation
 32kB FLASH and 8kB SRAM memory
 10-bit 1µs ADC with multi-input/multi-sample control engine
 9 ADC inputs including input from configurable analog front end
 3.3V I/Os
 2 general purpose I/Os with tri-state, and dedicated analog input to ADC
 True 5V I/Os
 13 general purpose I/Os with tri-state, pull-up and pull-down and dedicated I/O supply
 Configurable between true 5V and 3.3V I/Os
 Flexible clock and PLL from internal 2% oscillator, ring oscillator, external clock, or crystal
 9 timing generators
 Four 16-bit timers with up to 16 PWM/CC blocks and 7 independent dead-time controllers
 24-bit watchdog timer
 4s or 8s watchdog timer
 24-bit real time clock
 24-bit SysTick timer
 Wake-up timer for sleep modes from 0.125s to 8s
 SPI, I2C, and UART communication interfaces
 SWD debug interface with interface disable function
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Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
6. ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings
(Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect device
reliability.)
VALUE
UNIT
VHM, DRM to VSSP
PARAMETER
-0.3 to 54
V
VP to VSS
-0.3 to 20
V
-0.3 to VP + 0.3
V
-0.3 to 6
V
VCC33 to VSS
-0.3 to 4.1
V
VCC18 to VSS
-0.3 to 2.5
V
AIOx/.. (except AIO6/..), VCCIO, CLKOUT/ENHS2 to VSS
-0.3 to VSYS + 0.3
V
PDx/.., PEx/.. to VSS
-0.3 to VCCIO + 0.3
V
XIN, XOUT to VSS
-0.3 to VCC18 + 0.3
V
PCx/.. to VSSA
-0.3 to VCC33 + 0.3
V
DRLx to VSSP
-0.3 to VP + 0.3
V
DXBx to VSSP
-0.3 to 630
V
DXSx to VSSP
-11 to 610
V
DXSx allowable offset slew rate (dVDXSx/dt)
-50 to 50
V/ns
DXBx, DXHx to respective DXSx
-0.3 to 22
V
OMx to VSSP
-0.3 to 24
V
-0.3 to 0.3
V
0.2
ARMS
0.4
ARMS
CSM, REGO to VSS
VSYS, AIO6/.. to VSS
VSSP, VSSA to VSS
VSS, VSYS, DRM, DRLx, DXHx, REGO, OMx RMS current
VSSP RMS current
VP RMS current
(1)
(1)
(1)
0.6
ARMS
-40 to 105
°C
Human body model (JEDEC)
2
kV
Charge device model (JEDEC)
800
V
Machine model (JEDEC)
200
V
Operating temperature range
Electrostatic discharge (ESD)
(1)
Peak current can be 10 times higher than RMS value for pulses shorter than 10µs.
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Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
7. ARCHITECTURAL BLOCK DIAGRAM
Figure 7-1. Architectural Block Diagram
PAC5250
Power Application Controller
MULTI-MODE POWER
MANAGER
MULTIMODE
SWITCHING
SUPPLY
SWDIO, SWDCL
VHM
DRM
VP
CSM
VSSP, VSS, VSSA
DEBUG
32kB/16kB
FLASH
AHB/APB
XIN, XOUT
PAC SOC BUS
ARM
CORTEX-M0
CORE
8kB/4kB
SRAM
CLOCK
CONTROL
LINEAR
REGULATORS
(4)
APPLICATION SPECIFIC
POWER DRIVERS
OD (2)
OM0
OM2
PWM ENGINE
TIMERS (4)
DXBx
HSGD (3)
PWMAx, PWMBx,
PWMCx, PWMDx
REGO
VSYS
VCCIO
VCC33
VCC18
DXHx
DXSx
PWM /
CC (14)
ENHS2
RTC
LSGD (6)
DEAD TIME
(7)
PCx, PDx, PEx
DRLx
GPIO (15)
CONFIGURABLE
ANALOG FRONT END
BRIDGE
SPICSx, SPIMISO,
SPIMOSI, SPICLK
PGA/
CMP (4)
SPI
AMPx/CMPx/PHCx
WATCHDOG
I2CSDA, I2CSCL
DAC (2)
I2C
UARTRX, UARTTX
UART
10-BIT
ADC
MUX
DATA ACQUISITION &
SEQUENCER
DIFF-PGA/
PCMP (3)
DAxP/PCMPx
DAxN
ADx
nRESET1
SYSTEM
CONTROL
AUTO
SAMPLING
- 12 -
AIO
CONTROL
(10)
AIOx
BUF6
PBTN
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
8. PIN CONFIGURATION
8.1. PAC5250QF
43 PD6/PWMA7/PWMB1
44 PD5/PWMA5/PWMC1
45 PD4/PWMD1
46 PD3/PWMA5/PWMA7/PWMB1
47 PD2/PWMA3/PWMA4/PWMB0
48 PD1/SWDCL/EXTCLK
49 PD0/SWDIO
50 PE0/SPICLK
51 PE1/SPIMOSI/UARTTX
52 PE2/SPIMISO/UARTRX
53 PE3/SPICS0/nRESET1
54 PE4/SPICS1/I2CSCL
55 PE5/SPICS2/I2CSDA
56 VCCIO
57 XIN
Figure 8-1. PAC5250QF Pin Configuration (TQFN1010-57 Package)
XOUT 1
VCC18 2
PC3/AD3 3
42 DXB2
PC2/AD2 4
41 DXH2
VCC33 5
40 DXS2
VSSA 6
VSS 7
AIO0/DA0N 8
AIO1/DA0P/PCMP0 9
AIO2/DA1N 10
PAC5250QF
39 DXB1
TQFN1010-57
38 DXH1
AIO3/DA1P/PCMP1 11
37 DXS1
EP (VSS)
AIO4/DA2N 12
AIO5/DA2P/PCMP2 13
AIO6/AMP6/CMP6/BUF6/PBTN 14
AIO7/AMP7/CMP7/PHC7 15
36 DXB0
AIO8/AMP8/CMP8/PHC8 16
35 DXH0
AIO9/AMP9/CMP9/PHC9 17
34 DXS0
- 13 -
DRL5 33
OM2 31
DRL4 32
DRL3 29
CLKOUT/ENHS2 30
OM0 28
DRL2 27
DRL1 26
VSSP 24
DRL0 25
DRM 23
VHM 22
VP 21
CSM 20
REGO 19
VSYS 18
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
9. PIN DESCRIPTION
Table 4. Multi-Mode Power Manager and System Pin Description
PIN NAME
PIN NUMBER
TYPE
CSM
20
Analog
Switching supply current sense input. Connect to the positive side of the current sense
resistor.
DRM
23
Analog
Switching supply driver output. Connect to the base or gate of the external power NPN or
n-channel MOSFET. See PAC User Guide and application notes.
EP (VSS)
EP
Power
Exposed pad. Must be connected to VSS in a star ground configuration. Connect to a large
PCB copper area for power dissipation heat sinking.
REGO
19
Power
System regulator output. Connect to VSYS directly or through an external power-dissipating
resistor.
VCC18
2
Power
Internally generated 1.8V core power supply. Connect a 2.2μF or higher value ceramic
capacitor from VCC18 to VSSA. See Figure 9-1. Power Supply Bypass Capacitor Routing
below.
VCC33
5
Power
Internally generated 3.3V power supply. Connect a 2.2μF or higher value ceramic capacitor
from VCC33 to VSSA. See PCB layout note below.
VCCIO
56
Power
Internally generated digital I/O power supply. Connect a 4.7μF or higher value ceramic
capacitor from VCCIO to VSSA. See Figure 9-1. Power Supply Bypass Capacitor Routing
below.
Power
Switching supply controller supply input. Connect a 1μF or higher value ceramic capacitor,
or a 0.1μF ceramic capacitor in parallel with a 10μF or higher electrolytic capacitor from
VHM to VSSP. This pin requires good capacitive bypassing to VSSP, so the ceramic capacitor
must be connected with a shorter than 10mm trace from the pin. See Figure 9-1. Power
Supply Bypass Capacitor Routing below.
VHM
22
DESCRIPTION
VP
21
Power
Main power supply. Provides power to the power drivers as well as voltage feedback path
for the switching supply. Connect a properly sized supply bypass capacitor in parallel with
a 0.1μF ceramic capacitor from VP pin to VSS for voltage loop stabilization. This pin
requires good capacitive bypassing to VSS, so the ceramic capacitor must be connected with
a shorter than 10mm trace from the pin. See See Figure 9-1. Power Supply Bypass
Capacitor Routing below.
VSS
7
Power
Ground.
VSSA
6
Power
Analog ground. Connect to VSS in a star ground configuration.
VSSP
24
Power
Power ground. Connect to VSS in a star ground configuration.
VSYS
18
Power
5V system power supply. Connect a 4.7μF or higher value ceramic capacitor from V SYS to
VSSP. See Figure 9-1. Power Supply Bypass Capacitor Routing below.
XIN
57
Analog
Crystal oscillator driver input. Leave floating if unused.
XOUT
1
Analog
Crystal oscillator driver output. Leave floating if unused.
- 14 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Table 5. Configurable Analog Front End Pin Description
PIN NAME
AIO0/DA0N
AIO1/DA0P/PCMP0
AIO2/DA1N
AIO3/DA1P/PCMP1
AIO4/DA2N
AIO5/DA2P/PCMP2
AIO6/AMP6/CMP6/BUF6/PBTN
AIO7AMP7/CMP7/PHC7
AIO8/AMP8/CMP8/PHC8
AIO9/AMP9/CMP9/PHC9
PIN NUMBER
FUNCTION
TYPE
DESCRIPTION
AIO0
I/O
DA0N
Analog
AIO1
I/O
DA0P
Analog
Differential PGA 0 positive input.
PCMP0
Analog
Protection comparator input 0.
8
9
Analog front end I/O 0.
Differential PGA 0 negative input.
Analog front end I/O 1.
AIO2
I/O
DA1N
Analog
AIO3
I/O
DA1P
Analog
Differential PGA 1 positive input.
PCMP1
Analog
Protection comparator input 1.
10
11
Analog front end I/O 2.
Differential PGA 1 negative input.
Analog front end I/O 3.
AIO4
I/O
DA2N
Analog
AIO5
I/O
DA2P
Analog
Differential PGA 2 positive input.
PCMP2
Analog
Protection comparator input 2.
12
13
14
15
16
17
- 15 -
Analog front end I/O 4.
Differential PGA 2 negative input.
Analog front end I/O 5.
AIO6
I/O
AMP6
Analog
Analog front end I/O 6.
PGA input 6.
CMP6
Analog
Comparator input 6.
BUF6
Analog
Buffer output 6.
PBTN
Analog
Push button input.
AIO7
I/O
AMP7
Analog
Analog front end I/O 7.
PGA input 7.
CMP7
Analog
Comparator input 7.
PHC7
Analog
Phase comparator input 7.
AIO8
I/O
AMP8
Analog
PGA input 8.
CMP8
Analog
Comparator input 8.
PHC8
Analog
Phase comparator input 8.
AIO9
I/O
AMP9
Analog
PGA input 9.
CMP9
Analog
Comparator input 9.
PHC9
Analog
Phase comparator input 9.
Analog front end I/O 8.
Analog front end I/O 9.
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Table 6. Application Specific Power Drivers Pin Description
PIN NAME
PIN NUMBER
TYPE
DESCRIPTION
DRL0
25
Analog
Low-side gate driver 0.
DRL1
26
Analog
Low-side gate driver 1.
DRL2
27
Analog
Low-side gate driver 2.
DRL3
29
Analog
Low-side gate driver 3.
DRL4
32
Analog
Low-side gate driver 4.
DRL5
33
Analog
Low-side gate driver 5.
DXB0
36
Analog
Ultra-high-voltage high-side gate driver bootstrap 0.
DXB1
39
Analog
Ultra-high-voltage high-side gate driver bootstrap 1.
DXB2
42
Analog
Ultra-high-voltage high-side gate driver bootstrap 2.
DXH0
35
Analog
Ultra-high-voltage high-side gate driver 0.
DXH1
38
Analog
Ultra-high-voltage high-side gate driver 1.
DXH2
41
Analog
Ultra-high-voltage high-side gate driver 2.
DXS0
34
Analog
Ultra-high-voltage high-side gate driver source 0.
DXS1
37
Analog
Ultra-high-voltage high-side gate driver source 1.
DXS2
40
Analog
Ultra-high-voltage high-side gate driver source 2.
ENHS2
30
O
OM0
28
OD
Medium-voltage open-drain driver 0.
OM2
31
OD
Medium-voltage open-drain driver 2.
High-side driver group 2 control enable output.
- 16 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Table 7. I/O Ports Pin Description
PIN NAME
PIN NUMBER
PC2/AD2
4
PC3/AD3
3
PD0/SWDIO
49
PD1/SWDCL/EXTCLK
PD2/PWMA3/PWMA4/PWMB0
PD3/PWMA5/PWMA7/PWMB1
PD4/PWMD1
PD5/PWMA5/PWMC1
PD6/PWMA7/PWMB1
PE0/SPICLK
PE1/SPIMOSI/UARTTX
PE2/SPIMISO/UARTRX
FUNCTION
46
45
44
43
PC2
I/O
I/O port C2.
Analog
ADC input 2.
PC3
I/O
I/O port C3.
AD3
Analog
ADC input 3.
PD0
I/O
I/O port D0.
SWDIO
I/O
Serial wire debug I/O.
PD1
I/O
I/O port D1.
SWDCL
I
Serial wire debug clock.
EXTCLK
I
External clock.
PD2
I/O
I/O port D2.
PWMA3
I/O
Timer A PWM/capture 3.
PWMA4
I/O
Timer A PWM/capture 4.
PWMB0
I/O
Timer B PWM/capture 0.
PD3
I/O
I/O port D3.
PWMA5
I/O
Timer A PWM/capture 5.
PWMA7
I/O
Timer A PWM/capture 7.
PWMB1
I/O
Timer B PWM/capture 1.
PD4
I/O
I/O port D4.
PWMD1
I/O
Timer D PWM/capture 1.
PD5
I/O
I/O port D5.
PWMA5
I/O
Timer A PWM/capture 5.
PWMC1
I/O
Timer C PWM/capture 1.
PD6
I/O
I/O port D6.
PWMA7
I/O
Timer A PWM/capture 7.
PWMB1
I/O
Timer B PWM/capture 1.
PE0
I/O
I/O port E0.
SPICLK
I/O
SPI clock.
PE1
I/O
I/O port E1.
SPIMOSI
I/O
SPI master out slave in (MOSI).
UARTTX
O
50
51
52
DESCRIPTION
AD2
48
47
TYPE
UART transmit output.
PE2
I/O
I/O port E2.
SPIMISO
I/O
SPI master in slave out (MISO).
UARTRX
I
- 17 -
UART receive input.
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Table 8. I/O Ports Pin Description (Continued)
PIN NAME
PE3/SPICS0/nRESET1
PE4/SPICS1/I2CSCL
PE5/SPICS2/I2CSDA
PIN NUMBER
FUNCTION
TYPE
PE3
I/O
SPICS0
O
SPI chip select 0.
nRESET1
I
Reset input 1 (active low).
53
54
55
- 18 -
DESCRIPTION
I/O port E3.
PE4
I/O
SPICS1
O
I/O port E4.
I2CSCL
I/O
I2C clock.
PE5
I/O
I/O port E5.
SPICS2
O
I2CSDA
I/O
SPI chip select 1.
SPI chip select 2.
I2C data.
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Figure 9-1. Power Supply Bypass Capacitor Routing
- 19 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
10. MULTI-MODE POWER MANAGER (MMPM)
10.1. Features




Multi-mode switching supply controller configurable as high voltage or ultra-high-voltage buck, flyback AC/DC
DC supply up to 52V or line AC input
4 linear regulators with power and hibernate management
Power and temperature monitor, warning, and fault detection
10.2. Block Diagram
Figure 10-1. Multi-Mode Power Manager
MULTI-MODE POWER MANAGER
MULTI-MODE SWITCHING
SUPPLY CONTROLLER
COMP &
CURR LIMIT
START UP &
MODE CTRL
CLAMP
POWER
OK & OVP
ERROR
COMP
IMOD
DAC
PWM
LOGIC
CURR
SENSE
DRM
DRIVER
VSSP
MUX
VOLTAGE
SETTING
VP
VHM
ERROR
AMP
MUX
1.2V
REGO
SYSTEM
SUPPLY
REG
TIMERS
LINEAR
REG
LINEAR
REG
LINEAR
REG
VSYS
VCCIO
VCC33
HIBERNATE
2.5V VREF
VTHREF
POWER
& TEMP
MON
MUX
CSM
VSSA
VMON
VTEMP
VSS
VCC18
10.3. Functional Description
The Multi-Mode Power Manager (Figure 10-1) is optimized to efficiently provide "all-in-one" power management required
by the PAC and associated application circuitry from a wide range of input power sources. It incorporates a dedicated multimode switching supply (MMSS) controller operable as a buck, flyback, or boost converter to efficiently convert power
from a DC or AC input source to generate a main supply output V P. Four linear regulators provide V SYS, VCCIO, VCC33, and
VCC18 supplies for 5V system, 5V or 3.3V I/O, 3.3V mixed signal, and 1.8V microcontroller core circuitry. The power
manager also handles system functions including internal reference generation, timers, hibernate mode management, and
power and temperature monitoring.
10.3.1. Multi-Mode Switching Supply (MMSS) Controller
The MMSS controller drives an external power transistor for pulse-width modulation switching of an inductor or
transformer for power conversion. The DRM output drives the gate of the n-channel MOSFET or the base of the NPN
between the VHM on state and VSSP off state at proper duty cycle and switching frequency to ensure that the main supply
voltage VP is regulated. The VP regulation voltage is initially set to 12V during start up, and can be reconfigured to be 5V,
- 20 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
9V, or 15V by the microcontroller after initialization 1. When VP is lower than the target regulation voltage, the internal
feedback control circuitry causes the inductor current to increase to raise V P. Conversely, when VP is higher than the
regulation voltage, the feedback loop control causes the inductor current to decrease to lower V P. The feedback loop is
internally stabilized. The output current capability of the switching supply is determined by the external current sense
resistor. In the high-side current sense buck mode, the inductor current signal is sensed differentially between the CSM pin
and VP, and has a peak current limit threshold of 0.26V. In the low-side current sense flyback or boost mode, the inductor
current signal is sensed differentially between the CSM pin and VSSP, and has a peak current limit threshold of 1V.
The MMSS controller is flexible and configurable as a buck, flyback, or boost converter. Input sources include battery
supply for buck mode (Figure 10-2), and AC line supply voltage range for ultra-high-voltage buck mode (Figure 10-3),
AC/DC flyback mode (Figure 10-4). The MMSS controller operational mode is determined by external configuration and
register setting from the microcontroller after power up. It can operate in either high-side or low-side current sense mode,
and does not require external feedback loop compensation circuitry. For optional extended application range, the MMSS
also incorporates additional digital control by the microcontroller to add accurate computations for outer feedback loop
control such as power factor correction and accurate current control.
Figure 10-2. Buck Mode
VHM
VIN
PAC52xx
PAC5250
DRM
VP (12V default)
CSM
VP
Figure 10-3. Ultra-High-Voltage Buck Mode
VHM
VAC (120V/230V)
PAC5250
DRM
VP (12V default)
CSM
VP
1
Note that on any device with ultra-high voltage drivers (PAC525X), it is invalid to set VP to less than 12V.
- 21 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Figure 10-4. AC/DC Flyback Mode
VHM
VAC (120V/230V)
PAC5250
VP
DRM
CSM
VP (12V default)
The MMSS detects and selects between high-side and low-side mode during start up based on the placement of the current
sense resistor and the CSM pin voltage. It employs a safe start up mode with 9.5kHz switching frequency until V P exceeds
4.3V under-voltage-lockout threshold, then transitions to the 45kHz default switching frequency for at least 6ms to bring V P
close to the target voltage, before enabling the linear regulators. Any extra load should only be applied after the supplies are
available and the microprocessor has initialized. The switching frequency can be reconfigured by the microprocessor to be
181kHz to 500kHz in the high switching frequency mode for battery-based applications, and to be 45kHz to 125kHz in the
low switching frequency mode for AC applications. Upon initialization, the microcontroller must reconfigure the MMSS to
the desired settings for VP regulation voltage, switching mode, switching frequency, and V HM clamp. Refer to the PAC
application notes and user guide for MMSS controller design and programming.
If a stable external 4.5V to 18V power source is available, it can power the V P main supply and all the linear regulators
directly without requiring the MMSS controller to operate. In such applications, V HM can be connected directly to VP and
the microcontroller should disable the MMSS upon initialization to reduce power loss.
10.3.2. Linear Regulators
The MMPM includes up to four linear regulators. The system supply regulator is a medium voltage regulator that takes the
VP supply and sources up to 200mA at REGO until V SYS, externally coupled to REGO, reaches 5V. This allows a properly
rated external resistor to be connected from REGO to V SYS to close the current loop and offload power dissipation between
VP and VSYS. Once VSYS is above 4V, the three additional 40mA linear regulators for V CCIO, VCC33, and VCC18 supplies
sequentially power up. Figure 10-5 shows typical circuit connections for the linear regulators. For 5V I/O systems, short the
VCCIO pin to VSYS to bypass the VCCIO regulator. For 3.3V I/O systems, the VCCIO regulator generates 3.3V. The VCC33 and
VCC18 regulators generate 3.3V and 1.8V, respectively. When V SYS, VCCIO, VCC33, and VCC18 are all above their respective
power good threshold, and the configurable power on reset duration has expired, the microcontroller is initialized.
- 22 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Figure 10-5. Linear Regulators
VP
VP (12V typical)
PAC5250
VSYS & VCCIO (5V)
REGO
VSYS
VCCIO
4.7µF
(1)
VCC33
VCC18
VSS
VSSA
1µF
1µF
(1)
5V I/O connection shown.
Connect instead to a 4.7µF
capacitor for 3.3V I/O.
10.3.3. Power Up Sequence
The MMPM follows a typical power up sequence as in the Figure 10-6 below. A typical sequence begins with input power
supply being applied, followed by the safe start up and start up durations to bring the switching supply output V P to 12V,
before the linear regulators are enabled. When all the supplies are ready, the internal clocks become available, and the
microcontroller starts executing from the program memory. During initialization, the microcontroller can reconfigure the
switching supply to a different VP regulation voltage such as 15V and to an appropriate switching frequency and switching
mode. The total loading on the switching supply must be kept below 25% of the maximum output current until after the
reconfiguration of the switching supply is complete. For AC input supply applications, the start up sequence includes an
additional charging time for VHM depending on the start-up resistor and capacitor values.
Figure 10-6. Power Up Sequence
Safe start up
Start up
Regulators
enabled
Power-onreset delay
Reconfiguration by firmware
System operation
SOC.PWRCFG.TRESET + 10.5 ms
(default: 32ms + 10.5ms = 42.5ms)
6ms
VIN or VHM
VIN or VHM
14.8V
VP (5V/12V/15V)
VP (start up default)
VP
VSYS and VCCIO
4.3V
VSYS and VCCIO (5V)
4V
VCC33 (3.3V)
VCC33
VCC18
VCC18 (1.8V)
76%
Internal clocks
Power on reset
Microcontroller
reset
Microcontroller
initializing
Microcontroller
executing
10.3.4. Hibernate Mode
The IC can go into an ultra-low power hibernate mode via the microcontroller firmware or via the optional push button
(PBTN, see Push Button description in Configurable Analog Front End). In hibernate mode, only a minimal amount
(typically 18µA) of current is used by VHM, and the MMSS controller and all internal regulators are shut down to eliminate
power drain from the output supplies. The system exits hibernate mode after a wake-up timer duration (configurable from
125ms to 8s or infinite) has expired or, if push button enabled, after an additional push button event has been detected.
When exiting the hibernate mode, the power manager goes through the start up cycle and the microcontroller is
- 23 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
reinitialized. Only the persistent power manager status bits (resets and faults) are retained during hibernation.
10.3.5. Power and Temperature Monitor
Whenever any of the VSYS, VCCIO, VCC33, or VCC18 power supplies falls below their respective power good threshold voltage, a
fault event is detected and the microcontroller is reset. The microcontroller stays in the reset state until V SYS, VCCIO, VCC33,
and VCC18 supply rails are all good again and the reset time has expired. A microcontroller reset can also be initiated by a
maskable temperature fault event that occurs when the IC temperature reaches 170°C. The fault status bits are persistent
during reset, and can be read by the microcontroller upon re-initialization to determine the cause of previous reset.
A power monitoring signal VMON is provided onto the ADC pre-multiplexer for monitoring various internal power supplies.
VMON can be set to be VCC18, 0.4•VCC33, 0.4•VCCIO, 0.4•VSYS, 0.1•VREGO, 0.1•VP, 0.0333•VHM, or the internal compensation
voltage VCOMP for switching supply power monitoring.
For power and temperature warning, a VP low event at 77% of the regulation voltage and an IC temperature warning event
at 140°C are provided as maskable interrupts to the microcontroller. These warnings allow the microcontroller to safely
power down the system.
In addition to the temperature warning interrupt and fault reset, a temperature monitor signal VTEMP = 1.5 + 5.04e-3 • (T 25°C) (V) is provided onto the ADC pre-multiplexer for IC temperature measurement.
10.3.6. Voltage Reference
The reference block includes a 2.5V high precision reference voltage that provides the 2.5V reference voltage for the ADC,
the DACs, and the 4-level programmable threshold voltage VTHREF (0.1V, 0.2V, 0.5V, and 1.25V).
- 24 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
10.4. Electrical Characteristics
Table 9. Multi-Mode Switching Supply Controller Electrical Characteristics
(VHM = 24V, VP = 12V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Input Supply (VHM)
IHIB;VHM
VHM hibernate mode supply current
VHM, hibernate mode
18
36
µA
ISU;VHM
VHM start up supply current
VHM < VUVLOR;VHM
75
120
µA
IOP;VHM
VHM operating supply current
DRM floating
0.3
0.5
mA
VOP:VHM
VHM operating voltage range
5.2
52
V
VUVLOR;VHM
VHM under-voltage lockout rising
13.5
14.5
16
V
6.8
7.5
8.1
V
23
26.6
V
VUVLOF;VHM
VHM under-voltage lockout falling
VCLAMP;VHM
VHM clamp voltage
Clamp enabled, sink current = 100µA
ICLAMP;VHM
VHM clamp sink current limit
Clamp enabled
0.72
1.2
mA
Output Supply and Feedback (VP)
VREG;VP
VP output regulation voltage
Programmable to 5V, 9V, 12V, or 15V
Load = 0 to 500mA
-7
-1
5
%
kPOK;VP
VP power OK threshold
VP rising, hysteresis = 10%
82
87
92
%
kOVP;VP
VP over voltage protection threshold
VP rising, hysteresis = 15%
MMPM Controller Enabled
136
%
Switching Control
fSWMACC;DRM
Switching frequency accuracy
-10
10
High frequency mode, 8 settings
181
500
Low frequency mode, 8 settings
45
125
%
fSWM;DRM
Switching frequency programmable range
fSSU;DRM
Safe start up switching frequency
9.5
kHz
Minimum on time
440
nS
Low duty-cycle & Low-frequency mode
25
%
Low duty-cycle & High-frequency mode
440
nS
High duty-cycle mode
820
nS
tONMIN;DRM
tOFFMIN;DRM
Minimum off time
- 25 -
kHz
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Current Sense (CSM Pin)
VDET;CSM
CSM mode detection threshold
Rising, hysteresis = 50mV
0.40
0.55
0.69
V
VHSLIM;CSM
High-side current limit threshold
181kHz, duty = 25%, relative to VP
0.17
0.26
0.35
V
VLSLIM;CSM
Low-side current limit threshold
45kHz, duty = 25%
0.7
1
1.48
V
tBLANK;CSM
Current sense blanking time
VPROT;CSM
Low-side abnormal current sense
protection threshold
200
VP < 4.3V
0.8
VP > 4.3V
1.9
ns
V
Gate Driver Output (DRM Pin)
VHM−1.4
VOH;DRM
High-level output voltage
IDRM = -20mA
V
VOL;DRM
Low-level output voltage
IDRM = 20mA
IOH;DRM
High-level output source current
VDRM = VHM - 5V
-0.1
A
IOL;DRM
Low-level output sink current
VDRM = 5V
0.25
A
tPD;DRM
Strong pull down pulse width
High-side current sense mode
240
ns
0.6
- 26 -
V
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Table 10. Linear Regulators Electrical Characteristics
(VP = 12V and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
VOP;VP
VUVLO;VP
PARAMETER
CONDITIONS
VP operating voltage range
MIN
TYP
MAX
UNI
T
18
V
4.3
4.5
V
4.5
VP under-voltage-lockout threshold
VP rising, hysteresis = 0.2V
VP quiescent supply current
Power manager only, including IQ;VSYS
400
750
µA
IQ;VSYS
VSYS quiescent supply current
VCCIO, VCC33, and VCC18 regulators only
350
600
µA
VSYS
VSYS output voltage
Load = 10µA to 200mA
5
5.18
V
VCCIO
VCCIO output voltage
Load = 10mA
VCC33
VCC33 output voltage
VCC18
VCC18 output voltage
IQ;VP
4
4.8
VCCIO shorted to VSYS
VCCIO from regulator
VSYS
V
3.152
3.3
3.398
Load = 10mA
3.185
3.3
3.415
V
Load = 10mA
1.834
1.9
1.979
V
ILIM;VSYS
VSYS regulator current limit
220
330
mA
ILIM;VCCIO
VCCIO regulator current limit
45
80
mA
ILIM;VCC33
VCC33 regulator current limit
45
80
mA
ILIM;VCC18
VCC18 regulator current limit
45
80
mA
50
%
kSCFB
VDO;VSYS
VUVLO;VSYS
Short circuit current fold back
VSYS dropout voltage
VP=5V, ISYS =100mA
350
680
mV
VSYS under-voltage-lockout threshold
VSYS rising, hysteresis = 0.2V
3.5
4
4.4
V
kPOKIO
VCCIO Power OK threshold
VCCIO rising, hysteresis = 10%
75
82
89
%
kPOK33
VCC33 Power OK threshold
VCC33 rising, hysteresis = 10%
71
78
85
%
kPOK18
VCC18 Power OK threshold
VCC18 falling, hysteresis = 10%
58
66
74
%
MIN
TYP
MAX
UNI
T
TA = 25°C
2.487
2.5
2.513
TA = -40°C to 105°C
2.463
2.5
2.537
Table 11. Power System Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
VREF
PARAMETER
Reference voltage
CONDITIONS
VCC18
V
1
VSYS, VCCIO, VCC33
0.4
VP, VREGO
0.1
kMON
Power monitoring voltage (VMON)
coefficient
VTEMP
Temperature monitor voltage at 25°C
TA = 25°C, at ADC
kTEMP
Temperature monitor coefficient
At ADC
5.04
mV/K
TWARN
Over-temperature warning threshold
Hysteresis = 10°C
140
°C
TFAULT
Over-temperature fault threshold
Hysteresis = 10°C
170
°C
VHM
V/V
0.0333
- 27 -
1.475
1.5
1.540
V
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
10.5. Typical Performance Characteristics
(VP = 12V and TA = 25°C unless otherwise specified.)
Buck Mode Efficiency
vs. Output Current
50
70
VIN = 48V
60
50
40
30
20
0
0
100
0.1
0.2
0.3
0.4
40
50
60
0.30
0.5
1
1.5
2
0.20
0.15
RSTARTUP = 1MΩ
0.10
0.05
VP = 12V,
fSW;DRM = 45kHz
10
PACMMPM-004
PACMMPM-003
30
20
VP = 12V,
all regulators on
0.25
40
0
30
AC/DC Flyback Mode Standby Power
vs. Input Voltage
50
0
20
AC/DC Flyback Mode Efficiency
vs. Output Current
VAC = 230V
60
0
0.5
Input Voltage (V)
80
70
20
Output Current (A)
VAC = 120V
90
30
10
VP = 12V,
fSW;DRM = 181kHz
10
Efficiency (%)
40
Input Power (W)
Efficiency (%)
80
PACMMPM-002
PACMMPM-001
VIN = 24V
90
Input Current (µA)
100
Buck Mode Hibernate Input Current
vs. Input Voltage
RSTARTUP = 2MΩ
0
2.5
90
135
180
225
270
Input Voltage (VAC)
Output Current (A)
DRM Driver Output
On Resistance vs. Temperature
PACMMPM-005
80
On Resistance (Ω)
70
60
50
40
Pull up
30
20
Pull down
10
0
-40
0
40
80
120
Temperature (°C)
- 28 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
11. CONFIGURABLE ANALOG FRONT END (CAFE)
11.1. Block Diagram
Figure 11-1. Configurable Analog Front End
CONFIGURABLE ANALOG FRONT END
LP DAC
DIFF-PGA & PCOMP
INT1
PROTECT
HP DAC
ADC PRE-MUX
DAxN
MUX
S/H
DAxP/PCMPx
MUX
MUX
AMPx
BUF6
COMPARATOR
MUX
VTHREF
MUX
CMPx
DINx
VTEMP, VMON, VREF/2
VSYS
VSYS
AFE I/O
I/O
CONTROL
AIOx
MUX
(except AIO6)
ADC MUX
CONFIGURABLE DIGITAL SIGNAL MATRIX
PGA
CONFIGURABLE ANALOG SIGNAL MATRIX
OFFSET
CAL
PR1, PR2
DINx
PHASE COMPARATOR
PHCx
DINx
PBTN
PUSH
BUTTON
MUX
PHASE
REF
MUX
3V
- 29 -
PHASE
POS
INT2/POS
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
11.2. Functional Description
The device includes a Configurable Analog Front End (CAFE, Figure 11-1) accessible through up to 10 analog and I/O
pins. These pins can be configured to form flexible interconnected circuitry made up of up to 3 differential programmable
gain amplifiers, 4 single-ended programmable gain amplifiers, 4 general purpose comparators, 3 phase comparators, 10
protection comparators, and one buffer output. These pins can also be programmed as analog feed-through pins, or as
analog front end I/O pins that can function as digital inputs or digital open-drain outputs. The PAC proprietary configurable
analog signal matrix (CASM) and configurable digital signal matrix (CDSM) allow real time asynchronous analog and
digital signals to be routed in flexible circuit connections for different applications. A push button function is provided for
optional push button on, hibernate, and off power management function.
11.2.1. Differential Programmable Gain Amplifier (DA)
The DAxP and DAxN pin pair are positive and negative inputs, respectively, to a differential programmable gain amplifier.
The differential gain can be programmable to be 1x, 2x, 4x, 8x, 16x, 32x, and 48x for zero ohm signal source impedance.
The differential programmable gain amplifier has -0.3V to 3.5V input common mode range, and its output can be
configured for routing directly to the ADC pre-multiplexer, or through a sample-and-hold circuit synchronized with the
ADC auto-sampling mechanism. Each differential amplifier is accompanied by offset calibration circuitry, and two
protection comparators for protection event monitoring. The programmable gain differential amplifier is optimized for use
with signal source impedance lower than 500Ω and with matched source impedance on both positive and negative
inputs for minimal offset. The effective gain is scaled by 13.5k / (13.5k + RSOURCE), where RSOURCE is the matched
source impedance of each input.
11.2.2. Single-Ended Programmable Gain Amplifier (AMP)
Each AMPx input goes to a single-ended programmable gain amplifier with signal relative to V SSA. The amplifier gain can
be programmed to be 1x, 2x, 4x, 8x, 16x, 32x, and 48x, or as analog feed-through. The programmable gain amplifier output
is routed via a multiplexer to the configurable analog signal matrix CASM.
11.2.3. General Purpose Comparator (CMP)
The general purpose comparator takes the CMPx input and compares it to either the programmable threshold voltage
(VTHREF) or a signal from the configurable analog signal matrix CASM. The comparator has 0V to V SYS input common mode
range, and its polarity-selectable output is routed via a multiplexer to either a data input bit or the configurable digital signal
matrix CDSM. Each general purpose comparator has two mask bits to prevent or allow rising or falling edge of its output to
trigger second microcontroller interrupt INT2, where INT2 can be configured to activate protection event PR1. Each
comparator output, routed via CASM and with 500ns de-glitch time, can also be configured to activate protection event
PR1.
11.2.4. Phase Comparator (PHC)
The phase comparator takes the PHCx input and compares it to either the programmable threshold voltage (V THREF) or a
signal from the configurable analog signal matrix CASM. The comparison signal can be set to a phase reference signal
generated by averaging the PHCx input voltages. In a three-phase motor control application, the phase reference signal acts
as a virtual center tap for BEMF detection. The PHCx inputs are optionally fed through to the CASM. The phase
comparator has 0V to VSYS input common mode range, and its polarity-selectable output is routed to a data input bit and to
the phase/position multiplexer synchronized with the auto-sampling sequencers.
11.2.5. Protection Comparator (PCMP)
Two protection comparators are provided in association with each differential programmable gain amplifier, with outputs
available to trigger protection events and accessible as read-back output bits. The high-speed protection (HP) comparator
compares the PCMPx pin to the 8-bit HP DAC output voltage, with full scale voltage of 2.5V. The limit protection (LP)
comparator compares the differential programmable gain amplifier output to the 10-bit LP DAC output voltage, with full
scale voltage of 2.5V.
Each protection comparator has a mask bit to prevent or allow it to trigger the main microcontroller interrupt INT1. Each
protection comparator also has one mask bit to prevent or allow it to activate protection event PR1, and another mask bit to
- 30 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
prevent or allow it to activate protection event PR2. These two protection events can be used directly by protection circuitry
in the Application Specific Power Drivers (ASPD) to protect devices being driven.
11.2.6. Analog Output Buffer (BUF)
A subset of the signals from the configurable analog signal matrix CASM can be multiplexed to the BUF6 pin for external
use. The buffer offset voltage can be minimized with the built-in swap function.
11.2.7. Analog Front End I/O (AIO)
Up to 10 AIOx pins are available in the device. In the analog front end I/O mode, the pin can be configured to be a digital
input or digital open-drain output. The AIOx input or output signal can be set to a data input or output register bit, or
multiplexed to one of the signals in the configurable digital signal matrix CDSM. The signal can be set to active high
(default) or active low, with V SYS supply rail. Where AIO 6,7,8,9 supports microcontroller interrupt for external signals. Each
has two mask bits to prevent or allow rising or falling edge of its corresponding digital input to trigger second
microcontroller interrupt INT2.
11.2.8. Push Button (PBTN)
The push button PBTN, when enabled, can be used by the microcontroller to detect a user active-low push button event and
to put the system into an ultra-low-power hibernate mode. Once the system is in hibernate mode, PBTN can be used to
wake up the system. In addition, PBTN can also be used as a hardware reset for the microcontroller when it is held low for
longer than 8s during normal operation. The PBTN input is active low and has a 55kΩ pull-up resistor to 3V.
11.2.9. HP DAC and LP DAC
The 8-bit HP DAC can be used as the comparison voltage for the high-speed protection (HP) comparators, or routed for
general purpose use via the AB2 signal in the CASM. The HP DAC output full scale voltage is 2.5V.
The 10-bit LP DAC can be used as the comparison voltage for the limit protection (LP) comparators, or routed for general
purpose use via the AB3 signal in the CASM. The LP DAC output full scale voltage is 2.5V.
11.2.10. ADC Pre-Multiplexer
The ADC pre-multiplexer is a 16-to-1 multiplexer that selects between the 3 differential programmable gain amplifier
outputs, AB1 through AB9, temperature monitor signal (V TEMP), power monitor signal (V MON), and offset calibration
reference (VREF / 2). The ADC pre-multiplexer can be directly controlled or automatically scanned by the auto-sampling
sequencer.
When the ADC pre-multiplexer is automatically scanned, the unbuffered or sensitive signals should be masked by setting
appropriate register bits.
11.2.11. Configurable Analog Signal Matrix (CASM)
The CASM has 9 general purpose analog signals labeled AB1 through AB9 that can be used for:
 Routing the single-ended programmable gain amplifier or analog feed-through output to AB1 through AB9
 Routing an analog signal via AB1, AB2, or AB3 to the negative input of a general purpose comparator or
phase comparator
 Routing the 8-bit HP DAC output to AB2
 Routing the 10-bit LP DAC output to AB3
 Routing analog signals via AB1 through AB12 to the ADC pre-multiplexer
 Routing phase comparator feed-through signals to AB7, AB8, and AB9, and averaged voltage to AB1
11.2.12. Configurable Digital Signal Matrix (CDSM)
The CDSM has 7 general purpose bi-directional digital signals labeled DB1 through DB7 that can be used for:
 Routing the AIOx input to or output signals from DB1 through DB7
 Routing the general purpose comparator output signals to DB1 through DB7
- 31 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
- 32 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
11.3. Electrical Characteristics
Table 12. Differential Programmable Gain Amplifier (DA) Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
PARAMETER
ICC;DA
Operating supply current
MIN
TYP
MAX
UNI
T
150
300
µA
Each enabled amplifier
VICMR;DA
Input common mode range
-0.3
3.5
V
VOLR;DA
Output linear range
0.1
3.5
V
VOS;DA
Input offset voltage
8
mV
AVZI;DA
Differential amplifier gain
(zero ohm source impedance)
kCMRR;DA
Common mode rejection ratio
RINDIF;DA
Differential input impedance
Slew rate
tST;DA
(1)
CONDITIONS
(1)
Settling time
Gain = 48x, VDAxP= VDAxN = 0V, TA = 25°C
1
Gain = 2x
2
Gain = 4x
4
Gain = 8x, VDAxP = 125mV, VDAxN = 0V,
TA = 25°C
-2%
8
2%
Gain = 16x
16
Gain = 32x
32
Gain = 48x
48
Gain = 8x, VDAxP= VDAxN = 0V, TA = 25°C
55
dB
27
kΩ
10
V/µs
Gain = 8x
(1)
-8
Gain = 1x
7
To 1% of final value
200
400
ns
TYP
MAX
UNI
T
80
Guaranteed by design.
Table 13. Single-Ended Programmable Gain Amplifier (AMP) Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
ICC;AMP
PARAMETER
Operating supply current
VOLR;AMP
Output linear range
VOS;AMP
Input offset voltage
CONDITIONS
MIN
Each enabled amplifier
Gain = 1x, TA = 25°C, VAMPX = 2.5V
140
µA
0.1
3.5
V
-10
10
mV
Gain = 1x
1
Gain = 2x
2
Gain = 4x
AV;AMP
IIN;AMP
tST;AMP
(1)
Amplifier gain
4
Gain = 8x, VAMPx = 125mV, TA = 25°C
-2%
8
Gain = 16x
16
Gain = 32x
32
Gain = 48x
48
Input current
0
Slew rate (1)
Gain = 8x
Settling time (1)
To 1% of final value
8
2%
1
12
150
µA
V/µs
300
ns
Guaranteed by design.
- 33 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Table 14. General Purpose Comparator (CMP) Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
ICC;CMP
VICMR;CMP
Operating supply current
Input offset voltage
VHYS;CMP
Hysteresis
tDEL;CMP
CONDITIONS
MIN
Each enabled comparator
Input common mode range
VOS;CMP
IIN;CMP
(1)
PARAMETER
VCMPx = 2.5V, TA = 25°C
TYP
35
MAX
UNI
T
110
µA
0
VSYS
V
-10
10
mV
23
1
µA
0.1
µs
TYP
MAX
UNI
T
35
110
µA
0
VSYS
V
-10
10
mV
Input current
0
Comparator delay
mV
(1)
Guaranteed by design.
Table 15. Phase Comparator (PHC) Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
ICC;PHC
VICMR;PHC
(1)
PARAMETER
Operating supply current
CONDITIONS
MIN
Each enabled comparator
Input common mode range
VOS;PHC
Input offset voltage
VPHCx = 2.5V, TA = 25°C
VHYS;PHC
Hysteresis
23
IIN;PHC
Input current
0
tDEL;PHC
Comparator delay (1)
mV
1
µA
0.1
µs
TYP
MAX
UNI
T
35
100
µA
0.3
VSYS -1
V
-10
10
mV
Guaranteed by design.
Table 16. Protection Comparator (PCMP) Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
ICC;PCMP
VICMR;PCMP
Operating supply current
CONDITIONS
MIN
Each enabled comparator
Input common mode range
VOS;PCMP
Input offset voltage
VHYS;PCMP
Hysteresis
20
Input current
0
IIN;PCMP
tDEL;PCMP
(1)
PARAMETER
Comparator delay
VPCMPx = 2.5V, TA = 25°C
mV
1
µA
0.1
µs
TYP
MAX
UNI
T
35
100
µA
0.05
3.5
V
(1)
Guaranteed by design.
Table 17. Analog Output Buffer (BUF) Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
ICC;BUF
PARAMETER
Operating supply current
CONDITIONS
MIN
No load
VICMR;BUF
Input common mode range
VOLR;AMP
Output linear range
0.1
3.5
V
VOS;BUF
Offset voltage
VBUF = 2.5V, TA = 25°C
-18
18
mV
Maximum output current
CL = 0.1nF
0.8
IOMAX
- 34 -
1.3
mA
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
- 35 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Table 18. Analog Front End I/O (AIO) Electrical Characteristics
(VSYS = VCCIO = 5V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
VAIO
PARAMETER
CONDITIONS
Pin voltage range
MIN
TYP
0
VIH;AIO
High-level input voltage
VIL;AIO
Low-level input voltage
RPD;AIO
Pull-down resistance
Input mode
VOL;AIO
Low-level output voltage
IAIOx = 7mA, open-drain output mode
IOL;AIO
Low-level output sink current
VAIOx = 0.4V, open-drain output mode
ILK;AIO
High-level output leakage current
VAIOx = 5V, open-drain output mode
MAX
UNI
T
5
V
2.2
0.5
6
V
1
0.8
V
1.8
MΩ
0.4
V
14
mA
0
10
μA
TYP
MAX
UNI
T
5
V
Table 19. Push Button (PBTN) Electrical Characteristics
(VSYS = VCCIO = 5V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
PARAMETER
CONDITIONS
MIN
VI;PBTN
Input voltage range
0
VIH;PBTN
High-level input voltage
2
VIL;PBTN
Low-level input voltage
RPU;PBTN
Pull-up resistance
V
0.35
V
40
55
95
kΩ
MIN
TYP
MAX
UNI
T
TA = 25°C
2.480
2.5
2.520
TA = -40°C to 105°C
2.453
2.5
2.547
To 3V, push button input mode
Table 20. HP DAC and LP DAC Electrical Characteristics
(VSYS = VCCIO = 5V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
VDACREF
PARAMETER
DAC reference voltage
V
HP 8-bit DAC INL(1)
-1
1
LSB
HP 8-bit DAC DNL(1)
-0.5
0.5
LSB
-2
2
LSB
-1
1
LSB
LP 10-bit DAC INL
(1)
LP 10-bit DAC DNL
(1)
CONDITIONS
(1)
Guaranteed by design and characterization.
- 36 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
11.4. Typical Performance Characteristics
(VSYS = 5V and TA = 25°C unless otherwise specified.)
Differential PGA (DAx) Gain Characteristics
at 1x, 2x, 4x, and 8x Settings
Differential PGA (DAx) Gain Characteristics
at 16x, 32x, and 48x Settings
PACCAFE-001
4000
8x
4x
2x
48x
Output Voltage (mV)
Output Voltage (mV)
5000
3000
1x
2000
1000
0
0
500
1000
1500
2000
0
50
100
150
200
PGA (AMPx) Gain Characteristics
at 16x, 32x, and 48x Settings
250
5000
4x
2x
Output Voltage (mV)
8x
48x
3000
1x
2000
1000
0
500
1000
1500
2000
32x
4000
16x
3000
2000
1000
0
2500
PACCAFE-004
PACCAFE-003
Output Voltage (mV)
1000
PGA (AMPx) Gain Characteristics
at 1x, 2x, 4x, and 8x Settings
0
50
100
150
200
Input Voltage (mV)
Input Voltage (mV)
LP DAC Output Voltage vs. Input Code
HP DAC Output Voltage vs. Input Code
2500
250
2500
Output Voltage (mV)
2000
1500
1000
500
0
100h
200h
300h
2000
1500
1000
500
0
3FFh
Input Code
PACCAFE-006
PACCAFE-005
Output Voltage (mV)
2000
Differential Input Voltage (mV)
4000
0
16x
3000
Differential Input Voltage (mV)
5000
0
32x
4000
0
2500
PACCAFE-002
5000
0
40h
80h
C0h
FFh
Input Code
- 37 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
12. APPLICATION SPECIFIC POWER DRIVERS (ASPD)
12.1. Features
 6 low-side and 3 ultra-high-voltage high-side gate drivers
 2 open-drain drivers
 Configurable delays and fast fault protection
12.2. Block Diagram
Figure 12-1. Application Specific Power Drivers
APPLICATION SPECIFIC POWER DRIVERS
DXBx
HIGH-SIDE GATE DRIVERS
DELAY
LEVEL
SHIFT
PREDRIVER
DXHx
HS1
DXSx
FAULT
HS2
PROTECT
LS2
ENHS2
LOW-SIDE GATE DRIVERS
LS1
PORT/PWM SIGNALS
DELAY
PREDRIVER
VP
DRLx
ENDRV
OMx
DOUTOMx
OM DRIVERS
12.3. Functional Description
The Application Specific Power Drivers (ASPD, Figure 12-1) module handles power driving for power control
applications. PAC5250 has six low-side gate drivers (DRLx), three ultra-high-voltage high-side gate drivers (DXHx), two
medium-voltage open-drain drivers (OMx). Each gate driver can drive an external MOSFET or IGBT switch in response to
high-speed control signals from the microcontroller ports, and a pair of high-side and low-side gate drivers can form a halfbridge driver. The open-drain drivers provide activation control for relays, LEDs, buffers, and other loads.
Figure 12-2 below shows typical gate driver connections and Table 21 shows the ASPD resources available on PAC5250.
- 38 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Figure 12-2. Typical Gate Driver Connections
DXBx
VP
VIN
DXHx
DXSx
(To loads/inductors.)
DRLx
PAC5250
Table 21. Power Driver Resources by Part Number
PART
NUMBER
PAC5250
LOW-SIDE GATE
DRIVER
HIGH-SIDE GATE DRIVER
OPEN-DRAIN DRIVER
DRLx
SOURCE /
SINK
CURRENT
DXHx
MAX
SUPPLY
SOURCE/
SINK
CURRENT
OMx
6
1A/1A
3
600V
0.25A/0.5A
2 (23V/ 40mA)
The ASPD includes built-in configurable fault protection for the internal gate drivers. On PAC5250, the protection signal
ENHS2 are provided for external circuitry driver fault protection.
12.3.1. Low-Side Gate Driver
The DRLx low-side gate driver drives the gate of an external MOSFET or IGBT switch between the low-level V SSP power
ground rail and high-level VP supply rail. The DRLx output pin has sink and source output current capability of 1A. Each
low-side gate driver is controlled by a microcontroller port signal with 4 configurable levels of propagation delay.
12.3.2. Ultra-High-Voltage Gate Driver
The DXHx ultra-high-voltage high-side gate driver drives the gate of an external MOSFET or IGBT switch between its
low-level DXSx driver source rail and its high-level DXBx bootstrap rail. The DXSx pin can go up to 600V. The DXHx
output pin has 0.5A sink and 0.25A source output current capability. The DXBx bootstrap pin can have a maximum
operating voltage of 20V relative to the DXSx pin. The DXSx pin is designed to tolerate momentary switching negative
spikes down to -10V without affecting the DXHx output state. Each ultra-high-voltage high-side gate driver is controlled by
a microcontroller port signal.
For bootstrapped high-side operation, connect an appropriate capacitor between DXBx and DXSx and a properly rated
bootstrap diode from VP rail to DXBx.
12.3.3. High-Side Switching Transients
Typical high-side switching transients are shown in Figure 12-3(a). To ensure functionality and reliability, the DXSx and
DXBx pins must not exceed the peak and undershoot limit values shown. This should be verified by probing the DXSx and
DXBx pins directly relative to VSS pin. A small resistor and diode clamp for the DXSx pin can be used to make sure that
the pin voltage stays within the negative limit value. In addition, the high-side slew rate dV/dt must be kept within ±50V/ns
for DXSx. This can be achieved by adding a resistor-diode pair in series, and an optional capacitor in parallel with the
power switch gate. The parallel capacitor also provides a low impedance and close gate shunt against coupling from the
switch drain. These optional protection and slew rate control are shown in Figure 12-3(b).
- 39 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Figure 12-3. High-Side Switching Transients and Optional Circuitry
VDXBx ≤ 625V
DXBx
VP
VIN
DXHx
DXSx
dV/dt
VDXBx
PAC5250
dV/dt
DRLx
VDXSx
VDXSx ≥ -10V
(b) Optional Transient Protection and Slew Rate Control
(a) High-Side Switching Transients
12.3.4. Open-Drain Drivers
The OMx pin is a 23V open-drain driver output controlled by a register bit. OMx is capable of driving 40mA. The OMx pin
is switched to VSSP with 17Ω impedance in the on state when the corresponding bit is '1', and is in the high-impedance off
state when the corresponding bit is '0'.
12.3.5. Power Drivers Control
All power drivers are initially disabled from power-on-reset. To enable the power drivers, the microprocessor must first set
the driver enable bit to '1'. The gate drivers controlled by the microcontroller ports and PWM signals according to Table 22,
with configurable delays as shown in Table 22. The OMx open-drain drivers are controlled by their corresponding register
bits. Refer to the PAC application notes and user guide for additional information on power drivers control programming.
Table 22. Microcontroller Port and PWM to Power Driver Mapping
PART
NUMBER
PWMA0
PWMA1
PWMA2
PWMA3/
PWMA4/
PWMB0
PWMA5/
PWMC0
PWMA6/
PWMD0
PWMA4/
PWMB0
PWMA5/
PWMA7/
PWMC1
PWMA6/
PWMD0
PAC5250
DRL0
DRL1
DRL2
DRL3
DRL4
DRL5
DXH0
DXH1
DXH2
Table 23. Power Driver Delay Configuration
DRLx
DXHx
DELAY
SETTING
RISING
FALLING
RISING
FALLING
Default Setting
130ns
140ns
200ns
240ns
01b Setting
170ns
180ns
10b Setting
230ns
250ns
11b Setting
360ns
380ns
- 40 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
12.3.6. Gate Driver Fault Protection
The ASPD incorporates a configurable fault protection mechanism using two protection event signals from the
Configurable Analog Front End (CAFE), designated as protection event 1 (PR1) and protection event 2 (PR2) signals. The
DRL0/DRL1/DRL2 drivers are designated as low-side group 1, and the DRL3/DRL4/DRL5 gate drivers are designed as
low-side group 2. The DXH0/DXH1/DXH2 ultra-high-voltage gate drivers are designated as high-side group 1. The PR1
signal from the CAFE can be used to disable low-side group 1, high-side group 1, or both depending on the PR1 mask bit
settings. The PR2 signal from the CAFE can be used to disable low-side group 2, high-side group 2, or both depending on
the PR2 mask bit settings. ENHS2 (high-side group 2 control output) pin is provided for enabling external power drivers
with fault protection.
- 41 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
12.4. Electrical Characteristics
Table 24. Gate Drivers Electrical Characteristics
(VP = 12V, VSYS = 5V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VP−0.5
VP−0.25
UNI
T
Low-Side Gate Drivers (DRLx Pins)
VOH,DRL
High-level output voltage
IDRLx = -50mA
VOL,DRL
Low-level output voltage
IDRLx = 50mA
IOHPK,DRL
High-level pulsed peak source current
10µs pulse
-1
A
IOLPK,DRL
Low-level pulsed peak sink current
10µs pulse
1
A
Delay setting 00
10
Delay setting 01
50
Delay setting 10
120
Delay setting 11
250
TPD,DRL
Propagation Delay
0.175
V
0.35
V
ns
Ultra-High-Voltage Gate Drivers (DXHx, DXBx and DXSx Pins)
-10
605
Steady state
0
600
Repetitive, 10us pulse
1
625
Steady state
9
620
Bootstrap supply voltage range
VDXBx, relative to respective VDXSx
9
20
V
Bootstrap UVLO threshold
VDXBx rising, relative to respective VDXSx ,
Hys=0.5V
7.5
9.3
V
40
80
µA
10
µA
VDXS
Level-shift driver source voltage range
VDXB
Bootstrap pin voltage range
VBS;DXB
VUVLO;DXB
Repetitive, 10us pulse
IBS;DXB
Bootstrap supply current
IOS;DXB
Offset supply current
VDXBx = VDXSx =600V
VOH;DXH
High-level output voltage
IDXHx = -20mA
6.3
VDXBx−0.6
V
V
V
VOL;DXH
Low-level output voltage
IDXHx = 40mA
IOHPK;DXH
High-level pulsed peak source current
10µs pulse
-0.25
VDXSx+0.6
V
A
IOLPK;DXH
Low-level pulsed peak sink current
10µs pulse
0.5
A
Table 25. Open-Drain Drivers Electrical Characteristics
(VP = 12V, VSYS = 5V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNI
T
23
V
Medium-Voltage Open-Drain Drivers (OMx Pins)
VOM
Output voltage range
Off state
0
RON;OM
On state resistance
IOMx = 20mA
IOL;OM
On state sink current
VOMx = 2V
ILK;OM
Leakage current
VOMx = 23V, off state
17
40
- 42 -
35
80
0
Ω
mA
10
μA
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Table 26. Power Drivers Module Electrical Characteristics
(VP = 12V, VSYS = 5V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNI
T
High-Side Driver Group Control Output (ENHS2 Pin)
VOH;ENHS2
High-level output voltage
IENHS2 = -3mA
VOL;ENHS2
Low-level output voltage
IENHS2 = 1mA
IOH;ENHS2
High-level output source current
VENHS2 = 2.4V
IOL;ENHS2
Low-level output sink current
VENHS2 = 0.4V
- 43 -
2.4
V
-5.8
1
1.5
0.4
V
-4.3
mA
mA
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
12.5. Typical Performance Characteristics
(VP = 12V, VSYS = 5V and TA = 25°C unless otherwise specified.)
Low-Side Gate Driver (DRLx)
Source/Sink Current vs. Temperature
7
On Resistance (Ω)
Source/Sink Current (A)
PACASPD-002
8
PACASPD-001
3
Low-Side Gate Driver (DRLx)
On Resistance vs. Temperature
2
Source current
1
Sink current
6
5
Pull up
Pull down
4
3
2
1
0
-40
0
40
80
0
120
40
80
120
Ultra-High-Voltage High-Side Gate Driver (DXHx)
Source/Sink Current vs. Temperature
Ultra-High-Voltage High-Side Gate Driver (DXHx)
On Resistance vs. Temperature
25
Sink current
20
On Resistance (Ω)
0.8
0.6
0.4
Source current
0.2
0
-40
Pull up
15
10
Pull down
5
PAC5250
0
40
80
0
-40
120
PAC5250
0
40
80
120
Temperature (°C)
Temperature (°C)
Low-Side Gate Driver (DRLx)
Turn-On Delay vs. Temperature
Low-Side Gate Driver (DRLx)
Turn-Off Delay vs. Temperature
500
500
Turn-Off Delay (ns)
11b setting
300
10b setting
200
01b setting
00b setting (default)
100
CL = 1nF
0
40
80
Temperature (°C)
11b setting
400
300
10b setting
01b setting
200
00b setting (default)
100
0
-40
120
PACASPD-008
PACASPD-007
400
0
-40
PACASPD-006
PACASPD-005
Source/Sink Current (A)
0
Temperature (°C)
1.0
Turn-On Delay (ns)
-40
Temperature (°C)
CL = 1nF
0
40
80
120
Temperature (°C)
- 44 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Typical Performance Characteristics (Continued)
Ultra-High-Voltage High-Side Gate Driver (DXHx)
Turn-On Delay vs. Temperature
Ultra-High-Voltage High-Side Gate Driver (DXHx)
Turn-Off Delay vs. Temperature
500
500
Turn-Off Delay (ns)
400
300
200
100
CL = 1nF
0
-40
0
40
80
400
300
200
100
0
-40
120
Temperature (°C)
PACASPD-012
PACASPD-011
Turn-On Delay (ns)
(VP = 12V, VSYS = 5V and TA = 25°C unless otherwise specified.)
CL = 1nF
0
40
80
120
Temperature (°C)
OMx Open-Drain Driver On State
Output Voltage vs. Output Current
On State Output Voltage (V)
PACASPD-014
4
3
105°C
2
25°C
1
0
-30°C
0
40
80
120
160
200
Output Current (mA)
- 45 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
13. ADC WITH AUTO-SAMPLING SEQUENCER
13.1. Block Diagram
Figure 13-1. ADC with Auto-Sampling Sequencer
ADC RESULT REGISTERS
(16)
AHB/APB
ADC WITH AUTO-SAMPLING SEQUENCER
REGISTER
REGISTER
REGISTER
REGISTER
ADx
MUX
ADC
CONFIGURABLE ANALOG FRONT END
10-BIT
ADC
DIFF-PGA
DAxN
AUTO-SAMPLING
SEQUENCER
ADC PRE-MUX
S/H
DAxP
MUX
DIFFERENTIAL PGA
STATE MACHINE 0
STATE MACHINE 1
CASM
EMUX CONTROL
VTEMP, VMON, VREF/2
EMUX
13.2. Functional Description
13.2.1. ADC
The analog-to-digital converter (ADC) is a 10-bit succesive approximation register (SAR) ADC with 1 μs conversion
time and up to 1MSPS capability. The ADC input clock has a user-configurable divider from /1 to /8 of the system clock.
The integrated analog multiplexer allows selection from up to 6 direct ADx inputs, and from up to 10 analog inputs signals
in the Configurable Analog Front End (CAFE), including up to 3 differential input pairs. The ADC can be configured for
repeating or non-repeating conversions and can interrupt the microcontroller when a conversion is finished.
13.2.2. Auto-Sampling Sequencer
Two independent and flexible auto-sampling sequencer state machines allow signal sampling using the ADC without
interaction from microcontroller core. Each auto-sampling sequencer state machine can be programmed to take and store up
to 8 samples each in the ADC result register from different analog inputs, able to control the ADC MUX and ADC Premux
as well as the precise timing of the S/H in the Configurable analog front end. The sampling start of the auto-sampling
sequencer can be precisely triggered using timers A, B, C, or D or any of their associated PWM edges (high-to-low or lowto-high). It also supports manual start or a ping-pong-scheme, where one auto-sampling sequencer state machine triggers
the other when it finishes sampling.
The auto-sampling sequencer can interrupt the microcontroller when either conversion sequence is finished.
- 46 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
13.2.3. EMUX Control
A dedicated low latency interface controllable by the auto-sampling sequencer or register control allows changing the ADC
premultiplexer and asserting/deasserting the S/H circuit in the configurable analog front end, allowing back to back
conversions of multiple analog inputs without microcontroller interaction.
13.3. Electrical Characteristics
Table 27. ADC and Auto-Sampling Sequencer Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNI
T
16
MHz
ADC
fADCLK
ADC conversion clock input
tADCONV
ADC conversion time
fADCLK = 16MHz
1
ADC resolution
10
ADC effective resolution
μs
bits
9.2
bits
±0.5
LSB
±1
LSB
ADC offset error
0.6
%FS
ADC gain error
0.12
%FS
2.5
V
188
ns
1.3
pF
ADC differential non-linearity (DNL)
ADC integral non-linearity (INL)
Reference Voltage
VREFADC
ADC reference voltage input
Sample and Hold
tADCSH
ADC sample and hold time
CADCIC
ADC input capacitance
fADCLK = 16MHz
Input Voltage Range
VADCIN
ADC input voltage range
ADC multiplexer input
0
VREFADC
V
50
MHz
EMUX Clock Speed
fEMUXCLK
EMUX engine clock input
PLL Clock Speed
fOUTPLL
PLL output frequency
TA = -40°C to 85°C
3.5
100
MHz
TA = 85°C to 105°C
3.5
80
MHz
- 47 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
14. MEMORY SYSTEM
14.1. Features
 32kB embedded FLASH
 100,000 program/erase cycles
 10 years data retention
 8kB SRAM
14.2. Block Diagram
Figure 14-1. Memory System
INFO ROM
FLASH
SRAM
256B INFO
ROM
1kB FLASH
PAGES
8kB
SRAM
AHB/APB
MEMORY SYSTEM
14.3. Functional Description
The device has multiple banks of embedded FLASH memory, SRAM memory, as well as peripheral control registers that
are all program-accessible in a flat memory map.
14.3.1. Program and Data FLASH
32kB in 32 pages of 1kB each is available for program or data memory. Each of them can be individually erased or written
to while the microcontroller is executing a program from SRAM.
14.3.2. SRAM
Up to 8kB contiguous array of SRAM is available for non-persistent data storage. The SRAM memory supports word
(4-byte), half-word (2-byte) and byte address aligned access. The microcontroller may execute code out of SRAM for timecritical applications, or when modifying the contents of FLASH memory.
- 48 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
14.4. Electrical Characteristics
Table 28. Memory System Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNI
T
Embedded FLASH
tREAD;FLASH
FLASH read time
40
ns
tWRITE;FLASH
FLASH write time
20
μs
tPERASE;FLASH
FLASH page erase time
NPERASE;FLASH
FLASH program/erase cycles
tDR;FLASH
10
ms
100k
cycles
FLASH data retention
10
years
SRAM access cycle time
20
ns
SRAM
tSRAM
- 49 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
15. CLOCK CONTROL SYSTEM
15.1. Features







Ring oscillator with 7.5MHz, 9.6MHz, 13.8MHz, and 25.7MHz settings
High accuracy 1% trimmed 4MHz RC oscillator
Crystal oscillator driver supporting 2MHz to 10MHz crystals
External clock input up to 40MHz
PLL with 1MHz to 25 MHz input, and 3.5MHz to 100MHz output
/1 to /8 clock divider for HCLK
/1 to /128 clock divider for ACLK
15.2. Block Diagram
Figure 15-1. Clock Control System
CLOCK CONTROL SYSTEM
FRCLK
FRCLK
CLOCK
GATING
DIV
RTC
DIV
WDT
DIV
WIC
DIV
ADC
DIV
SYSTICK
CORTEX M0
CLOCK SOURCES
PLL
PLL
CLOCK
CLOCK
TREE
TREE
SRAM
RING
OSCILLATOR
XIN
XOUT
PLL
PLL
MUX
MUX
FRCLK
MUX
1% RC
OSCILLATOR
EXTCLK
FLASH
FCLK
DIVDIV
CRYSTAL
DRIVER
DIVDIV
HCLK
CLOCK
GATING
DIV
UART
DIV
I2C
DIV
SOC BUS
DIV
SPI
ACLK
DIV
ADC EMUX
TIMERS A, B, C & D
CLOCK
GATING
- 50 -
DIV
TIMER
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
15.3. Functional Description
The PAC clock control system covers a wide range of applications.
15.3.1. Free Running Clock (FRCLK)
The free running clock (FRCLK) is generated from one of the 4 clock sources: ring oscillator, trimmed RC oscillator,
crystal driver or external clock input. The FRCLK is used for the real-time clock (RTC), watchdog timer (WDT), input to
the PLL, or FCLK source to clock the system in low power and sleep mode.
15.3.2. Fast Clock (FCLK)
The fast clock (FCLK) is generated from the PLL or supplied by the FRCLK directly. The FCLK supplies the watchdog
timer (WDT), ADC, wake-up interrupt controller (WIC), SysTick timer, ARM Cortex-M0 peripheral high speed clock
(HCLK) and low speed clock (LSCLK).
15.3.3. High-Speed Clock (HCLK)
The high-speed clock (HCLK) is derived from the FCLK with a /1, /2, /4 or /8 divider. It supplies the peripheral AHB/APB
bus, Timers A to D, dead-time controllers, SPI interface, I 2C interface, UART interface, EMUX interface, SOC bridge
interface and memory subsystem, and can go as high as 50MHz.
15.3.4. Auxiliary Clock (ACLK)
The auxiliary clock (ACLK) is derived from FCLK with a /1, /2, to /128 divider, and supplies the timer and dead -time
blocks. It can be clocked faster or slower than HCLK and can go as high as 100MHz.
15.3.5. Clock Gating
The clock tree supports clock gating in deep-sleep mode for the timer block, ADC, SPI interface, I 2C interface, UART
interface, memory subsystem and the ARM Cortex-M0 itself.
15.3.6. Ring Oscillator (ROSC)
The integrated ring oscillator provides 4 different clocks with 7.5MHz, 9.6MHz, 13.8MHz, and 25.7MHz settings. After
reset, the clock tree always defaults to this clock input with the lowest frequency setting.
15.3.7. Trimmed 4MHz RC Oscillator
The 1% trimmed 4MHz RC oscillator provides an accurate clock suitable for many applications. It is also used to derive the
clock for the Multi-Mode Power Manager.
15.3.8. Internal Slow RC Oscillator
An internal 32kHz RC oscillator is used during start up to provide an initial clock to analog circuitry. It is not used as a
clock input to the clock tree.
15.3.9. Crystal Oscillator Driver
The optional crystal oscillator driver can drive crystals from 2MHz to 10MHz to provide a highly accurate and stable clock
into the system.
15.3.10. External Clock Input
The clock tree can be supplied with an external clock up to 10MHz.
15.3.11. PLL
The integrated PLL input clock is supplied by the FRCLK with an input frequency range of 1MHz to 25MHz. The PLL
output frequency is adjustable from 3.5MHz to 100MHz.
- 51 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
15.4. Electrical Characteristics
Table 29. Clock Control System Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNI
T
Clock Tree (FRCLK, FCLK, HCLK, and ACLK)
fFRCLK
Free running clock frequency
50
MHz
fFCLK
Fast clock frequency
100
MHz
fHCLK
High-speed clock frequency
50
MHz
fACLK
Auxiliary clock frequency
100
MHz
Internal Oscillators
fROSC
fTRIM
Ring oscillator frequency
Trimmed RC oscillator frequency
Trimmed RC oscillator clock jitter
Frequency setting = 11b
7.5
Frequency setting = 10b
9.6
Frequency setting = 01b
13.8
Frequency setting = 00b
25.7
MHz
TA = 25°C
3.96
4
4.04
TA = -40°C to 105°C
3.90
4
4.06
TA = -40°C to 85°C
0.5
MHz
%
Crystal Oscillator Driver
VIH;XIN
XIN high-level input voltage
VIL;XIN
XIN low-level input voltage
fXTAL
Crystal oscillator frequency range
Recommended capacitive load
External circuit ESR
V
0.65•VCC18
2
fXTAL = 2MHz to 3MHz
25
fXTAL = 3MHz to 6MHz
20
fXTAL = 6MHz to 10MHz
16
0.35•VCC18
V
10
MHz
pF
fXTAL = 2MHz to 3MHz
1000
fXTAL = 3MHz to 6MHz
400
fXTAL = 6MHz to 10MHz
100
Ω
External Clock Input
fEXTCLK
External clock input frequency range
40
MHz
tHIGH;EXTCLK
External clock high time
10
ns
tLOW;EXTCLK
External clock low time
10
ns
PLL
fINPLL
PLL input frequency range
2
25
MHz
fOUTPLL
PLL output frequency range
3.5
100
MHz
PLL settling time
PLL period jitter
0.5
RMS
30
±150
Peak to peak
- 52 -
ms
ps
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
16. ARM CORTEX-M0 MICROCONTROLLER CORE
16.1. Features
ARM Cortex-M0 core
Fast single-cycle 32-bit x 32-bit multiplier
24-bit SysTick timer
Up to 50MHz operation
Serial wire debug (SWD), with 4 break-point and 2 watch-point unit comparators
Nested vectored interrupt controller (NVIC) with 25 external interrupts
Wake-up interrupt controller (WIC) with GPIO, real-time clock (RTC) and watchdog timer (WDT) interrupts
enabled
 Sleep and deep-sleep mode with clock gating







16.2. Block Diagram
Figure 16-1. ARM Cortex-M0 Microcontroller Core
SWDCL
SWDDA
SERIAL WIRE
DEBUG WITH
DISABLE
ARM
CORTEX-M0
1-CYCLE
32X32
MULTIPLIER
24-BIT
SYSTICK
NESTED
VECTORED
INTERRUPT
CONTROLLER
AHB/APB
ARM CORTEX-M0 MICROCONTROLLER CORE
WAKE-UP
INTERRUPT
CONTROLLER
16.3. Functional Description
The ARM Cortex-M0 microcontroller core is configured for little endian operation and includes the fast single-cycle 32-bit
multiplier and 24-bit SysTick timer and can operate at a frequency of up to 50MHz.
The microcontroller nested vectored interrupt controller (NVIC) supports 25 external interrupts for the device's peripherals
and sub-systems. For low-latency interrupt processing, the NVIC also supports interrupt tail-chaining. The wake-up
interrupt controller (WIC) is able to wake up the device from low-power modes using any GPIO interrupt, as well as from
the RTC or WDT. The ARM Cortex-M0 supports both sleep and deep-sleep low-power modes. The deep-sleep mode
supports clock gating to limit standby power even further.
Firmware debug support includes 4 break-point and 2 watch-point unit comparators using the serial wire debug (SWD)
protocol. The serial wire debug mechanism can be disabled to prevent device access to the firmware in the field.
- 53 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
16.4. Electrical Characteristics
Table 30. Microcontroller and Clock Control System Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
PARAMETER
fHCLK
CONDITIONS
Microcontroller clock
IOP;VSYS
TYP
HCLK
VSYS operating supply current
IQ;VCCIO
MIN
fFRCLK = fHCLK = fACLK = ROSC 11b, PLL
disabled, CPU halt; other clock sources, ADC,
timers, and serial interface disabled
3.4
fFRCLK = fHCLK = fACLK = ROSC 10, PLL
disabled, CPU halt; other clock sources, ADC,
timers, and serial interface disabled
4
fFRCLK = fHCLK = fACLK = ROSC 01, PLL
disabled, CPU halt; other clock sources, ADC,
timers, and serial interface disabled
5.3
fFRCLK = fHCLK = fACLK = ROSC 00, PLL
disabled, CPU halt; other clock sources, ADC,
timers, and serial interface disabled
9
fFRCLK = fHCLK = fACLK = CLKREF, PLL disabled,
CPU halt; other clock sources, ADC, timers,
and serial interface disabled
2.3
fFRCLK = fHCLK = fACLK = 10MHz XTAL, PLL
disabled, CPU halt; other clock sources, ADC,
timers, and serial interface disabled
4.5
fFRCLK = 4MHz CLKREF, fHCLK = 50MHz, fACLK
= fOUTPLL = 100MHz, CPU halt; other clock
sources, ADC, timers, and serial interface
disabled
23.3
VCCIO quiescent supply current
0.02
MAX
UNI
T
50
MHz
mA
mA
16.5. Typical Performance Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = 25°C unless otherwise specified.)
IVCC18 vs. PLL Frequency
IVCC18 (mA)
20
PACMCU-001
25
fHCLK = fACLK = fOUTPLL
15
fHCLK = 0.5•fOUTPLL,
fACLK = fOUTPLL
10
5
0
0
20
40
60
80
100
PLL Frequency (MHz)
- 54 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
17. I/O CONTROLLER
17.1. Features




5V-compliant I/O PAx, PDx, PEx
3.3V-compliant I/O PCx
Configurable drive strength on PAx, PDx, PEx
Configurable pull-up or pull-down on PAx, PDx, PEx
17.2. Block Diagram
Figure 17-1. I/O controller
DIGITAL I/O
GPIO (PAx, PDx, PEx)
VCCIO (5V/3.3V)
PERIPHERAL
PULL UP
GPIO INPUT
PAx, PDx, PEx
VCCIO (5V/3.3V)
PULL DOWN
PERIPHERAL
GPIO OUTPUT
OUTPUT ENABLE
DRIVE STRENGTH
GPIO (PCx)
ADC MUX
GPIO INPUT
INPUT ENABLE
PCx
GPIO OUTPUT
AHB/APB
VCC33 (3.3V)
OUTPUT ENABLE
17.3. Functional Description
The PAC can support up to 4 ports with 8 I/Os each from PAx, PCx, PDx, and PEx, in addition to the I/Os on the analog
front end. All PAx, PCx, PDx, and PEx ports have interrupt capability with configurable interrupt edge.
PAx, PDx, and PEx I/Os use VCCIO as the I/O supply voltage that is 5V on default parts (and 3.3V available from factory).
The drive current can be configured as 8mA or 16mA. They also support weak pull-up and pull-down to save external
components.
PCx uses VCC33 as its I/O supply voltage. The drive current is fixed to 8mA. PC0 to PC5 are also associated with analog
inputs AD0 to AD5 to the ADC.
- 55 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
17.4. Electrical Characteristics
Table 31. I/O Controller Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNI
T
PAx, PDx, PEx (5V Operation)
VIH
High-level input voltage
VCCIO = 5V
3
V
VIL
Low-level input voltage
VCCIO = 5V
IOL
Low-level output sink current
VCCIO = 5V,
VOL = 0.4V
Drive strength setting = 0b
7
Drive strength setting = 1b
15
IOH
High-level output source current
VCCIO = 5V,
VOH = 2.4V
Drive strength setting = 0b
-7
Drive strength setting = 1b
-15
RPU
Weak pull-up resistance
VCCIO = 5V
53
66
87
kΩ
RPD
Weak pull-down resistance
VCCIO = 5V
63
108
244
kΩ
IIL
Input leakage current
TA = 125°C
-10
0
10
μA
2
0.8
V
mA
mA
PAx, PDx, PEx (3.3V Operation)
VIH
High-level input voltage
VCCIO = 3.3V
V
VIL
Low-level input voltage
VCCIO = 3.3V
IOL
Low-level output sink current
VCCIO = 3.3V,
VOL = 0.4V
Drive strength setting = 0b
4
Drive strength setting = 1b
8
IOH
High-level output source current
VCCIO = 3.3V,
VOH = 2.4V
Drive strength setting = 0b
-4
Drive strength setting = 1b
-8
RPU
Weak pull-up resistance
VCCIO = 3.3V
47
74
104
kΩ
RPD
Weak pull-down resistance
VCCIO = 3.3V
50
84
121
kΩ
IIL
Input leakage current
TA = 125°C
-10
0
10
μA
2
0.8
V
mA
mA
PCx (3.3V Operation)
VIH
High-level input voltage
VCC33 = 3.3V
VIL
Low-level input voltage
VCC33 = 3.3V
IOL
Low-level output sink current
VCC33 = 3.3V, VOL = 0.4V
IOH
High-level output source current
VCC33 = 3.3V, VOH = 2.4V
IIL
Input leakage current
TA = 125°C
V
0.8
7
-10
- 56 -
V
mA
0
-7
mA
10
μA
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
18. SERIAL INTERFACE
18.1. Block Diagram
Figure 18-1. Serial Interface
SERIAL INTERFACE
I2C
I2C
MASTER
SCL
SDA
I2C
SLAVE
UART
16550-COMPATIBLE
UART
AHB/APB
TX
RX
SPI
SPICLK
SPI
MASTER
SPIMISO
SPIMOSI
SPI
SLAVE
SPICS0, 1, 2
18.2. Functional Description
The device has up to three serial interfaces: I2C, UART, and SPI.
18.2.1. I2C Controller
The I2C controller is a configurable peripheral that can support various modes of operation:
 I2C master operation
 Normal mode (100kHz), fast mode (400kHz), or fast mode plus (1MHz)
 Single and multi-master
 Synchronization (multi-master)
 Arbitration (multi-master)
 7-bit or 10-bit slave addressing
2
 I C slave operation
 Normal mode (100kHz), fast mode (400kHz), or fast mode plus (1MHz)
 Clock stretching
 7-bit or 10-bit slave addressing
The I2C peripheral may operate either by polling, or can be configured to be interrupt driven for both receive and transmit
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PAC5250
Power Application Controller
data.
18.3. UART Controller
The UART peripheral is a configurable peripheral that can support various features and modes of operation:
 Programmable clock selection
 National Instruments PC16550D compatible
 16-deep transmit and receive FIFO and fractional clock divisor
 Up to 3.125Mbps communication speed (with HCLK = 50MHz)
The UART peripheral may operate either by polling, or can be configured to be interrupt driven for both receive and
transmit data.
18.4. SPI Controller
The device contains an SPI controller that can each be used in either master or slave operation, with the following features:
 SPI master operation
 Control of up to three different SPI slaves
 Operation up to 25MHz
 Flexible multiple transmit mode for variable-size SPI data with user-defined chip-select behavior
 Chip select “shaping” through programmable additional delay for chip-select setup, hold and wait time
for back-to-back transfers
 SPI master or slave operation
 Supports clock phase and polarity control
 Data transmission/reception can be on 8-, 16-, 24- or 32-bit boundary
 Selectable data bit ordering (LSB or MSB first)
 Programmable chip select polarity
 Selectable “auto-retransmit” mode
The SPI peripheral may operate either by polling, or can be configured to be interrupt driven for both receive and transmit
data.
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PAC5250
Power Application Controller
18.5. Dynamic Characteristics
Table 32. Serial Interface Dynamic Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNI
T
I2C
fI2CCLK
2
I C input clock frequency
Standard mode (100kHz)
2.8
MHz
Fast mode (400kHz)
2.8
MHz
Fast mode plus (1MHz)
6.14
MHz
UART
fUARTCLK
UART input clock frequency
UART baud rate
fHCLK/16
MHz
fHCLK = 50MHz
3.125
Mbps
Master mode
fHCLK/2
MHz
Slave mode
fHCLK/2
MHz
SPI
fSPICLK
SPI input clock frequency
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Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Table 33. I2C Dynamic Characteristics
SYMBOL
fSCL
tLOW
tHIGH
tHD;STA
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
PARAMETER
SCL clock frequency
SCL clock low
SCL clock high
CONDITIONS
Data hold time
Data set-up time
0
100
0
400
Fast mode plus
0
1000
Standard mode
4.7
Fast mode
1.3
Fast mode plus
0.5
Standard mode
4.0
Fast mode
0.6
Fast mode plus
0.26
Standard mode
4.0
0.6
4.7
Fast mode
0.6
Fast mode plus
0.26
Standard mode
0
3.45
Fast mode
0
0.9
Fast mode plus
0
Standard mode
250
Fast mode
100
50
Fast mode
0.6
Fast mode plus
0.26
Standard mode
Bus free time between a STOP and START
Fast mode
condition
Fast mode plus
4.7
tf
Cb
Rise time for SDA and SCL
Fall time for SDA and SCL
Capacitive load for each bus line
μs
Standard mode
4.0
Fast mode
kHz
μs
0.26
Standard mode
UNIT
μs
Fast mode plus
μs
μs
ns
μs
1.3
μs
0.5
Standard mode
tr
MAX
Fast mode
Fast mode plus
Set-up time for STOP condition
TYP
Standard mode
Hold time for a repeated START condition Fast mode
Set-up time for a repeated START
condition
MIN
1000
20
300
ns
Fast mode plus
120
Standard mode
300
Fast mode
300
Fast mode plus
120
Standard mode, Fast mode
400
pF
Fast mode plus
550
pF
- 60 -
ns
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Figure 18-2. I2C Timing Diagram
tHD;STA
tSU;DAT
tSU;STA
tr
tf
tBUF
SDA
tHD;DAT
tf
tr
tSU;STO
SCL
S
tLOW
tHIGH
Sr
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P
S
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
19. TIMERS
19.1. Block Diagram
Figure 19-1. Timers A, B, C, and D
TIMER A PWM
PWMA0, PWMA1,
PWMA2, PWMA3
PWMA4, PWMA5,
PWMA6, PWMA7
CAPTURE &
COMPARE
TIMER A
16-BIT
SYNC
TIMERS A, B, C, AND D
DEAD TIME
GENERATOR
CAPTURE &
COMPARE
TIMER B PWM
PWMB0
PWMB1
CAPTURE &
COMPARE
TIMER B
16-BIT
DEAD TIME
GENERATOR
CAPTURE &
COMPARE
TIMER C PWM
PWMC1
CAPTURE &
COMPARE
TIMER C
16-BIT
DEAD TIME
GENERATOR
CAPTURE &
COMPARE
AHB/APB
PWMC0
TIMER D PWM
PWMD0
PWMD1
CAPTURE &
COMPARE
TIMER D
16-BIT
DEAD TIME
GENERATOR
CAPTURE &
COMPARE
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Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
Figure 19-2. SOC Bus Watchdog and Wake-Up Timer
SOC
SOC BUS
WATCHDOG
WAKE-UP
TIMER
SOC BUS
AHB/APB
SOC BUS WATCHDOG AND WAKE-UP TIMER
Figure 19-3. Real-Time Clock and Watchdog Timer
REAL-TIME CLOCK AND WATCHDOG TIMER
WDT
24-BIT
AHB/APB
RTC
24-BIT
19.2. Functional Description
The device includes 9 timers: timer A, timer B, timer C, timer D, watchdog timer 1 (WDT), watchdog timer 2, wake-up
timer, real-time clock (RTC), and SysTick timer. The device supports up to 14 different PWM signals and has up to 7 deadtime controllers. Timers A, B, C and D can be concatenated to synchronize to a single clock and start/stop signal for
applications that require a synchronized timer period between timers.
19.2.1. Timer A
Timer A is a general purpose 16-bit timer with 8 PWM/capture and compare units. It has 4 pairs of PWM signals going into
4 dead-time controllers. Timer A can be concatenated with timers B, C, and D to synchronize the PWM/capture and
compare units. It can use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.
19.2.2. Timer B
Timer B is a general purpose 16-bit timer with 2 PWM/capture and compare units. It has one pair of PWM signals going
into one dead-time controller, as well as 2 additional compare units that can be used for additional system time bases for
interrupts. Timer B can be concatenated with timers A, C, and D to synchronize the PWM/capture and compare units. It can
use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.
19.2.3. Timer C
Timer C is a general purpose 16-bit timer with 2 PWM/capture and compare units. It has one pair of PWM signals going
into one dead-time controller. Timer C can be concatenated with timers A, B, and D to synchronize the PWM/capture and
compare units. It can use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.
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Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
19.2.4. Timer D
Timer D is a general purpose 16-bit timer with 2 PWM/capture and compare units. It has one pair of PWM signals going
into one dead-time controller. Timer D can be concatenated with timers A, B, and C to synchronize the PWM/capture and
compare units. It can use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.
19.2.5. Watchdog Timer
The 24-bit watchdog timer (WDT) can be used for long time period measurements or periodic wake up from sleep mode.
The watchdog timer can be used as a system watchdog, or as an interval timer, or both. The watchdog timer can use either
FRCLK or FCLK as clock input with an additional clock divider from /2 to /65536.
19.2.6. SOC Bus Watchdog Timer
The watchdog timer 2 is used to monitor internal SOC Bus communication. It will trigger device reset if there is no SOC
Bus communication to the AFE for 4s or 8s.
19.2.7. Wake-Up Timer
The wake-up timer can be used for very low power hibernate and sleep modes to wake up the micro controller periodically.
It can be configured to be 125ms, 250ms, 500ms, 1s, 2s, 4, or 8s.
19.2.8. Real-Time Clock
The 24-bit real-time clock (RTC) can be used for time measurements when an accurate clock source is used. This timer can
also be used for periodic wake up from sleep mode. The RTC uses FRCLK as clock input with an additional clock divider
from /2 to /65536.
- 64 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
20. THERMAL CHARACTERISTICS
Table 34. Thermal Characteristics
PARAMETER
VALUE
UNIT
Operating ambient temperature range
-40 to 105
°C
Operating junction temperature range
-40 to 150
°C
Storage temperature range
-55 to 150
°C
Lead temperature (Soldering, 10 seconds)
300
°C
Junction-to-case thermal resistance (θJC)
16.8
°C/W
Junction-to-ambient thermal resistance (θJA)
31.5
°C/W
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Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
21. APPLICATION EXAMPLES
The following simplified diagrams show different examples of PAC applications. Refer to application notes for detailed
design description.
Figure 21-1. 3-Phase Motor Using PAC5255 (Simplified Diagram)
VP
VAC
PAC5255
DRM
CSM
INTERFACE
GPIO
MONITORING
SIGNALS
DXBx
VP
DXHx
DXSx
M
DRLx
DAxP, DAxN
Figure 21-2. Solar Micro-Inverter Using PAC5255 (Simplified Diagram)
VP
PAC5255
DRM
CSM
INTERFACE
GPIO
MONITORING
SIGNALS
DRL2
AMPx
DXB0, DXB1
VP
DXH0, DXH1
DXS0, DXS1
VAC
DRL0, DRL1
DAxP, DAxN
- 66 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
VP
Figure 21-3. Motor with LED Lighting Using
PAC5255 (Simplified Diagram)
VAC
DRM
CSM
VP
INTERFACE
GPIO
MONITORING
SIGNALS
INTERFACE
VAC
PAC5255
DRM
CSM
DXBx
VP
DXHx
GPIO
MONITORING
SIGNALS
DXSx
DXBx
VP
DRLx
DXHx
DAxP, DAxN
DXSx
M
M
DRLx
DAxP, DAxN
DRLx
AMPx
- 67 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
22. PACKAGE OUTLINE AND DIMENSIONS
22.1. TQFN1010-57 Package Outline and Dimensions
Figure 22-1. TQFN1010-57
D
e
D/2
e/2
pin #1
pin #1 top
side marking
4xe
E
E2
E1
E1 / 2
4xe
D2
Detail A
A3
L
L1
Bottom View
A1
Top View
D1
A
b
b1
Side View
Table 22-1. Dimensions
Millimeters
Inches
Dimensions
Min.
Max.
Min.
Max.
A
0.700
0.800
0.028
0.031
A1
-0.004
0.046
0.000
A3
0.110
0.002
0.004
b
0.175
0.225
0.007
0.009
b1
0.100
0.200
0.004
0.008
D
9.900
10.100
0.390
0.398
D1
4.975
5.025
0.196
D2
0.500
0.198
0.020
E
9.900
10.100
0.390
0.398
E1
2.975
3.025
0.117
0.119
E2
0.500
e
L
L1
0.020
0.500
0.350
0.020
0.450
0.050
0.014
0.018
0.050
- 68 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
- 69 -
Rev 1.7‒April 15, 2016
PAC5250
Power Application Controller
23. LEGAL INFORMATION
Copyright © 2015 Active-Semi, Inc. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Active-Semi reserves the right to modify its products, circuitry or product specifications without notice. Active-Semi products are not intended, designed,
warranted or authorized for use as critical components in life-support, life-critical or safety-critical devices, systems, or equipment, nor in applications
where failure or malfunction of any Active-Semi product can reasonably be expected to result in personal injury, death or severe property or environmental
damage. Active-Semi accepts no liability for inclusion and/or use of its products in such equipment or applications. Active-Semi does not assume any
liability arising out of the use of any product, circuit, or any information described in this document. No license, express, implied or otherwise, is granted
under any patents, copyrights or other intellectual property rights of Active-Semi or others. Active-Semi assumes no liability for any infringement of the
intellectual property rights or other rights of third parties which would result from the use of information contained herein. Customers should evaluate
each product to make sure that it is suitable for their applications. Customers are responsible for the design, testing, and operation of their applications and
products using Active-Semi products. Customers should provide appropriate design and operating safeguards to minimize the risks associated with their
applications and products. All products are sold subject to Active-Semi's terms and conditions of sale supplied at the time of order acknowledgment.
Exportation of any Active-Semi product may be subject to export control laws.
Active-SemiTM, Active-Semi logo, Solutions for SustainabilityTM, Power Application ControllerTM, Micro Application ControllerTM, Multi-Mode Power
ManagerTM, Configurable Analog Front EndTM, and Application Specific Power DriversTM are trademarks of Active-Semi, Inc.
ARM® is a registered trademark and CortexTM is a trademark of ARM Limited. All referenced brands and trademarks are the property of their respective
owners.
For more information on this and other products, contact [email protected] or visit www.active-semi.com.
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Rev 1.7‒April 15, 2016