Download

®
RT8241E
High Efficiency Single Synchronous Buck PWM Controller
General Description
Features
The RT8241E PWM controller provides high efficiency,
excellent transient response, and high DC output accuracy
needed for stepping down high voltage batteries to
generate low voltage CPU core, I/O, and chipset RAM
supplies in notebook computers.
z
Meet Intel VCCSA Voltage Slew Rate
z
Built-in 1% Reference Voltage
2-Bit Programmable Output Voltage with Integrated
Transition Support
Quick Load-Step Response within 100ns
4700 ppm/°°C Programmable Current Limit by Low
Side RDS(ON) Sensing
4.5V to 26V Battery Input Range
Internal Ramp Current Limit Soft-Start Control
Drives Large Synchronous Rectifier FETs
Integrated Boost Switch
Over/Under Voltage Protection
Thermal Shutdown
Power Good Indicator
RoHS Compliant and Halogen Free
z
z
z
z
z
z
z
z
z
Applications
z
z
z
z
Notebook Computers
CPU/GPU Core Supply
Chipset/RAM Supply
Generic DC/DC Power Regulator
Pin Configurations
The RT8241E is available in a WQFN-12L 2x2 package.
RT8241E
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Note :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
GND
13
3
4
5
6
9
PGOOD
8
G1
G0
7
33 : Product Code
33W
DS8241E-03 January 2014
2
10
Marking Information
Suitable for use in SnPb or Pb-free soldering processes.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
1
11
WQFN-12L 2x2
Richtek products are :
`
LGATE
PHASE
UGATE
12
EN
Package Type
QW : WQFN-12L 2x2 (W-Type)
FB
Ordering Information
CS
(TOP VIEW)
GND
The RT8241E achieves high efficiency at a reduced cost
by eliminating the current-sense resistor found in
traditional current-mode PWMs. Efficiency is further
enhanced by its ability to drive very large synchronous
rectifier MOSFETs and enter diode emulation mode at
light load condition. The buck conversion allows this device
to directly step down high voltage batteries at the highest
possible efficiency. The RT8241E is intended for CPU core,
chipset, DRAM, or other low voltage supplies as low as
0.675V.
z
VCC
The constant-on-time PWM control scheme handles wide
input/output voltage ratios with ease and provides 100ns
“instant-on” response to load transients while maintaining
a relatively constant switching frequency.
BOOT
The RT8241E supports on chip voltage programming
function between 0.675V and 0.9V by controlling GX digital
inputs.
z
W : Date Code
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8241E
Typical Application Circuit
For Fixed Voltage Regulator :
RT8241E
5 VCC
BOOT 4
R1
VCC
CBYPASS
R2
UGATE 3
C1
CIN
R4
Q2
VOUT
C2*
G0 7
G1 8
GND
COUT
R5*
LGATE 1
11 CS
12,
13 (Exposed Pad)
LOUT
PHASE 2
6 EN
VIN
Q1
9 PGOOD
Chip Enable
RCS
R3
FB 10
* : Optional
For Adjustable Voltage Regulator :
VCC
RT8241E
5 VCC
BOOT 4
R1
CBYPASS
R2
Chip Enable
UGATE 3
R4
C1
CIN
11 CS
12,
13 (Exposed Pad)
VIN
Q1
9 PGOOD
6 EN
RCS
R3
LOUT
PHASE 2
LGATE 1
R5*
Q2
G0 7
G1 8
GND
C2*
RFB1
C3*
VOUT
COUT
RFB2
FB 10
* : Optional
G0
0
0
1
1
Table 1. VID Table
G1
0
1
0
1
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
2
VFB
0.9V
0.85V
0.725V
0.675V
is a registered trademark of Richtek Technology Corporation.
DS8241E-03 January 2014
RT8241E
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
LGATE
Gate Drive Output for Low Side External MOSFET.
2
PHASE
External Inductor Connection Pin for PWM Converter. It behaves as the
current sense comparator input for low side MOSFET RDS(ON) sensing and
reference voltage for on time generation.
3
UGATE
4
BOOT
5
VCC
6
EN
Chip Enable (Active High).
7
G0
2-Bit Input Pin.
8
G1
2-Bit Input Pin.
9
PGOOD
Open Drain Power Good Indicator. High impedance indicates power is good.
10
FB
11
CS
Output Voltage Feedback Input.
Current Limit Threshold Setting Input. Connect a setting resistor to GND and
the current limit threshold is equal to 1/8 of the voltage seen at this pin.
Ground. The exposed pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
Gate Drive Output for the High Side External MOSFET.
Supply Input for High Side Driver. Connect a capacitor to the floating node
(PHASE) pin.
Control Voltage Input. Provides the power for the buck controller, the low
side driver and the bootstrap circuit for high side driver. Bypass to GND with
a 4.7μF ceramic capacitor.
12, 13 (Exposed Pad) GND
Function Block Diagram
TRIG
On-time compute
One shot
PHASE
FB
SS
(Internal)
tON
R
- COMP
GM
+
VREF
+
0.45V
+
Voltage
Programmer
85% VREF
VCC
G1
ZCD +
-
Thermal
Shutdown
SS
EN
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8241E-03 January 2014
LGATE
LG RDS(ON)
+
UGATE
PHASE
Diode
Emuation
GND
PGOOD
leakage
-
G0
UG RDS(ON)
DRV
UV Latch
S1 Q
-
BST switch
resistance
DRV
Min toff
Q
TRIG
One shot
OV Latch
S1 Q
-
1.1V
BOOT
S Q
+
10µA
+
-
1/8
CS
OC threshold
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8241E
Absolute Maximum Ratings
(Note 1)
VCC, FB, PGOOD, EN, CS, G0, G1 to GND ----------------------------------------------------------------------PHASE to GND
DC ----------------------------------------------------------------------------------------------------------------------------<20ns -----------------------------------------------------------------------------------------------------------------------z BOOT to PHASE ----------------------------------------------------------------------------------------------------------z UGATE to PHASE
DC ----------------------------------------------------------------------------------------------------------------------------<20ns -----------------------------------------------------------------------------------------------------------------------z LGATE to GND
DC ----------------------------------------------------------------------------------------------------------------------------<20ns -----------------------------------------------------------------------------------------------------------------------z Power Dissipation, PD @ TA = 25°C
WQFN-12L 2x2 -----------------------------------------------------------------------------------------------------------z Package Thermal Resistance (Note 2)
WQFN-12L 2x2, θJA ------------------------------------------------------------------------------------------------------z Junction Temperature ----------------------------------------------------------------------------------------------------z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------z Storage Temperature Range -------------------------------------------------------------------------------------------z ESD Susceptibility (Note 3)
HBM (Human Body Mode) ---------------------------------------------------------------------------------------------MM (Machine Mode) -----------------------------------------------------------------------------------------------------z
−0.3V to 6V
z
Recommended Operating Conditions
z
z
z
z
−0.3V to 32V
−8V to 38V
−0.3V to 6V
−0.3V to 6V
−5V to 7.5V
−0.3V to 6V
−2.5V to 7.5V
0.606W
165°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Input Voltage, VIN -----------------------------------------------------------------------------------------------Control Voltage, VCC -----------------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------------------
4.5V to 26V
4.5V to 5.5V
−40°C to 125°C
−40°C to 85°C
Electrical Characteristics
(VCC = 5V, VIN = 8V, VEN = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
PWM Controller
VCC Quiescent Supply Current
IQ
VCC Shutdown Current
ISHDN
CS Shutdown Current
FB Error Comparator Threshold
VFB
VOUT Voltage Range
VOUT
On-Time, Pulse Width
tON
Minimum Off-Time
tOFF
FB forced above the regulation
point, VEN = 5V
VCC current, VEN = 0V
--
500
1250
μA
--
--
1
μA
CS pull to GND
--
--
1
μA
TA = 25°C
−1
0
1
−1.5
0
1.5
0.675
--
3.3
V
--
400
--
ns
250
400
550
ns
TA = −40°C to 85°C
VFB = 0.9V (f SW = 300kHz)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
4
(Note 5)
%
is a registered trademark of Richtek Technology Corporation.
DS8241E-03 January 2014
RT8241E
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
9
10
11
μA
--
4700
--
ppm/°C
PHASE − GND
−10
--
5
mV
GND − PHASE = VCS/8
−20
0
20
mV
Current Sensing
CS Source Current
CS Source Current
Temperature Coefficient
Zero Crossing Threshold
Protection Function
Current Limit Threshold
Offset
Negative Current Limit
Threshold Offset
Under Voltage Protection
PHASE − GND = VCS/8
--
3
--
mV
UVP Detect, Falling Edge
0.41
0.45
0.49
V
UVP Fault Delay
VFB = 0.375V
--
3.5
--
μs
Over Voltage Protection
OVP Detect, Rising Edge
1.065
1.1
1.133
V
OVP Fault Delay
VCC Under Voltage Lockout
VUVLO
(UVLO) Threshold
VCC UVLO Hysteresis
ΔVUVLO
VFB = 1.183V
Falling edge, PWM disabled below
this level
--
5
--
μs
3.5
3.7
3.9
V
--
100
--
mV
VOUT Soft-Start
From EN = High to VOUT = 95%
--
0.8
--
ms
1.75
--
10
mV/μs
--
3
-
ms
Dynamic VID Slew Rate
SGX
UVP Blank Time
G0/G1 Transition
From EN signal going high
Thermal Shutdown
Thermal Shutdown
Hysteresis
Driver On-Resistance
TSD
--
150
--
ΔTSD
--
10
--
UGATE Driver Source
RUGATEsr
--
1.8
3.6
Ω
UGATE Driver Sink
RUGATEsk
BOOT−PHASE forced to 5V, UGATE
High State
BOOT−PHASE forced to 5V, UGATE
Low State
--
1.2
2.4
Ω
LGATE Driver Source
RLGATEsr
LGATE, High State
--
1.8
3.6
Ω
LGATE Driver Sink
RLGATEsk
LGATE, Low State
--
0.8
1.34
Ω
LGATE Rising (VPHASE = 1.5V)
--
30
--
ns
UGATE Rising
--
30
--
ns
VCC to BOOT, 10mA
--
--
80
Ω
Dead Time
Internal Boost Charging
Switch On-Resistance
°C
EN Threshold
EN Threshold
Voltage
Logic-High
VIH
1.8
--
--
Logic-Low
VIL
--
--
0.5
750
--
--
--
--
300
Voltage Programming (G0, G1)
G0, G1 Input
Logic-High
Threshold
Logic-Low
Voltage
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8241E-03 January 2014
V
mV
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT8241E
Parameter
Symbol
Test Conditions
PGOOD (upper side threshold determined by OVP threshold)
Falling edge, measured at FB,
Trip Threshold
with respect to reference, no
load.
Trip Hysteresis
Falling edge, FB forced below
Fault Propagation Delay
PGOOD trip threshold
Output Low Voltage
ISINK = 1mA
Leakage Current
High State, forced to 5V
Min
Typ
Max
Unit
−19
−15
−11
--
3
--
--
2.5
--
μs
--
--
0.4
V
--
--
1
μA
%
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC 51-3
thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by Design.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
6
is a registered trademark of Richtek Technology Corporation.
DS8241E-03 January 2014
RT8241E
Typical Operating Characteristics
Efficiency vs. Output Current
Switching Frequency vs. Output Current
90
Efficiency (%)
80
70
60
50
40
30
20
VIN = 8V, VOUT = 0.9V,
VCC = VEN = 5V
10
0
0.001
0.01
0.1
1
Switching Frequency (kHz)1
100
10
Output Current (A)
Efficiency vs. Output Current
70
60
50
40
30
20
VIN = 12V, VOUT = 0.9V,
VCC = VEN = 5V
0.1
1
Switching Frequency (kHz)1
Efficiency (%)
80
0.01
10
Efficiency vs. Output Current
Efficiency (%)
80
70
60
50
40
30
20
VIN = 20V, VOUT = 0.9V,
VCC = VEN = 5V
0.1
1
Output Current (A)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8241E-03 January 2014
10
Switching Frequency (kHz)1
90
0.01
350
VIN = 12V, VOUT = 0.9V,
325
VCC = VEN = 5V
300
275
250
225
200
175
150
125
100
75
50
25
0
0.001
0.01
0.1
1
10
Switching Frequency vs. Output Current
100
0
0.001
10
Output Current (A)
Output Current (A)
10
1
Switching Frequency vs. Output Current
90
0
0.001
0.1
Output Current (A)
100
10
350
VIN = 8V, VOUT = 0.9V,
325
VCC = VEN = 5V
300
275
250
225
200
175
150
125
100
75
50
25
0
0.001
0.01
350
325 VIN = 20V, VOUT = 0.9V,
VCC = VEN = 5V
300
275
250
225
200
175
150
125
100
75
50
25
0
0.001
0.01
0.1
1
10
Output Current (A)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT8241E
Standby Current vs. Input Voltage
Shutdown Current vs. Input Voltage
1.0
730
0.9
Shutdown Current (μA) 1
Standby Current (μA)
720
710
700
690
680
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
VEN = 5V, No Load
EN = GND, No Load
0.0
670
5
7
9
11
13
15
17
19
21
23
5
25
13
15
17
19
Power On from EN
Power Off from EN
21
23
25
VIN = 12V, VOUT = 0.9V,
VCC = VEN = 5V, ILOAD = 0.1A
PGOOD
(5V/Div)
EN
(5V/Div)
PHASE
(20V/Div)
PHASE
(20V/Div)
VIN = 12V, VOUT = 0.9V,
VCC = VEN = 5V, ILOAD = 0.1A
VOUT
(1V/Div)
Time (400μs/Div)
Time (1ms/Div)
DVID Up
DVID Down
0.9V
0.9V
VOUT
(50mV/Div)
VIN = 12V, VOUT = 0.9V to 0.8V,
VCC = VEN = 5V, No Load
VOUT
(50mV/Div)
VIN = 12V, VOUT = 0.8V to 0.9V,
VCC = VEN = 5V, No Load
0.8V
G1
(5V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
G1
(5V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
Time (20μs/Div)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
8
11
Input Voltage (V)
EN
(5V/Div)
0.8V
9
Input Voltage (V)
PGOOD
(5V/Div)
VOUT
(1V/Div)
7
Time (20μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8241E-03 January 2014
RT8241E
UVP
OVP
PGOOD
(5V/Div)
PGOOD
(5V/Div)
LGATE
(5V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
VOUT
(1V/Div)
VIN = 12V, VOUT = 0.9V,
VCC = VEN = 5V, No Load
Time (100μs/Div)
VOUT
(1V/Div)
VIN = 12V, VOUT = 0.9V,
VCC = VEN = 5V, No Load
Time (100μs/Div)
Load Transient Response
I LOAD
(5A/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
VIN = 12V, VOUT = 0.9V,
VCC = VEN = 5V, ILOAD = 0A to 6A
VOUT_ac
(20mV/Div)
Time (100μs/Div)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8241E-03 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT8241E
Application Information
The RT8241E is a constant on-time PWM controller which
provides four DC feedback voltages by controlling the G0
and G1 digital input. The constant on-time PWM control
scheme handles wide input/output ratios with ease and
provides 100ns “instant-on” response to load steps while
maintaining a relatively constant operating frequency and
inductor operating point over a wide range of input voltages.
The topology circumvents the poor load transient timing
problems of fixed-frequency current mode PWMs, while
avoiding the problems caused by widely varying switching
frequencies in conventional constant on-time and constant
off-time PWM schemes. The DRV TM mode PWM
modulator is specifically designed to have better noise
immunity for such a single output application.
PWM Operation
The Mach ResponseTM, DRVTM mode controller relies on
the output filter capacitor's Effective Series Resistance
(ESR) to act as a current sense resistor, so the output
ripple voltage provides the PWM ramp signal. Referring to
the function diagrams of the RT8241E, the synchronous
high side MOSFET is turned on at the beginning of each
cycle. After the internal one-shot timer expires, the high
side MOSFET is turned off. The pulse width of this one
shot is determined by the converter's input and output
voltages to keep the frequency fairly constant over the
input voltage range. Another one-shot sets a minimum
off-time (400ns typ.).
Diode-Emulation Mode
RT8241E automatically reduces switching frequency at
light-load conditions to maintain high efficiency. This
reduction of frequency is achieved smoothly and without
increasing VOUT ripple or load regulation. As the output
current decreases from heavy load condition, the inductor
current is also reduced, and eventually comes to the point
that its valley touches zero current, which is the boundary
between continuous conduction and discontinuous
conduction modes. By emulating the behavior of diodes,
the low side MOSFET allows only partial negative current
when the inductor freewheeling current becomes negative.
As the load current is further decreased, it takes longer
and longer to discharge the output capacitor to the level
that is required for the next “ON” cycle. The on-time is
kept the same as that in the heavy-load condition. In
reverse, when the output current increases from light load
to heavy load, the switching frequency increases to the
preset value as the inductor current reaches the continuous
condition. The transition load point to the light-load
operation can be calculated as follows (Figure 1) :
(VIN − VOUT )
× tON
2L
where tON is the on-time.
ILOAD ≈
IL
Slope = (VIN-VOUT) / L
IL_Peak
ILOAD = IL_Peak/2
On-Time Control (TON)
The on-time one-shot comparator has two inputs. One
input monitors the output voltage, while the other input
samples the input voltage and converts it to a current.
This input voltage proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
zero volts to VOUT, thereby making the on-time of the high
side switch directly proportional to the output voltage and
inversely proportional to the input voltage. The
implementation results in a nearly constant switching
frequency without the need of a clock generator.
0
tON
t
Figure 1. Boundary Condition of CCM/DCM
The switching waveforms may appear noisy and
asynchronous when light loading causes diode-emulation
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in DEM noise
vs. light-load efficiency is made by varying the inductor
value. Generally, low inductor values produce a broader
efficiency vs. load curve, while higher values result in higher
full-load efficiency (assuming that the coil resistance
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
10
is a registered trademark of Richtek Technology Corporation.
DS8241E-03 January 2014
RT8241E
remains fixed) and less output voltage ripple. The
disadvantages for using higher inductor values include
larger physical size and degraded load-transient response
(especially at low input voltage levels).
Output Voltage Setting (FB)
As Figure 2 shows, the output voltage can be adjusted
from 0.675V to 3.3V by setting the feedback resistors
RFB1 and RFB2. Choose RFB2 to be approximately 20kΩ,
and solve for RFB1 using the equation :
VOUT
MOSFET remains on until VFB reaches the new internal
VREF. Thus, the negative inductor current will be increased.
If the negative current become large enough to trigger
NOCP, the low side MOSFET will be turned off to prevent
large negative current from damaging the component.
Refer to the Negative Over Current Limit section for a full
description.
Gx
GND
Initial VREF
VREF
R
= VFB × (1+ FB1 )
R FB2
Final VREF
VFB
where VFB is as shown in Table 2.
UGATE
Table 2. Feedback Voltage Selection
G0 State
G1 State
Feedback Voltage
0
0
VFB = 0.9V
0
1
VFB = 0.85V
1
0
VFB = 0.725V
1
1
VFB = 0.675V
VIN
CIN
Q1
UGATE
BOOT
VOUT
PHASE
Q2
LGATE
G0
G0
G1
G1
RFB1
COUT
RFB2
FB
Figure 2. Setting VOUT with a Resistor-Divider
Output Voltage Transition Operation
The digital input control pin Gx allows VOUT to transition
to both higher and lower values. For a downward transition,
the rapid change of Gx from high to low will suddenly cause
VFB to drop to a new internal VREF. At this time the LGATE
will drive high to turn on the low side MOSFET and draw
current from the output capacitor via the inductor. LGATE
will remain on until VFB falls to the new internal VREF, at
which point a normal UGATE switching cycle begins, as
shown in Figure 3. For a down transition, the low side
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8241E-03 January 2014
LGATE
Initial VOUT
VOUT
Final VOUT
Figure 3. Output Voltage Down Transition
For an upward transition (from lower to higher VOUT) as
shown in Figure 4, Gx changes from low to high and causes
VFB to rise to a new internal VREF. This quickly trips the
VFB comparator regardless of whether DEM is active or
not, generating an UGATE on-time and causing a
subsequent LGATE to be turned on. At the end of the
minimum off-time (400ns), if VFB is still below the new
internal VREF, another UGATE on-time will be started. This
sequence continues until the FB pin exceeds the new
internal VREF.
Gx
GND
Final VREF
VREF
Initial VREF
VFB
UGATE
LGATE
Final VOUT
VOUT
Initial VOUT
Figure 4. Output Voltage Up Transition
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT8241E
If the VOUT change is significant, there can be several
consecutive cycle of UGATE on-time followed by minimum
LGATE time. This can cause a rapid increase in inductor
current: typically it only takes a few switching cycles for
inductor current to rise up to the current limit. At some
point the VFB will rise up to the new internal VREF and the
UGATE pulses will cease, but the inductor's LI2 energy
must then flow into the output capacitor. This can create
a significant overshoot, as shown in Figure 5.
Gx
GND
Final VREF
VREF
Initial VREF
VCS (mV) = RCS (kΩ ) × 10(μ A)
The Inductor current can be monitored by the voltage
between GND and the PHASE pin. Hence, the PHASE
pin should be connected to the drain terminal of the low
side MOSFET. I CS has temperature coefficient to
compensate the temperature dependency of the RDS(ON).
GND is used as the positive current sensing node, so
GND should be connected to the source terminal of the
bottom MOSFET.
While the comparison is being done during the OFF state,
VCS sets the valley level of the inductor current. Thus, the
load current at over-current threshold, ILOAD_OC, can be
calculated as follows :
ILOAD_OC =
VFB
UGATE
=
LGATE
Final VOUT
VOUT
Initial VOUT
Figure5. Output Voltage Up Transition with Overshooting
Iripple
VCS
+
8 × RDS(ON)
2
VCS
(VIN − VOUT ) × VOUT
1
+
×
8 × RDS(ON) 2 x L x fSW
VIN
In an over-current condition, the current to the load exceeds
the current to the output capacitor, thus causing the output
voltage to fall. Eventually the voltage crosses the under
voltage protection threshold and the device shuts down.
IL
IL_Peak
This overshoot can be approximated by the following
equation, where ICL is the current limit, VFINAL is the
desired set point for the final voltage, L is in μH and COUT
is in μF.
VMAX = (
ICL 2 × L
) + VFINAL 2
COUT
ILOAD
ILIM
0
t
Figure 6. “ Valley” Current Limit
Current Limit Setting (OCP)
The RT8241E has a cycle-by-cycle current limiting control.
The current limit circuit employs a unique “valley” current
sensing algorithm. If the magnitude of the current sense
signal at the CS pin is above the current limit threshold,
the PWM is not allowed to initiate a new cycle (Figure.
6). In order to provide both good accuracy and a cost
effective solution, the RT8241E supports temperature
compensated MOSFET RDS(ON) sensing. The CS pin
should be connected to GND through the trip voltage setting
resistor, RCS. The 10μA CS terminal source current, ICS,
and the trip voltage setting resistor, RCS, set the CS trip
voltage, VCS, as in the following equation.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
Negative Over Current Limit (PWM Only Mode)
The RT8241E supports cycle-by-cycle negative over
current limiting in CCM Mode only. The over current limit
is set to be negative but is the same absolute value as
the positive over current limit. If output voltage continues
to rise, the low side MOSEFT remains on. Thus, the
inductor current is reduced and reverses direction after it
reaches zero. When there is too much negative current in
the inductor, the low side MOSFET is turned off and the
current flows towards VIN through the body diode of the
high side MOSFET. Because this protection limits the
discharge current of the output capacitor, the output voltage
is a registered trademark of Richtek Technology Corporation.
DS8241E-03 January 2014
RT8241E
tends to rise, eventually hitting the over voltage protection
threshold and shutting down the device. If the device hits
the negative over current threshold again before output
voltage is discharged to the target level, the low side
MOSFET is turned off and the process repeats. It ensures
maximum allowable discharge capability when output
voltage continues to rise. On the other hand, if the output
is discharged to the target level before negative current
threshold is reached, the low side MOSFET is turned off,
the high side MOSFET is then turned on, and the device
resumes normal operation.
The high side driver is designed to drive high current, low
RDS(ON) N-MOSFET(s). When configured as a floating
driver, 5V bias voltage is delivered from the VCC supply.
The average drive current is proportional to the gate charge
at VGS = 5V times switching frequency. The instantaneous
drive current is supplied by the flying capacitor between
the BOOT and PHASE pins. A dead time to prevent shoot
through is internally generated between high side
MOSFET off to low side MOSFET on, and low side
MOSFET off to high side MOSFET on. The low side driver
is designed to drive high current, low R DS(ON) NMOSFET(s). The internal pull-down transistor that drives
LGATE low is robust, with a 0.8Ω typical on resistance. A
5V bias voltage is delivered from the VCC supply. The
instantaneous drive current is supplied by the flying
capacitor between VCC and GND.
For high current applications, some combinations of high
and low side MOSFETs might be encountered that will
cause excessive gate drain coupling, which can lead to
efficiency killing, EMI-producing shoot through currents.
This is often remedied by adding a resistor in series with
BOOT, which increases the turn-on time of the high side
MOSFET without degrading the turn-off time, as shown in
Figure 7.
VIN
BOOT
Q1
The power good output is an open-drain output and requires
a pull-up resistor. When the feedback voltage is above
1.1V or below 0.45V, PGOOD will be pulled low. PGOOD
is allowed to be high until soft-start ends and the output
reaches 89% of its set voltage. There is a 2.5μs delay
built into PGOOD circuitry to prevent false transition.
When Gx changes, PGOOD remains in its present state
for 32 clock cycles. Meanwhile, VOUT or VFB regulates to
the new level.
POR, UVLO and Soft-Start
MOSFET Gate Driver (UGATE, LGATE)
UGATE
Power Good Output (PGOOD)
CIN
R
PHASE
Power on reset (POR) occurs when VCC rises above 3.7V
(typ.). After POR is triggered, the RT8241E will reset the
fault latch and prepare the PWM for operation. Below 3.6V
(typ.), the VCC under voltage lockout (UVLO) circuitry
inhibits switching by keeping UGATE and LGATE low. A
built-in soft-start is used to prevent surge current from the
power supply input after EN is enabled. It clamps the
ramping of the internal reference voltage which is compared
with the FB signal. The typical soft-start duration is 0.8ms.
Over Voltage Protection (OVP)
The output voltage can be continuously monitored for over
voltage protection. When VFB exceeds 1.1V, over voltage
protection is triggered and the low side MOSFET is latched
on. This activates the low side MOSFET to discharge the
output capacitor. The RT8241E is latched once OVP is
triggered and can only be released by VCC or EN power
on reset. There is a 5μs delay built into the over voltage
protection circuit to prevent false transitions.
Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. When VFB is less than 0.45V, under
voltage protection is triggered and then both UGATE and
LGATE gate drivers are forced low. In order to remove the
residual charge on the output capacitor during the under
voltage period, if PHASE is greater than 1V, the LGATE
is forced high until PHASE is lower than 1V. There is a
3.5μs delay built into the under voltage protection circuit
to prevent false transitions. During soft-start, the UVP
blanking time is 3ms.
Figure 7. Reducing the UGATE Rise Time
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8241E-03 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT8241E
Output Inductor Selection
The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as follows :
t × (VIN − VOUT )
L = ON
LIR × ILOAD(MAX)
where LIR is the ratio of peak-to-peak ripple current to the
maximum average inductor current. Select a low pass
inductor having the lowest possible DC resistance that
fits in the allowed dimensions. Ferrite cores are often the
best choice, although powdered iron is inexpensive and
can work well at 200kHz. The core must be large enough
not to saturate at the peak inductor current (IPEAK) :
IPEAK = ILOAD(MAX) +
LIR
× ILOAD(MAX)
2
Output Capacitor Selection
The output filter capacitor must have ESR low enough to
meet output ripple and load transient requirement, yet have
high enough ESR to satisfy stability requirements. Also,
the capacitance must be high enough to absorb the inductor
energy going from a full load to no load condition without
tripping the OVP circuit. For CPU core voltage converters
and other applications where the output is subject to violent
load transient, the output capacitor's size depends on how
much ESR is needed to prevent the output from dipping
too low under a load transient. Ignoring the sag due to
finite capacitance :
ESR ≤
VP−P
ILOAD(MAX)
In non-CPU applications, the output capacitor's size
depends on how much ESR is needed to maintain at an
acceptable level of output voltage ripple :
ESR ≤
VP−P
LIR × ILOAD(MAX)
Organic semiconductor capacitor(s) or special polymer
capacitor(s) are recommended.
Output Capacitor Stability
Stability is determined by the value of the ESR zero relative
to the switching frequency. The point of instability is given
by the following equation :
fESR =
f
1
≤ SW
2π × ESR × COUT
4
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
Do not put high value ceramic capacitors directly across
the outputs without taking precautions to ensure stability.
Large ceramic capacitors can have a high ESR zero
frequency and cause erratic and unstable operation.
However, it is easy to add sufficient series resistance by
placing the capacitors a couple of inches downstream from
the inductor and connecting VFB divider close to the
inductor. There are two related but distinct ways including
double pulsing and feedback loop instability to identify
the unstable operation. Double pulsing occurs due to noise
on the output or because the ESR is too low such that
there is not enough voltage ramp in the output voltage
signal. This “fools” the error comparator into triggering a
new cycle immediately after the 400ns minimum off-time
period has expired. Double-pulsing is more annoying than
harmful, resulting in nothing worse than increased output
ripple. However, it may indicate the possible presence of
loop instability, which is caused by insufficient ESR. Loop
instability can result in oscillation at the output after line
or load perturbations that can trip the over voltage
protection latch or cause the output voltage to fall below
the tolerance limit. The easiest method for stability
checking is to apply a very zero-to-max load transient
and carefully observe the output voltage ripple envelope
for overshoot and ringing. It helps to simultaneously monitor
the inductor current with an AC probe. Do not allow more
than one ringing cycle after the initial step-response underor overshoot.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications of
the RT8241E, the maximum junction temperature is 125°C
is a registered trademark of Richtek Technology Corporation.
DS8241E-03 January 2014
RT8241E
and TA is the ambient temperature. The junction to ambient
thermal resistance, θJA, is layout dependent. For WQFN12L 2x2 packages, the thermal resistance, θJA, is 165°C/
W on a standard JEDEC 51-3 single-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (165°C/W) = 0.606W for
WQFN-12L 2x2 package
Maximum Power Dissipation (W)1
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. For the RT8241E package, the derating
curve in Figure 8 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to converter
instability. For best performance of the RT8241E, the
following guidelines should be strictly followed.
`
Connect an RC low-pass filter from VCC, (1μF and 10Ω
are recommended). Place the filter capacitor close to
the IC.
`
Keep current limit setting network as close as possible
to the IC. Routing of the network should be kept away
from high voltage switching nodes to prevent it from
coupling.
`
Connections from the drivers to the respective gate of
the high side or the low side MOSFET should be as
short as possible to reduce stray inductance.
`
All sensitive analog traces and components pertaining
to VOUT, FB, GND, EN, PGOOD, CS and VCC should
be placed away from high voltage switching nodes such
as PHASE, LGATE, UGATE, or BOOT nodes to prevent
it from coupling. Use internal layer(s) as ground plane(s)
and shield the feedback trace from power traces and
components.
Four-Layer PCB
` Current sense connections must always be made using
0
25
50
75
100
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.
125
Ambient Temperature (°C)
Figure 8. Derating Curves for the RT8241E Package
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8241E-03 January 2014
`
Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT8241E
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
1.900
2.100
0.075
0.083
E
1.900
2.100
0.075
0.083
e
0.400
0.016
D2
0.850
0.950
0.033
0.037
E2
0.850
0.950
0.033
0.037
L
0.250
0.350
0.010
0.014
W-Type 12L QFN 2x2 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
16
DS8241E-03 January 2014