® RT9420 Host-Side Single Cell Lithium Battery Gauge General Description Features The RT9420 is a compact, host-side fuel gauge IC for lithium-ion (Li+) battery-powered systems. For the embedded Fuel Gauge function, the state-ofcharge (SOC) calculation is based on the battery voltage information and the dynamic difference between battery voltage and relaxed OCV, by using iteration to estimate the increasing or decreasing SOC. Voltage-based algorithm can support smoothly SOC and does not accumulate error with time and current. That is an advantage compared to coulomb counter which suffer from SOC drift caused by current-sense error and battery self-discharge. The disadvantage of voltage-based fuel gauge, it can report incremental SOC(%), but can't report capacity (mAh). Host-Side Fuel Gauging Precision Voltage Measurement ±12.5mV Accuracy Accurate Relative Capacity (RSOC) Calculated from Voltaic Gauge Algorithm with Temperature Compensation No Accumulation Error on Capacity Calculation No Battery Relearning Necessary No Current Sense Resistor Required External Alarm/Interrupt for Low Battery Alert I2C Compatible Interface Low Power Consumption Applications A quick sensing operation provides a good initial estimate of the battery's SOC. This feature allows the IC to be located on system side, reducing cost and supply chain constraints on the battery. Measurement and estimated capacity data sets are accessed through an I2C interface. Smartphones Tablet PC Digital Still Cameras Digital Video Cameras Handheld and Portable Applications The RT9420 is available in the WDFN-8L 2x3 package. Simplified Application Circuit PACK+ + PMIC_VBAT IO Power RT9420 R1 VBAT R2 R3 System Processor VDD IRQ ALERT C1 Li + Protection Circuit QS TEST GND SDA SCL SDA SCL C2 PACKPMIC_GND Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9420-01 October 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9420 Ordering Information Pin Configurations RT9420 (TOP VIEW) TEST VBAT VDD GND Lead Plating System G : Green (Halogen Free and Pb Free) 1 2 3 8 GND Package Type QW : WDFN-8L 2x3 (W-Type) 4 7 6 9 5 SDA SCL QS ALERT Note : WDFN-8L 2x3 Richtek products are : RoHS compliant and compatible with the current require- Marking Information ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 06 : Product Code W : Date Code 06W Function Pin Description Pin No. Pin Name Pin Function 1 TEST Test Pin. Connect to GND pin during normal operation. 2 VBAT Battery Voltage Measurement Input. 3 VDD Processor Power Input. Decouple with a 10nF capacitor. 4 GND Ground. 5 ALERT Alert Output. When SOCLow condition is detected, it outputs low as interrupt signal. Connect to interrupt input of the system processor. Connect to GND if not used. 6 QS Quick Sensing Input. Active high to restart the calculation. Pull low to GND during normal operation. 7 SCL Serial Clock Input. Slave I C clock line for communication with system. 8 SDA Serial Data Input. Slave I C data line for communication with system. 9 (Exposed Pad) GND The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 2 2 Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS9420-01 October 2014 RT9420 Function Block Diagram VDD I C Interface SDA SCL Voltaic Gauge Algorithm Controller QS ALERT TEST GND VBAT 12-bit ADC 2 Battery OCV Model Operation 12-bit ADC Controller Analog-to-Digital Converter. It converts the voltage input from VBAT pin to target value. The controller takes care of the control flow of system routine, ADC measurement flow, algorithm calculation and alert determined. Battery OCV Model Parameters for battery characteristics. I2C Interface The fuel gauge registers can be accessed through the I2C Voltaic Gauge Algorithm Interface. The RT9428 calculates and determines that the embedded Fuel Gauge calculates and determines the Li+ battery SOC according to battery voltage only. The algorithm estimates the increasing or decreasing SOC by an iteration model according to the difference between battery voltage and the battery OCV. The dynamic voltaic information can effectively emulate the Li+ battery behavior and determines the SOC (%), but can't report capacity (mAh). Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9420-01 October 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9420 Absolute Maximum Ratings (Note 1) Voltage on TEST Pin Relative to GND -------------------------------------------------------------------------------Voltage on VBAT Pin Relative to GND ------------------------------------------------------------------------------Voltage on All Other Pins Relative to GND -------------------------------------------------------------------------SCL, SDA, QS, ALERT to GND --------------------------------------------------------------------------------------VBAT to GND --------------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WDFN-8L 2x3 -------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WDFN-8L 2x3, θJA --------------------------------------------------------------------------------------------------------WDFN-8L 2x3, θJC --------------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------- Recommended Operating Conditions −0.3V to 5.5V −0.3V to 5.5V −0.3V to 6V −0.3V to 5.5V −0.3V to 5V 3.17W 31.5°C/W 7.5°C/W 260°C 150°C −65°C to 150°C (Note 3) Supply Voltage, VDD ----------------------------------------------------------------------------------------------------- 2.5V to 4.5V Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (2.5V ≤ VDD ≤ 4.5V, TA = 25°C unless otherwise specified) Parameter (Note 4) Symbol Test Conditions Min Typ Max Unit -- 22 40 A -- 0.5 1 -- 1 3 3.5 1 3.5 12.5 -- 12.5 25 -- 25 15 -- -- DC Section Active Current IACTIVE Sleep-Mode Current (Note 5) ISLEEP Time-Base Accuracy tERR Voltage Measurement Error VGERR VBAT Pin Input Impedance RVBAT SCL, SDA, QS Input Voltage VDD = 2.5V TA = 20C to 70C (Note 4) VBAT = 4V Logic-High All voltage reference to GND 1.4 -- -- Logic-Low All voltage reference to GND -- -- 0.5 A % mV M V SDA Output Logic-Low VOL_SDA IOL_SDA = 4mA, All voltage reference to GND -- -- 0.4 V ALERT Output Logic-Low VOL_ALERT IOL_ALERT = 2mA, All voltage reference to GND -- -- 0.4 V SCL, SDA Pull-Down Current IPD VDD = 4.5V, VSCL = VSDA = 0.4V -- 0.2 0.4 A Bus Low Timeout tSLEEP (Note 6) 2 -- 3 s Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS9420-01 October 2014 RT9420 Parameter Symbol Test Conditions Min Typ Max Unit 10 -- 250 kHz 1.3 -- -- s 0.6 -- -- s 2 I C Interface Clock Operating Frequency f SCL Bus Free Time Between a STOP and START Condition tBUF Hold Time After START Condition tHD_STA Low Period of the SCL Clock tLOW 1.3 -- -- s High Period of the SCL Clock tHIGH 0.6 -- -- s Setup Time for a Repeated START Condition tSU_STA 0.6 -- -- s Data Hold Time tHD_DAT (Note 8, Note 9) 0.2 -- 0.9 ms Data Setup Time tSU_DAT (Note 8) 100 -- -- ns Clock Data Rising Time tR 20 -- 300 ns Clock Data Falling Time tF 20 -- 300 ns Set-Up Time for STOP Condition tSU_STO 0.6 -- -- s Spike Pulse Widths Suppressed by Input Filter tSP (Note 10) 0 -- 50 ns Capacitive Load for Each Bus CB Line (Note 11) 400 -- -- pF -- -- 60 pF SCL, SDA Input Capacitance (Note 7) (Note 7) CBIN Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. Specifications are 100% tested at T A = 25°C. Limits over the operating range are guaranteed by design and characterization. Note 5. SDA, SCL = GND; QS, ALERT idle. Note 6. The RT9420 enter sleep mode after SCL and SDA low for longer than 3s. Note 7. fSCL must meet the minimum clock low time plus the rise/fall time. Note 8. The maximum tHD_DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 9. This device internally provides a hold time of at least 75ns for the SDA signal to bridge the undefined region of the falling edge of SCL. Note 10. Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant. Note 11. CB total capacitance of one bus line in pF. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9420-01 October 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9420 Typical Application Circuit PMIC_VBAT PACK+ R1 1k + IO Power VBAT R3 4.7k System Processor VDD IRQ ALERT C1 1µF Li + Protection Circuit R2 150 RT9420 QS TEST SDA SCL SDA SCL C2 10nF GND PACKPMIC_GND Timing Diagram SDA tLOW tF tR tSU_DAT tF tHD_STA tSP tBUF tR SCL S tHD_STA tHD_DAT tHIGH Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 tSU_STA tSU_STO Sr P S is a registered trademark of Richtek Technology Corporation. DS9420-01 October 2014 RT9420 Typical Operating Characteristics (TA = 25°°C, battery is Sanyo UF534553F, unless otherwise specified.) Quiescent Current vs. Supply Voltage Voltage ADC Error vs. Temperature 25 40 20 Voltage ADC Error (mV) 30 25 20 70°C 25°C −20°C 15 10 5 15 VBAT = 3V VBAT = 3.6V VBAT = 4.3V 10 5 0 -5 -10 -15 -20 0 -25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 -20 4.5 -5 10 Supply Voltage (V) 40 55 70 Constant Discharge C/2 SOC Accuracy * 10 100 10 90 8 90 8 80 6 80 6 70 4 70 4 60 2 60 2 50 0 50 0 40 -2 40 -2 30 -4 Reference SOC RT9420 SOC Error 20 10 0 0 2 4 6 8 10 12 14 16 18 20 -8 10 -10 0 -6 -8 -10 2 4 6 8 10 12 14 Time (h) Zigzag Discharge C/2 SOC Accuracy * 90 8 80 6 70 4 60 2 50 0 40 -2 -4 Reference SOC RT9420 SOC Error SOC Error (%) * : Sample accuracy with custom parameters into the IC. 10 10 -4 Reference SOC RT9420 SOC Error 0 20 100 20 30 -6 Time (h) 30 SOC (%) 100 SOC Error (%) SOC (%) Constant Discharge C/4 SOC Accuracy * SOC (%) 25 Temperature (°C) -6 -8 0 -10 0 2 4 6 8 10 12 Time (h) Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9420-01 October 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 SOC Error (%) Quiescent Current (µA) 35 RT9420 Application Information Voltaic Gauge Theory and Performance The embedded Fuel Gauge calculates and determines the Li+ battery SOC according to battery voltage only. The algorithm estimates the increasing or decreasing SOC by an iteration model according to the difference between battery voltage and the battery OCV. The dynamic voltaic information can effectively emulate the Li+ battery behavior and determines the SOC(%), but can't report capacity(mAh). The calculation is based on the battery voltage information and the dynamic difference between battery voltage and relaxed OCV, by using iteration algorithm to estimate the increasing or decreasing SOC to calculate SOC. Comparing to coulomb counter based fuel gauge solution; voltaic gauge does not accumulate error with time and current. The coulomb counter based fuel gauge suffers from SOC drift due to current-sense error and cell selfdischarge. Even there is a very small current sensing error, the coulomb counter accumulates the error from time to time. The accumulated error can be eliminated by only full charged or full discharged. The VoltaicGauge estimates battery SOC by only voltage information and will not accumulate error because it does not rely on battery current information. Power On When the IC is powered on by the battery insertion, the IC measures the battery voltage quickly and predicts the first SOC according to the voltage. The first SOC would be accurate if the battery has been well relaxed for over 30 min. Otherwise, the initial SOC error occurs. However, the initial SOC error will be convergent and the SOC will be adjusted gradually and finally approach to the accurate SOC without accumulation error. Quick Sensing A Quick Sensing operation allows the RT9420 to restart sensing and SOC calculation. It has the same behavior as power on. The operation is used to reduce the initial SOC error caused by unwell power-on sequence. A Quick Sensing operation could be performed by either a rising edge on the QS pin or I2C Quick Sensing command to the Control register. Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 QS pin active high to restart the SOC calculation, and pull low to GND during normal operation. Temperature Compensation To maximize the SOC performance, the host must measure battery temperature periodically, and compensate the VGCOMP Voltaic-Gauge parameter at least once per minute. Contact Richtek for instructions for temperature compensation. ALERT Interrupt The RT9420 monitors the SOC and reports the alert condition if the SOC change over 1% or if the SOC falls below the SOCLow which is in the Config (0Dh) register. When alert condition occurs, the RT9420 outputs logiclow to the ALERT pin and sets 1 to the [Alert] bit in the Config register and sets 1 to the corresponding alert flag in the Status register. The only three ways to recover the alert condition is writing 0 to clear [Alert] bit or writing 0 to clear both [SL] and [SC] bit or power on reset. Before the recovery, the [Alert] bit will keep 1 and the ALERT pin will keep logic-low. It can't recover the alert condition by entering sleep mode. Please note that the SOC low alert detection function is enable when power on. Sleep Mode RT9420 will enter sleep mode if host pulls low both SDA and SCL to logic-low at least 2.5s. All operation such as voltage measurement and SOC calculation are halted and power consumption is reduced under 3μA in sleep mode. Any rising edge of SDA or SCL will transfer IC back to active mode immediately. The other way to enter sleep mode is write [Sleep] bit in the Config register to 1 through I2C communication, and the only way to exit sleep mode is to write [Sleep] bit to logic 0 or power on reset the IC. is a registered trademark of Richtek Technology Corporation. DS9420-01 October 2014 RT9420 Initialization I2C Register The RT9420 can be reset by writing an initialization command to MFA resister. The behavior of initialization is the same as power on reset. The RT9420 supports the following 16-bit I2C registers: VBAT, SOC, Control, Device ID, Config and MFA. The register writing is valid when all of 16 bits data are transferred; otherwise, the write data will be ignored. The valid register addresses are defined in Table 1. Other remaining addresses are reserved. Table 1. I2C Register Address (Hex) Register 02h-03h VBAT 04h-05h Read/ Write Default (Hex) It reports voltage measured from the input of VBAT pin. R -- SOC It reports the SOC result calculated by voltaic-gauge algorithm. R -- 06h-07h Control It's the command interface for special function such as Quick Sensing. W -- 08h-09h Device ID It reports the device ID. R -- 0Ah Status It reports alert status. R/W 01h 0Bh dSOC It reports approximately incremental SOC in unit of 1% per hour. R -- 0Ch-0Dh Config The Config register includes the parameter of compensation, setting of sleep mode and SOCLow threshold. It also indicates the alert status. R/W 321Ch W -- Description 0Eh-0Fh RSVD FEh-FFh Manufacturer Access. Sends special commands to the IC for the manufacturing. MFA VBAT The VBAT register is a read only register that reports the measured voltage at VBAT pin. The VBAT is reported in units of 1.25mV. The first report is made after chip POR with 250ms delay and then updates 1s periodically. Figure 1 shows the VBAT register format. MSB-Address 02h 11 10 2 2 MSB 9 2 8 2 7 2 6 2 LSB-Address 03h 5 2 4 3 2 2 2 2 LSB MSB 1 2 0 2 0 0 MSB-Address 04h 7 2 2 MSB 6 2 5 2 4 2 3 2 2 2 LSB-Address 05h 1 0 -1 2 2 2 LSB MSB -2 2 -3 2 -4 2 -5 2 -6 2 -7 -8 2 LSB Unit : 1% Figure 2. SOC Register Control 0 0 LSB 0 : Bits Always Read Logic 0 Unit : 1.25mV Figure 1. VBAT Register The Control register allows the host processor to send special commands to the IC (Table2). Valid Control register write values are listed as follows. All other Control register values are reserved. SOC The SOC register is a read only register that returns the relative state of charge of the cell as calculated by the voltaic gauge algorithm. The result is displayed as a percentage of the cell's full capacity. The high byte is reported in units of %. The low byte is reported in units of 1/256%. Figure 2 shows the SOC register format. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9420-01 October 2014 Table 2. Control Register Commands Value Command Description 4000h Quick Sensing Restart sensing and SOC calculation is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT9420 Device ID [SOCLow] The Device ID register is a read only register that contains a value indicating the production ID of the RT9420. The SOCLow is a 5-bit value for setting the low battery alert threshold and defined as 2's-complement form. The programming unit is 1% and range is 32% to 1%. (00000 = 32%, 10001 = 15%, 11100 = 4%, 11111 = 1%). The power on reset value for SOCLow is 4% or 1Ch. dSOC The dSOC register is a read only registert that reports the approximately incremetal SOC in unit of 1% per hour. MFA Config The Config register includes the parameter of compensation, setting of sleep mode and SOCLow threshold. It also indicates the alert status. The format of Config is shown in Figure 3. VGCOMP is the setting to optimize IC performance for different cell chemistries or temperatures. Contact Richtek for instructions for optimization. The power on reset value for VGCOMP is 32h. Register 0x0C Bit 7:0 7 6 5 4:0 0x0D Description VGCOMP Sleep SCEN Alert SOCLow Figure 3. Config Register The MFA register allows the host processor to send special commands to the chip for manufacturing. Table 3. MFA Register Commands Value Command Description 5400h Initialization Reset the IC Status The Status register reports the alert status of RT9420. When any alert flag of Status register is set, the [Alert] flag of Config register will be set. [SC] The [SC] flag is set when SOC changes at least 1%. The [SC] flag is cleared by either host writing 0 to clear or a reset condition occurs. The power on reset value of [SC] is logic 0. [SL] [Sleep] Writing [Sleep] to logic 1 forces the IC to enter Sleep mode. Writing [Sleep] to logic 0 forces the IC to exit Sleep mode. The power on reset value for [Sleep] is logic 0. The [SL] flag is set when SOC is lower than SOC threshold set by [SOCLow] bits. The [SL] flag is cleared by either host writing 0 to clear or a reset condition occurs. The power on reset value of [SL] is logic 0. [SCEN] [RI] Writing [SCEN] to logic 1 to enable SOC Change Alert. When SOC Change Alert is enabled, the [SC] flag is set to 1 if SOC is changed at least 1%. The power on reset value for [SCEN] is logic 0. The [RI] flag is set at POR and could be cleared after configuration. The power on reset value of [RI] is logic 1. Register [Alert] The [Alert] bit is set by the IC when the alert condition occurs. The [Alert] bit is cleared by either host writing 0 to clear or a reset condition occurs. The power on reset value for [Alert] is logic 0. Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 0x0A Bit 7: 6 5 4 3: 1 0 Description Reserved SC SL Reserved RI Figure 4. Status Register is a registered trademark of Richtek Technology Corporation. DS9420-01 October 2014 RT9420 Battery PACK PMIC_VBAT IO Power Pack+ R1 1k R2 150 RT9420 VBAT + VDD ALERT IRQ SDA SCL SDA SCL C1 1µF Protection IC (Li+/Polymer) QS TEST System Processor R3 4.7k C2 10nF GND Pack- System GND PMIC_GND Figure 5. RT9420 Application Example with Alert Interrupt Figure 5 presents a single cell battery-powered system application. The RT9420 is used on system side and direct powered from the battery. The RC filter saves the noise for IC power supply and voltage measurement on VBAT pin. To reduce the I-R drop effect, make the connection of VBAT as close as possible to the battery pack. The ALERT pin provides a battery low interrupt signal to system processor when capacity low is detected. The QS pin is unused in this configuration, so it needs to be tied to GND. I2C Bus Interface Figure 6 shows the timing diagram of the I2C interface. A byte of data consists of 8 bits ordered MSB first and the LSB followed by the Acknowledge bit. The RT9420 address is 0110110 (6Ch) and is a receive only (slave) device. The second word selects the register to which the data will be written. The third word contains data to write to the selected register. Table 4 applies to the transaction formats. S SAddr W A CAddr A Data0 A Data1 A P Write Protocol S SAddr A W A Data1 CAddr A Sr SAddr R A Data0 N P Read Protocol Figure 6. I2C Timing Diagram The RT9420 communicates with a host (master) by using the standard I2C 2-wire interface. After the START condition, the I2C master sends 8-bit data, consisting of 7-bit slave address and a following data direction bit (R/W). Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9420-01 October 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT9420 Table 4. 2-Wire Protocol Symbol S Description START bit SAddr Slave address (7bit) CAddr Command address (byte) Data Data byte written by master Symbol Description Sr Repeated START R/W Read : R/W = 1; Write : R/W = 0 P STOP bit Data Data byte returned by slave A Acknowledge bit written by master A Acknowledge bit returned by slave N No acknowledge bit written by master N No acknowledge bit returned by slave Thermal Considerations PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. For WDFN-8L 2x3 package, the thermal resistance, θJA, is 31.5°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be 4.0 Maximum Power Dissipation (W)1 For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : Four-Layer PCB 3.2 2.4 1.6 0.8 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 7. Derating Curve of Maximum Power Dissipation calculated by the following formula : PD(MAX) = (125°C − 25°C) / (31.5°C/W) = 3.17W for WDFN-8L 2x3 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 7 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS9420-01 October 2014 RT9420 Layout Considerations VDD and GND need direct connect to Battery for preventing the affect of I-R drop. PACK+ Input filter must be placed as close as possible to the VDD and VBAT. Positive Power Bus PMIC_VBAT PACK- C1 TEST VBAT VDD C2 GND R2 1 2 3 4 8 GND PACK- R1 9 7 6 5 Connect to GND, SDA if not used. SCL QS R3 IO Power ALERT Negative Power Bus PMIC_GND Battery PACK Figure 8. PCB Layout Guide Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9420-01 October 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT9420 Outline Dimension D D2 L E E2 SEE DETAIL A 1 e b 2 A A1 1 2 1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 D 1.900 2.100 0.075 0.083 D2 1.550 1.650 0.061 0.065 E 2.900 3.100 0.114 0.122 E2 1.650 1.750 0.065 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 8L DFN 2x3 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 14 DS9420-01 October 2014