ETC PSB4600F

ICs for Communications
PCI Interface for Telephony/Data Applications
PITA
PSB 4600 Version 1.2
Preliminary Data Sheet 12.98
DS 1
PSB 4600
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Edition 12.98
Published by Siemens AG,
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81541 München
© Siemens AG 1998.
All Rights Reserved.
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PSB 4600
Organization of this Data Sheet
This Preliminary Data Sheet is divided into 13 chapters:
• Chapter 1, Features
Describes the compliants, interfaces and the compatibilities of the PITA.
• Chapter 2, Applications realized with the PITA
Describes the applications realized with the PITA.
• Chapter 3, Construction of the PITA
Shows a block diagram and describes the interfaces and their functions.
• Chapter 4, Communication with the PITA
Describes the different controllers, registers and the power management of the
PITA.
• Chapter 5, Communication with external Components
Gives a general description of the interfaces and modes of the PITA.
• Chapter 6, Configuration of the PITA
Describes the pinstrapping and pins used for pinstrapping during system reset.
• Chapter 7, Pinning
Describes the pins, types of pins and the characteristics of the interfaces.
• Chapter 8, Package Outlines
Describes the package outlines.
• Chapter 9, Precautions
Describes electrical maximum ratings and electrical characteristics.
• Chapter 10, Configuration Space Register of the PITA
Contains maps and descriptions of the PCI Configuration Space Registers of
the PITA.
• Chapter 11, Internal Register of the PITA
Contains maps and descriptions of the Internal Registers of the PITA.
• Chapter 12, Abbreviations
Describes abbreviations occuring in this data sheet.
• Chapter 13, Index
Semiconductor Group
3
Preliminary Data Sheet 12.98
PSB 4600
Important Notes about this Data Sheet
________________________________________
What’s New?
The organization of the structure follows the guidelines of Information Mapping®.
________________________________________
What is Information Mapping®?
This is a research based method for the
– analysis
– structure
– presentation
of user-orientated manuals.
________________________________________
Major Changes
Instead of the used chapters with mono causal descriptions you now get
– all information
– for a scope
– under the corresponding heading.
________________________________________
The Intention
This Data Sheet is intended to be
–
–
–
–
–
easily surveyed
increasingly readable
customized applicable
practice-orientated
offering the quickest possible way to the required information.
________________________________________
Semiconductor Group
4
Preliminary Data Sheet 12.98
PSB 4600
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2
Applications realized with the PITA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
3
Construction of the PITA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.3
4.3.1
4.3.2
4.4
Communication with the PITA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Information about the PCI Configuration Space . . . . . . . . . . . . . . . . . . 4-3
Access to the PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Other Registers of the PCI Configuration Space . . . . . . . . . . . . . . . . . 4-11
PCI Master Target Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Supported PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Transaction Type Single Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Transaction Type Single Data Write . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Transaction Type Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Transaction Type Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Transaction Type Fast Back to Back . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Information about the Power Management States . . . . . . . . . . . . . . . 4-25
Configuration Space Registers of the Power Management . . . . . . . . . 4-28
Interrupt Control Register - Retry Counter . . . . . . . . . . . . . . . . . . . . . . . . 4-35
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
Communication with external Components . . . . . . . . . . . . . . . . . . . . . 5-1
Serial DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
IOM-2 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
IOM-2 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
IOM-2 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
IOM-2 Modes - Supplementary Description . . . . . . . . . . . . . . . . . . . . . 5-24
Single Modem Mode V2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Single Modem Mode ALIS V3.X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
Dual Modem/Modem+Voice Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
Loop Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47
ALE after System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50
ALE after internal Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51
ALE after setting the Parallel Interface Mode Bit . . . . . . . . . . . . . . . . . 5-52
Non Multiplexed Mode (Write Transaction) . . . . . . . . . . . . . . . . . . . . . 5-53
Non Multiplexed Mode (Read Transaction) . . . . . . . . . . . . . . . . . . . . . 5-54
Multiplexed Mode (Write Transaction) . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
Multiplexed Mode (Read Transaction) . . . . . . . . . . . . . . . . . . . . . . . . . 5-56
Transaction Disconnect with Target Abort . . . . . . . . . . . . . . . . . . . . . . 5-57
Transaction Termination with Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60
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Preliminary Data Sheet 12.98
PSB 4600
5.2.10
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.4
5.4.1
5.4.2
5.4.3
Timing of the Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62
General Purpose I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
Information about the GP I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . 5-66
Timing of the GP I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68
Internal Registers of the GP I/O Interface . . . . . . . . . . . . . . . . . . . . . . 5-69
Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-76
Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78
Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80
Usage of the GP I/O Interface as ALIS V2.1 Control Interface . . . . . . 5-82
SPI EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84
Information about the SPI EEPROM Interface . . . . . . . . . . . . . . . . . . 5-85
Timing of the SPI EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . 5-88
Internal Registers for the SPI EEPROM Interface . . . . . . . . . . . . . . . . 5-90
6
Configuration of the PITA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
8
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
9
9.1
9.2
9.3
9.4
Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
10
10.1
10.2
10.3
Configuration Space Register of the PITA . . . . . . . . . . . . . . . . . . . . . 10-1
Description of the Register Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Configuration Space Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Registers which do not occur elsewhere in the Data Sheet . . . . . . . . . 10-13
11
11.1
11.2
11.3
Internal Register of the PITA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Description of the Register Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Internal Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Registers which do not occur elsewhere in the Data Sheet . . . . . . . . . 11-10
12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
13
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Semiconductor Group
6
Preliminary Data Sheet 12.98
PSB 4600
Introduction
________________________________________
What is the PITA?
The PITA is a cost-effective PCI bridge for industrial and communication
applications.
________________________________________
The PITA can be used in
• PCI ISDN cards.
• PCI hardware modems.
• PCI software modems.
• Industrial PCI bridge applications.
________________________________________
Interfaces of the PITA
The PITA offers the following interfaces:
Interfaces
to find in
PCI Master Target Controller
see chapter “4.2” on page 4-13
Serial DMA Interface
see chapter “5.1” on page 5-2
Parallel Interface
see chapter “5.2” on page 5-47
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0-1
Preliminary Data Sheet 12.98
PSB 4600
The PITA offers the following interfaces:
Interfaces
to find in
General Purpose I/O Interface
see chapter “5.3” on page 5-65
SPI EEPROM Interface
see chapter “5.4” on page 5-84
Semiconductor Group
0-2
Preliminary Data Sheet 12.98
PSB 4600
Features
1
Features
________________________________________
Compliant with
• PC98
• PCI Bus Specification Version 2.2
• PCI Power Management Specification Version 1.0
________________________________________
Interfaces
• PCI Master Target Interface
– PCI 2.2 compliant
– 32 bit
– 33 MHz
• Serial Interface
– Supports IOM-2 Modes
– Supports serial interface to the ALIS chip-set family
– DMA Controller for serial communication
– 16 word FIFOs for each direction
• Parallel Interface
With chip select logic supporting up to three external components
• General Purpose I/O Interface
With interrupt capability
• SPITM Interface
for optional EEPROM
________________________________________
Semiconductor Group
1-1
Preliminary Data Sheet 12.98
PSB 4600
Features
________________________________________
Compatibility
• ALIS V2.1 PSB 4596
• ALIS V3.X PSB 4596
• ISDN IOM-2 Components, e.g.:
– IEC-Q family
– SBCX
• Components consisting of a parallel multiplexed or non multiplexed Intel
Interface, e.g:
– IPAC
– ISAC
– ISAR
________________________________________
Semiconductor Group
1-2
Preliminary Data Sheet 12.98
PSB 4600
Applications realized with the PITA
2
Applications realized with the PITA
________________________________________
Overview
The PITA provides a PCI interface supporting a serial and parallel interface,
including communication applications such as analog software modems and
hardware ISDN modems.
________________________________________
Note
The name ALIS referes to the ALIS chip-set (Analog Line Interface Solution),
consting of ALIS-A (PSB4595) and ALIS-D (PSB4596).
________________________________________
ISDN-S Interface Application with the IPAC
PSB 2115
IPAC
S-Interface
Microcontroller
Interface
SPI
PSB 4600
PITA
EEPROM
PCI Bus
________________________________________
Semiconductor Group
2-1
Preliminary Data Sheet 12.98
PSB 4600
Applications realized with the PITA
________________________________________
ISDN-U Interface Application with the 3PAC and IEC-Q TE
PSB 2113
3PAC
PSB 21911
IEC-Q TE
U-Interface
Microcontroller
Interface
SPI
PSB 4600
PITA
EEPROM
PCI Bus
________________________________________
Software Modem using the ALIS-A and ALIS-D with PCI Interface
PSB 4596
ALIS-D
PSB 4595
ALIS-A
a/b
Data/Control
Interface
SPI
PSB 4600
PITA
EEPROM
PCI Bus
________________________________________
Semiconductor Group
2-2
Preliminary Data Sheet 12.98
PSB 4600
Applications realized with the PITA
________________________________________
ISDN Modem using the ISAR 34 with two Interfaces
IOM-2
PEB 2081
SBCX
S-Interface
PSB 21911
IEC-Q TE
U-Interface
Microcontroller
Bus
PSB 7115
ISAR34
SPI
PSB 4600
PITA
EEPROM
PCI Bus
________________________________________
Semiconductor Group
2-3
Preliminary Data Sheet 12.98
PSB 4600
Construction of the PITA
3
Construction of the PITA
________________________________________
Overview
The PITA provides a Peripheral Component Interconnect (PCI) bus interface
which acts as a bridge between the PCI bus and the different controllers and
interfaces:
• The Parallel Interface Control supports up to three external devices.
• The Serial Interface is controlled by the internal DMA Controller; serial
communications use transmit and receive FIFOs.
• The EEPROM for configuration of the PITA and customer specific data
storage.
• The General Purpose I/O Interface.
________________________________________
Block Diagram of the PITA
PCI-Bus
PCI
Controller
DMA
Controller
TX FIFO
RX FIFO
PITA
EEPROM
Control
SPIInterface
Parallel
Interface
Control
Parallel
Microcontroller
Interface
Serial
Interface
Control
Serial
Interface
General
Purpose
Interface
________________________________________
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3-1
Preliminary Data Sheet 12.98
PSB 4600
Construction of the PITA
________________________________________
Description of the single Blocks
Name
provides
supports
PCI Bus
Control
• a 32 bit interface
at speeds up to
33 MHz
• Bus Master DMA
capability for data
passing through
the Serial
Interface
• Target capability
for data passing
through the
Parallel Interface
the Power
Management States:
default
Parallel
Interface
Control
Notes
• D0
• D1
• D3
configurable
• D2
Chips with a
SIEMENS/Intel
standard parallel
Interface, including:
• ISDN devices
• Modems DSPs
• Industrial devices
Serial
Interface
Control
Semiconductor Group
Chips with a serial
interface, including:
• Analog voice
codecs
• Analog modem
codecs
• IOM-2 devices.
3-2
Transmit and
receive data
are held in
separate 16word FIFOs.
Preliminary Data Sheet 12.98
PSB 4600
Construction of the PITA
Description of the single Blocks
Name
provides
EEPROM
Control
• additional
information, such
as
– the Subsystem
ID
supports
This is an
optional
feature that
can be used to
customize the
PITA
configuration
at start-up.
– the Subsystem
Vendor ID
– enabling of the
D2 Power
Management
state
General
Purpose
I/O
Interface
Notes
• GP outputs
• GP inputs
• GP interrupt
inputs
It can be
configured to
act as
• Input pins
• Output pins
• Interrupt
pins.
At start-up
these pins are
used for the
EEPROM
interface.
________________________________________
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3-3
Preliminary Data Sheet 12.98
PSB 4600
Construction of the PITA
________________________________________
Logical Symbol of the PITA
INT1
INT0#
RD#
WR#
PA(7:0)
VDD5
VDD3
GP3
VSS
GP2 / EEPROM SCK
FSC
PME#
RST#
INTA#
GNT#
CLK
REQ#
SERR#
PERR#
IDSEL
DEVSEL#
STOP#
TXD
IRDY#
ELD
TRDY#
RXD
FRAME#
DCL
ECS#
PAR
GP0 / EEPROM SO
AD(31:0) C/BE#(3:0)
+3.3 V
0V
SRST#
GP1 / EEPROM SI
EEPROM
Interface
+5 V
Serial
Interface
CLKRUN#
General
Purpose
Interface
PAD(7:0)
PRST
CS#(2:0)
ALE
Parallel Microcontroller Interface
PCI
Interface
________________________________________
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Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4
Communication with the PITA
________________________________________
For communication with the PITA following blocks are used:
Components
Page
PCI Configuration Space
4-2
PCI Master Target Controller
4-13
Power Management
4-13
Interrupt Control Register - Retry Counter
4-35
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Semiconductor Group
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Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.1
PCI Configuration Space
________________________________________
Overview
Overview
Page
Information about the PCI Configuration Space
4-3
Access to the PCI Configuration Space
4-6
Base Address Register
4-7
Other Registers of the PCI Configuration Space
4-11
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Semiconductor Group
4-2
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.1.1
Information about the PCI Configuration Space
________________________________________
Description
The PCI Configuration Space contains information about
• the PCI device
• the requested address space in the memory space of the PCI system.
The address space includes 64 32-bit registers where as the first 16 registers
build the configuration space header (00h-3Ch, refer to “Configuration Space
Register of the PITA” on page 10-1)
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Semiconductor Group
4-3
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
Construction of the PCI Configuration Space
31
24 23
16 15
8 7
0
Device ID
Vendor ID
00h
Status
Command
04h
Class Code
BIST
Header Type
Latency Timer
Revision ID
08h
Cach Line Size
0Ch
Base Address Register 0 (Internal Registers, ASR)
10h
Base Address Register 1 (Parallel Interface -> CS2-0)
14h
Base Address Register 2 (unused)
18h
Base Address Register 3 (unused)
1Ch
Base Address Register 4 (unused)
20h
Base Address Register 5 (unused)
24h
CardBus CIS Pointer
28h
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address
30h
Reserved
Cap_Ptr
Reserved
Max_Lat
Min_Gnt
Power Management Capabilities
Data
2Ch
34h
38h
Interrupt Pin
Interrupt Line
3Ch
Next Item Pointer
Capability ID
40h
Bridge Support
PMCSR
44h
Power Data Register 1
48h
Power Data Register 2
4Ch
Power Data Register 3
50h
Unused Configuration Space Registers
54h
CardBus CIS
58h
5Ch
Unused Configuration Space Registers
shaded fields loaded during
initialization if EEPROM is connected
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Semiconductor Group
4-4
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
Description of Register Types
Type
Description
R
• read only
• these bits are initialized by pinstrapping during PCI reset
H
• read only
• hardwired
RC
• read clear
• these bits are set by the internal logic
• these bits can be read out and reset by writing logical “1”
to them
• writing logical “0” doesn’t influence the states of these bits
RW
• read write
• these bits can be read out and written via the PCI bus
EW
• EEPROM write
• these bits can be set by an external EEPROM after a
system reset
________________________________________
Semiconductor Group
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Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.1.2
Access to the PCI Configuration Space
________________________________________
Description
The PITA supports single 32 bit data transactions for the access to the PCI
Configuration Space.
________________________________________
Special Qualities
Name
Description
Subsystem ID
• during System reset:
– as well as part of the Subsystem Vendor ID
– can be set via pinstrapping if no EEPROM is
used
• with external EEPROM the complete 16 bit
value can be loaded for the Subsystem ID
Subsystem Vendor ID
• 16 bit ID of the card manufacturer
• default value: 110Ah (Vendor ID of SIEMENS
AG)
• identifies the card of the card manufacturer
• has to be applied for at the PCI Special Interest
Group
• during system reset part of the Subsystem ID
CardBus CIS Pointer
is not supported by the PITA, although it is
implemented in the PCI Configuration Space
________________________________________
Semiconductor Group
4-6
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.1.3
Base Address Register
________________________________________
Base Address Registers 0 - 5
Base Address Register
Description
Base Address Register 0
• the lower 12 bits are connected to logical
“0”
• occupies an address space of 4K
Base Address Register 1
• the lower 12 bits are connected to logical
“0”
• allows continuous read and write
operations for access to the parallel
interface
• occupies an address space of 4K
– address space is segmented in 4x1K
address blocks
Base Address Register 2 - 5
not used
________________________________________
Structure of the Address Space of Base Address Register 1
Address Space
Access to
3FFh - 000h
device 1 on the parallel interface (CS0)
7FFh - 400h
device 2 on the parallel interface (CS1)
BFFh - 800h
device 3 on the parallel interface (CS2)
FFFh - C00h
not used
________________________________________
Semiconductor Group
4-7
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
Configuration Space Register: 04h
Bit 1
Memory_Access_Enable
Type
RW
Default Value
0b
Description
Only if this bit is set to ‘1’, the PCI interface will react on
transactions to the base address registers BAR (all Base
Address Registers are defined as memory mapped).
________________________________________
Configuration Space Register: 10h
Bit 31:12
Base Address Register 0
Type
RW
Default Value
0000h
Bit 11:00
Base Address Register 0
Type
H
Default Value
000h
Description
Bar 0 contains the base address of an address space in the
PCI main memory through which the internal registers of the
PITA can be accessed.
________________________________________
Semiconductor Group
4-8
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
Configuration Space Register: 14h
Bit 31:12
Base Address Register 1
Type
RW
Default Value
0000h
Bit 11:00
Base Address Register 0
Type
H
Default Value
000h
Description
Bar 1 contains the base address of a 4-kbyte address space
in the PCI main memory through which the internal registers
of the PITA can be accessed.
________________________________________
Configuration Space Register: 18h
Bit 31:0
Base Address Register 2
Type
H
Default Value
0000 0000h
Description
Base Address Register 2 is not supported.
________________________________________
Configuration Space Register: 1Ch
Bit 31:0
Base Address Register 3
Type
H
Default Value
0000 0000h
Description
Base Address Register 3 is not supported.
Semiconductor Group
4-9
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
Configuration Space Register: 20h
Bit 31:0
Base Address Register 4
Type
H
Default Value
0000 0000h
Description
Base Address Register 4 is not supported.
________________________________________
Configuration Space Register: 24h
Bit 31:0
Base Address Register 5
Type
H
Default Value
0000 0000h
Description
Base Address Register 5 is not supported.
________________________________________
Semiconductor Group
4-10
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.1.4
Other Registers of the PCI Configuration Space
________________________________________
Configuration Space Register: 28h
Bit 31:0
CardBus CIS Pointer
Type
H
Default Value
0000 02C0h
Description
Bit 31:28
ROM_Image_Number
Type
H
Default Value
0000b
Description
Bit 27:3
Address_Space_Offset
Type
H
Default Value
000058h
Description
Points to the first CIS register in the Configuration Space.
Bit 2:0
Address_Space_Indicator
Type
H
Default Value
000b
Description
CIS in the device specific Configuration Space.
________________________________________
Semiconductor Group
4-11
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
Note
The CardBus function is not supported in this version of the PITA.
________________________________________
Configuration Space Register: 2Ch
Bit 31:20
Subsystem ID
Type
H/EW
Default Value
000h
Bit 19:16
Subsystem ID
Type
R/EW
Default Value
pinstrap value or EEPROM value
Description
Identifies a specific board of a manufacturer on which the
PITA is used.
The 4 LSBs will be set by pinstrapping during PCI reset if no
EEPROM is used and the complete 16 bit register can be
configured by a connected EEPROM.
Bit 15:0
Subsystem Vendor ID
Type
R/EW
Default Value
pinstrap value or EEPROM value
Description
Marks of the Vendor of the board on which the PITA is used.
This register will be set by pinstrapping during PCI reset if no
EEPROM is used or configured from a connected EEPROM.
This ID is allocated by the PCI SIG.
________________________________________
Semiconductor Group
4-12
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.2
PCI Master Target Controller
________________________________________
Introduction
The interface of the PCI bus is represented by the PCI Master/Target Controller.
This Controller is part of the PITA.
The PCI Master/Target Controller supports
• several types of transactions,
• two of the six Base Address Registers.
The PCI Master Target Controller
• has a “Medium Device Select” behavior,
• truncates burst transactions at the end of the first dataphase.
________________________________________
Semiconductor Group
4-13
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.2.1
Supported PCI Commands
________________________________________
PCI Master Controller:
PCI Command
Transaction Type
Memory Read
single transfer
Memory Write
single transfer
________________________________________
PCI Target Controller:
PCI Command
Transaction Type
Memory Read
single transfer
Memory Read Multiple
single transfer, mapped on Memory Read
Memory Read Line
single transfer, mapped on Memory Read
Memory Write
single transfer
Memory Write and
Invalidate
single transfer, mapped on Memory Write
Configuration Read
single transfer
Configuration Write
single transfer
________________________________________
Semiconductor Group
4-14
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
Overview
Overview
Page
Transaction Type Single Data Read
4-16
Transaction Type Single Data Write
4-17
Transaction Type Burst Read
4-18
Transaction Type Burst Write
4-20
Transaction Type Fast Back to Back
4-22
________________________________________
Note
The following timing diagrams are meant as an example and show the
transactions to and from the PCI configuration space.
________________________________________
Semiconductor Group
4-15
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.2.2
Transaction Type Single Data Read
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
IDSEL
FRAME
IRDY
TRDY
DEVSEL
AD31-0
ADR
C/BE3-0
1010b
DATA
BE
STOP
________________________________________
Semiconductor Group
4-16
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.2.3
Transaction Type Single Data Write
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
IDSEL
FRAME
IRDY
TRDY
DEVSEL
AD31-0
ADR
DATA
C/BE3-0
1011b
BE
STOP
________________________________________
Semiconductor Group
4-17
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.2.4
Transaction Type Burst Read
________________________________________
Description
• Asserting IRDY and STOP at the first dataphase leads to the disconnection
(Disconnect-B) of the burst read transaction by the PITA.
• STOP is asserted until FRAME is deasserted.
• Deassertion of FRAME means that STOP and DEVSEL together are
deasserted.
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
IDSEL
FRAME
IRDY
TRDY
DEVSEL
AD31-0
ADR
C/BE3-0
1010b
DATA
BE
STOP
________________________________________
Semiconductor Group
4-18
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
Configuration Space Register: 04h
Bit 26:25
DEVSEL_Timing
Type
H
Default Value
01b
Description
‘01’ = medium timing, i.e. the DEVSEL signal will be
asserted from the PCI interface with the second positive PCI
clock edge after FRAME was asserted on the PCI bus by a
master.
________________________________________
Semiconductor Group
4-19
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.2.5
Transaction Type Burst Write
________________________________________
Description
• Asserting IRDY and STOP at the first dataphase leads to the disconnection
(Disconnect-B) of the burst write transaction by the PITA.
• STOP is asserted until FRAME is deasserted.
• Deassertion of FRAME means that STOP and DEVSEL together are
deasserted.
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
IDSEL
FRAME
IRDY
TRDY
DEVSEL
AD31-0
ADR
DATA1
DATA2
C/BE3-0
1010b
BE1
BE2
STOP
________________________________________
Semiconductor Group
4-20
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
Configuration Space Register: 04h
Bit 26:25
DEVSEL_Timing
Type
H
Default Value
01b
Description
‘01’ = medium timing, i.e. the DEVSEL signal will be
asserted from the PCI interface with the second positive PCI
clock edge after FRAME was asserted on the PCI bus by a
master.
________________________________________
Semiconductor Group
4-21
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.2.6
Transaction Type Fast Back to Back
________________________________________
Description
With the fast back to back transaction a PCI Master Controller can perform
• several write transactions
• a read transaction as last transaction
without setting the PCI bus to IDLE state in between or releasing the bus to
another master.
At the end of a transaction:
• The Master asserts the FRAME signal and at the same time the TRDY signal
is deasserted.
The transaction is answered with a RETRY signal by the PITA
• if the parallel interface is included in the fast back to back transaction
• and the parallel interface is still busy.
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
IDSEL
FRAME
IRDY
TRDY
DEVSEL
AD31-0
ADR
DATA1
ADR2
DATA2
C/BE3-0
1011b
BE1
1011b
BE2
STOP
________________________________________
Semiconductor Group
4-22
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
Configuration Space Register: 04h
Bit 23
Fast_Back_To_Back_Capability
Type
H
Default Value
1b
Description
The PITA supports fast back-to-back.
Bit 9
Fast_Back_To_Back_Enable
Type
H
Default Value
0b
Description
The PITA itself generates no Fast back-to-back
transactions.
________________________________________
Semiconductor Group
4-23
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.3
Power Management
________________________________________
Overview
Overview
Page
Information about the Power Management
4-25
Configuration Space Registers of the Power Management
4-28
________________________________________
Semiconductor Group
4-24
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.3.1
Information about the Power Management States
________________________________________
Description
The PITA supports the Power Management states D0, D1, D2, D3, D3hot and
D3cold.
________________________________________
D0
• The D0 state represents the default state of the internal logic after a system
reset.
• After a system reset the PCI interface is in the D0 state and has to be initialized
before being used.
• The PITA responds only to configuration accesses while not completely
initialized.
• The PCI Master Target controller is disabled while not completely initialized.
________________________________________
D1
• D1 is a light sleep rate.
• The PITA supports the D1 state by default if this state is not disabled by an
EEPROM configuration.
• The PITA PCI function can be set to the D1 state by software.
• The PITA PCI function only responds to PCI configuration accesses.
• All accesses to the memory spaces defined by the Base Address Registers are
disabled.
• The only PCI bus operation the PCI interface is allowed to initiate is the
assertion of the PME signal.
________________________________________
D2
• By default the support of the D2 state is disabled in the PITA.
• D2 can be enabled by configuration by an EEPROM.
• Same state behavior as described for the state D1.
________________________________________
Semiconductor Group
4-25
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
D3
• Same state behavior as described for the state D1.
• The only legal state transitions from D3 to D0 are:
– by software reset; the software has to perform a fully reinitialization of the
PCI function including the PCI Configuration Space.
– by system reset
________________________________________
D3hot
• Power and clock are still available to the PITA.
• Power and clock can be returned to D0 by software.
• State behavior as described for the state D3.
________________________________________
D3cold (POWER OFF)
•
•
•
•
D3cold is a “power off” state.
The PCI bus power Vcc has been disconnected.
If Vcc is removed from the device.
PME generation is not possible in that state.
________________________________________
Semiconductor Group
4-26
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
Electrical Characteristics
Parameter
Symbol
Limit
Values
min
Power supply
current
ICC
Unit
Test Condition
0
mA
D3cold state - power
off
(power is removed)
19
mA
D3hot state - power
down
19
mA
D2 state - deep sleep
mode
19
mA
D1 state - light sleep
mode
19
mA
D0 state - operational
mode
max
________________________________________
Semiconductor Group
4-27
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.3.2
Configuration Space Registers of the Power Management
________________________________________
Configuration Space Register: 34h
Bit 31:8
Reserved
Type
H
Default Value
000000h
Description
Reserved
Bit 7:0
Cap_Ptr
Type
H
Default Value
40h
Description
The Capabilities Pointer points to the first Power
Management Register in the PCI Configuration Space.
________________________________________
Configuration Space Register: 40h
Bit 31:0
Power Management Capabilities (PMC)
Bit 31
PME_Support_D3cold
Type
H
Default Value
0b
Description
Bit 31=PME_Support_D3cold=’0’; not supported
Semiconductor Group
4-28
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
Configuration Space Register: 40h (cont’d)
Bit 30
PME_Support_D3hot
Type
H
Default Value
0b
Description
Bit 30=PME_Support_D3hot=’0’; PME supports D3hot
Bit 29
PME_Support_D2
Type
H or EW
Default Value
0b
Description
Bit 29=PME_Support_D2=’0’; not supported; can be
enabled by EEPROM
Bit 28
PME_Support_D1
Type
H or EW
Default Value
1b
Description
Bit 28=PME_Support_D1=’0’; not supported; can be
enabled by EEPROM
Bit 27
PME_Support_D0
Type
H
Default Value
0b
Description
Bit 27=PME_Support_D0=’0’; not supported
Semiconductor Group
4-29
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
Configuration Space Register: 40h (cont’d)
Bit 26
D2_Support
Type
H or EW
Default Value
0b
Description
• Not supported from the PITA by default.
• Support can be enabled by EEPROM. Board with the
PITA must be able to assert the PME signal.
• D2 state is fully enabled when
– assertion of PME_Clock
– assertion of the PME_Support_2 bit
is required.
Bit 25
D1_Support
Type
H or EW
Default Value
1b
Description
• The PITA supports the D1 Power state by default.
• Can be disabled by EEPROM.
Bit 24:22
Reserved
Type
H
Default Value
000b
Description
Reserved
Bit 21
DSI (Device Specific Initialization)
Type
H
Default Value
1b
Description
Indicates that the PITA requires a specific initialization
sequence following the transition to D0 state (uninitialized).
Semiconductor Group
4-30
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
Configuration Space Register: 40h (cont’d)
Bit 20
Reserved
Type
H
Default Value
0b
Description
Reserved
Bit 19
PME_Clock
Type
H or EW
Default Value
1b
Description
The PME_Clock bit is by default =’1’, because only PME
assertion is supported if the PCI clock is present. If also PME
assertion out of D2 (no clock running) is supported, the
PME_Clock bit must be set to ’0’ by EEPROM.
Bit 18:16
Version
Type
H
Default Value
001b
Description
The value 01b indicates that the device complies with the
Revision 1.0 of the PCI Power Management Interface
Specification.
Bit 15:8
Next_Item_Ptr
Type
H
Default Value
00h
Description
No next item
Semiconductor Group
4-31
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
Configuration Space Register: 40h (cont’d)
Bit 7:0
Capabiltity_ID
Type
H
Default Value
01h
Description
’Indicates that the data structure is currently pointed to the
PCI Power Management data structure.
________________________________________
Configuration Space Register: 44h
Bit 31:24
DATA_Register
Type
H
Default Value
00h
Description
Depending on the Data_Select field (Bit 12:9) parts of the
Power Data register (48h) are mapped to this register.
Bit 23:16
PMCSR_BSE (Bride support extension)
Type
H
Default Value
00h
Description
not used
Bit 15
PME_Status
Type
RC
Default Value
0b
Description
This bit is set when the PCI interface asserts the PME signal
independent of the state of the PME_EN bit.
Semiconductor Group
4-32
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
Configuration Space Register: 44h (cont’d)
Bit 15:8
Power Management Control/Status Register
Type
H
Default Value
00h
Bit 14:13
Data_Scale
Type
H
Default Value
00b
Description
Depending on the Data_Select field (Bit 12:9) parts of the
Power_Data register are mapped to this register.
Bit 12:9
Data_Select
Type
RW
Default Value
0h
Description
• Values from 0 - 7 are supported: Parts of the Power_Data
register are mapped to the DATA register and the
Data_Scale field.
• Values from 8 - 15: Zero values are mapped to the DATA
register and the Data_Select field.
Bit 8
PME_En
Type
RW
Default Value
0b
Description
Enables ar disables the PITA to assert the PME signal.
PME_En=’0’: Assertion of the PME signal is disabled.
PME_En=’1’: The device is enabled to assert the PME
signal.
Semiconductor Group
4-33
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
Configuration Space Register: 44h (cont’d)
Bit 8
PME_En
Type
RW
Default Value
000000b
Description
Reserved
Bit 7:2
Reserved
Type
H
Default Value
00h
Description
Reserved
Bit 1:0
Power_State
Type
RW
Default Value
00b
Description
Power_State=’00’: D0 state (supported by the PITA)
Power_State=’01’: D1 state (supported by the PITA)
Power_State=’10’: D2 state (not supported by default)
Power_State=’11’: D3 state (supported by the PITA).
________________________________________
Semiconductor Group
4-34
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
4.4
Interrupt Control Register - Retry Counter
________________________________________
Description
• Part of the PCI Master Target Controller
• Functionality:
1. Disconnection of the PCI Master transaction with Retry by the addressed PCI
Slave.
2. Decrement of the counter.
3. The Retry_Counter_Int bit is set.
4. An interrupt will be generated if the Retry_Counter_Enable bit is set.
5. The PCI Master starts the transaction again.
________________________________________
Internal Register: 00h
Bit 27
RETRY_Counter_Down_Int_En
Type
RW
Default Value
0b
Description
Enable for the Retry_Counter_Down interrupt bit
Bit 11
Retry_Counter_Int
Type
RC
Default Value
0b
Description
If a PCI Master initiated transaction is retried from a PCI
Slave with the number of retries defined in the
Retry_Counter register, this interrupt bit is set by the PCI
interface.
________________________________________
Semiconductor Group
4-35
Preliminary Data Sheet 12.98
PSB 4600
Communication with the PITA
________________________________________
Internal Register:1Ch
Bit 23:16
Retry Count Register
Type
RW
Default Value
00h
Description
• Part of the PCI Master Target Controller
• Functionality:
1. Disconnection of the PCI Master transaction with Retry by
the addressed PCI Slave.
2. Decrement of the counter.
3. The Retry_Counter_Int bit is set.
4. If the Retry_Counter_Enable an interrupt will be
generated.
5. The PCI Master starts the transaction again.
________________________________________
Semiconductor Group
4-36
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5
Communication with external Components
________________________________________
Interfaces
Interfaces
Page
Serial DMA Interface
5-2
Parallel Interface
5-47
General Purpose I/O Interface
5-65
SPI EEPROM Interface
5-84
________________________________________
Semiconductor Group
5-1
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1
Serial DMA Interface
________________________________________
Introduction
The serial DMA interface is used in different modes to transmit and receive 16 bit/
32 bit data frames. These data frames have different structures:
• Data/Voice and Command
• Data/Voice and Command for two codecs
• Different time slots on IOM-2.
________________________________________
Usage of the Serial DMA Interface
The serial DMA interface is clocked by default with the internally generated clock
(PCI clock divided by 40).
The Ser_Clock_Set bit must be set in the Serial Clock Select register to ’1’ when
the interface works in ALIS V3.X or IOM-2 mode
• after a system reset
• before starting the DMA controller.
The reset of this bit can result in an unknown behavior of the FIFOs and the serial
controller.
The serial DMA interface is fully controlled by the DMA controller.
________________________________________
Semiconductor Group
5-2
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Overview
Overview
Page
DMA Controller
5-4
IOM-2 Mode 1
5-15
IOM-2 Mode 2
5-18
IOM-2 Mode 3
5-21
IOM-2 Modes - Supplementary Description
5-24
Single Modem Mode V2.1
5-29
Single Modem Mode ALIS V3.X
5-33
Dual Modem/Modem+Voice Mode
5-42
Loop Back Mode
5-45
________________________________________
Semiconductor Group
5-3
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.1
DMA Controller
________________________________________
Overview
Overview
Page
Information about the DMA Controller
5-5
Interrupts
5-9
Internal Registers of the DMA Controller
5-10
________________________________________
Semiconductor Group
5-4
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.1.1
Information about the DMA Controller
________________________________________
Description
For the control of the DMA Controller, three register are implemented in the
internal registers:
• The Circular Buffer Start Address is a 4-kbyte aligned PCI address which
points to a 4-kbyte circular buffer in the PCI main memory. All DMA read/write
transactions between host and PITA will be processed via this 4-kbyte address
space.
• The DMA Control register includes the 6-bit parameter DMA Select which is
used to define the mode for the next DMA transfer. With the DMA_Start bit the
DMA transfer can be started and stopped.
• The contents of the DMA Write Count Register is interpreted as a threshold for
the write transfers from the DMA controller.
________________________________________
Function of the DMA Controller
Phase
Function
1
DMA_Start bit is set in the DMA Control Register and a DMA
transfer is started as defined in the DMA Select Register.
2
The DMA controller loads the Circular Buffer Start Address to its
Actual Circular Buffer Pointer.
3
The DMA controller fills the TX FIFO by reading 15 times through
the PCI interface (PCI master mode) from the circular buffer.
4
The DMA controller signals the end of the initial sequence.
5
The DMA controller increments the Actual Circular Buffer Pointer by
4 each read transfer.
6
The DMA controller loads the contents of the 12 bit DMA Write
Count Register to its internal 12 bit DMA write counter.
7
After the first 15 read transfers in the beginning of the 16th read
transfer the DMA controller starts the normal DMA algorithm.
________________________________________
Semiconductor Group
5-5
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Function of the DMA Algorithm
Phase
Function
1
The DMA controller reads the 16th data word from the current
address in the circular buffer (Actual Circular Buffer Pointer) to the
internal TX FIFO.
2
The DMA controller writes the first received 16-bit data word from
the RX FIFO to the same address in the circular buffer.
3
The DMA controller increments the Actual Buffer Pointer by 4.
4
The DMA controller reads the 17th data word from the current
address in the circular buffer (Actual Circular Buffer Pointer) to the
internal TX FIFO.
5
The DMA controller writes the second received 16-bit data word
from the RX FIFO to the same address in the circular buffer.
6
The DMA controller increments the Actual Buffer Pointer by 4.
7
and so on
________________________________________
DMA Write Counter
After each write transaction from the RX FIFO to the buffer the internal DMA write
counter is incremented by 1. If this counter reaches ’0’ an interrupt is generated
and the counter is loaded again with the contents of the DMA Write Counter
Register.
The internal DMA write counter is decremented every two write transactions as
long as two 16 bit values per FSC frame are transferred in the following modes:
•
•
•
•
32 bit frame mode
dual modem mode
modem+voice mode
IOM-2 mode 2 and 3.
________________________________________
Semiconductor Group
5-6
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
DMA_Start bit
• The reset of the DMA_Start bit stops the DMA transfer immediately.
• The assertion of the DMA_Start bit resets the TX and RX FIFO’s.
This means that all FIFO data is lost when the DMA transfer is stopped.
________________________________________
Data in the Circular Buffer
Since no data is written from the RX FIFO to the circular buffer for the first 15
addresses, the first interrupt after the DMA_Start assertion means that the
received data is available in the circular buffer on address
• 003Ch to 003Ch + [DMA Write Count]: 16 bit frame modes
• 003Ch to 0003Ch + 2 x [DMA Write Count]: 32 bit frame modes.
During normal data transfer every interrupt means that received data is available
in the circular buffer on address
• [end address from last interrupt] to [end address from last interrupt] + [DMA
Write Count]: 16 bit frame modes
• [end address from last interrupt] to [end address from last interrupt] + 2 x [DMA
Write Count]: 32 bit frame modes
________________________________________
Semiconductor Group
5-7
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Example for DMA controlled Data Transfer via Circular Buffer
The status of the DMA controller:
16 bit frame access mode (ALIS V2.1 mode/IOM-2 mode 1) when three data
frames are already written to the TX line.
Circular Buffer
Memory
31
0000h
0004h
0008h
0038h
003Ch
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
16 15
Serial Control
0
TX data 1
TX data 2
TX data 3
TX data 4
TX data 5
TX data 6
TX data 7
TX data 8
TX data 9
TX data 10
TX data 11
TX data 12
TX data 13
TX data 14
TX data 15
RX data 1
RX data 2
RX data 3
RX data 4
TX data 20
TX data 21
TX data 22
TX data 23
TX data 4
TX data 5
TX data 6
TX data 7
TX data 8
TX data 9
TX data 10
TX data 11
TX data 12
TX data 13
TX data 14
TX data 15
TX data 16
TX data 17
TX data 18
TX data 19
TX FIFO
Actual_Circular_Buffer_Pointer
RX data 20
RX data 19
RX data 18
RX data 17
RX data 16
RX data 15
RX data 14
RX data 13
RX data 12
RX data 11
RX data 10
RX data 9
RX data 8
RX data 7
RX data 6
RX data 5
RX FIFO
DMA
Controller
PITA
________________________________________
Semiconductor Group
5-8
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.1.2
Interrupts
________________________________________
FIFO Overflow/Empty Interrupt
• This interrupt bit is set by the serial controller during the active DMA if:
– The selected serial protocol could not be generated because there was no
data available in the TX FIFO.
– A received data frame was lost because of FIFO Overflow.
• This bit is not set during the DMA start sequence by the serial controller.
________________________________________
Write Counter Interrupt
An interrupt by the write counter must be processed by the host in the following
way:
• read out the new received data in the circular buffer
• fill in new transmit data in the circular buffer
• reset the DMA_Write_Counter bit in the Interrupt Control Register.
________________________________________
Note
This has to be done before the DMA Write Counter expires once again (e.g.
interrupt
latency),
which
would
cause
the
generation
of
a
DMA_Write_Counter_Overflow.
________________________________________
Semiconductor Group
5-9
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.1.3
Internal Registers of the DMA Controller
________________________________________
Internal Registers: 00h
Bit 26
FIFO_Overflow_Empty_Int_En
Type
RW
Default Value
0b
Description
Enable for the FIFO_Overflow_Empty interrupt bit
Bit 25
DMA_Write_Counter_Overflow_Int_En
Type
RW
Default Value
0b
Description
Enable for the DMA_Write_Counter_Overflow interrupt bit.
Bit 24
DMA_Write_Counter_Int_En
Type
RW
Default Value
0b
Description
Enable for the DMA_Write_Counter interrupt bit.
Bit 10
FIFO_Overflow_Empty_Int
Type
RC
Default Value
0b
Description
During a DMA transfer the serial controller was unable to
write received data to the RX FIFO because is was already
full or the serial controller was unable to send data after the
rising FSC edge because of empty TX FIFO.
Semiconductor Group
5-10
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Registers: 00h (cont’d)
Bit 9
DMA_Write_Counter_Overflow_Int
Type
RC
Default Value
0b
Description
This bit is set if the internal DMA write counter is counted
down while the DMA_Write_Counter_Int bit is still active.
This means that the interrupt generated by the
DMA_Write_Counter_Int bit is not yet processed.
Bit 8
DMA_Write_Counter_Int
Type
RC
Default Value
0b
Description
This bit is set if the number of data, defined in the DMA Write
Count Register is written through the PCI interface. In the
32-bit modes (dual modem, modem+voice, IOM-2 mode 2,
IOM-2 mode 3) this bit is set if the number of data pairs
defined in the DMA Write Count Register is transferred
through the PCI interface.
________________________________________
Internal Registers: 04h
Bit 31:0
DMA Control Register
Bit 31:9
Reserved
Type
H
Default Value
0000000h
Description
Reserved
Semiconductor Group
5-11
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Registers: 04h (cont’d)
Bit 8
DMA_Start
Type
RW
Default Value
0b
Description
By asserting this bit a DMA transfer between the circular
buffer and the serial DMA interface using internal RX/TX
FIFOs is started. This bit is reset by the host if the DMA
transfer is to be finished.
Bit 7:6
Reserved
Type
H
Default Value
00b
Description
Reserved
Bit 5:0
DMA Select
Type
RW
Default Value
000000b
Description
Used to define the mode for the next DMA transfer:
– Mode 1 (’000001’): Single Modem Mode V2.1
– Mode 2 (’000010’): Single Modem Mode V3.X
– Mode 3 (’000100’): Single Dual Modem/Modem+Voice
Mode V3.X
– Mode 4 (’001000’): IOM-2 Mode 1
– Mode 5 (’010000’): IOM-2 Mode 2
– Mode 6 (’100000’): IOM-2 Mode 3
With the DMA_Start bit the DMA transfer can be started or
stopped.
________________________________________
Semiconductor Group
5-12
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Internal Registers: 08h
Bit 31:12
Circular Buffer Start Address
Type
RW
Default Value
000000h
Bit 11:0
Circular Buffer Start Address
Type
H
Default Value
000h
Description
• 4-kbyte aligned PCI address which points to a 4-kbyte
circular buffer in the PCI main memory.
• All DMA read/write transactions between the host and the
PITA are processed via this 4-kbyte address space.
________________________________________
Internal Register: 0Ch
Bit 31:02
Actual Circular Buffer Pointer
Type
R
Default Value
0000 0000h
Bit 1:0
Actual Circular Buffer Pointer
Type
H
Default Value
00b
Description
By reading this register the software has access to the PCI
address in the DMA circular buffer address pointer.
The bits 31-12 are equal the contents of the Circular Buffer
Start Address Register. The bits 11-0 represent the actual
dword address in the circular buffer.
________________________________________
Semiconductor Group
5-13
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Internal Register: 1Ch
Bit 11:0
DMA Write Count Register
Type
RW
Default Value
000h
Description
________________________________________
Semiconductor Group
5-14
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.2
IOM-2 Mode 1
________________________________________
Transmission and Reception of Data in the Circular Buffer
Circular Buffer
Memory
31
16 15
0
31
16 15
Don´t care
0000h
0004h
0008h
0038h
003Ch
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
8 7
B1
0
B2
TX data 1
TX data 2
TX data 3
TX data 4
TX data 5
TX data 6
TX data 7
TX data 8
TX data 9
TX data 10
TX data 11
TX data 12
TX data 13
TX data 14
TX data 15
RX data 1
RX data 2
RX data 3
RX data 4
TX data 20
TX data 21
TX data 22
TX data 23
________________________________________
Data in Circular Buffer and on Serial DMA Interface
Direction
Data in Circular Buffer
Data on Serial DMA
Interface
Transmit
Bits from circular buffer:
[31:16] = don’t care
[15:8] = B1 [7:0]
[7:0]
= B2 [7:0]
Write to serial DMA interface:
Semiconductor Group
5-15
B1 [7:0]
B2 [7:0]
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Data in Circular Buffer and on Serial DMA Interface (cont’d)
Direction
Data in Circular Buffer
Data on Serial DMA
Interface
Receive
Bits to circular buffer:
[31:16] = don’t care
[15:8] = B1 [7:0]
[7:0]
= B2 [7:0]
Read from serial DMA
interface:
B1 [7:0]
B2 [7:0]
________________________________________
Timing Diagram
125 us
FSC (i)
DCL (i)
TXD (o)
8 bit B1 channel DU
8 bit B2 channel DU
RXD (i)
8 bit B1 channel DD
8 bit B2 channel DD
16 bit B1, B2 frame, double clock
________________________________________
Internal Registers: 04h
Bit 5:0
DMA Select
Type
RW
Default Value
000000b
Description
The DMA Control Register includes the 6 bit parameter DMA
Select.
Used to define the mode for the next DMA transfer:
Mode 4 (’001000’): IOM-2 Mode 1
With the DMA_Start bit the DMA transfer can be started or
stopped.
________________________________________
Semiconductor Group
5-16
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Internal Register: 20h
Bit 1
DCL_Out_En
Type
RW
Default Value
0b
Description
Bit 1=’0’: The DCL signal is configured as input, i.e. not
driven by the PITA.
Bit 0
Serial_Clock_Select
Type
RW
Default Value
0b
Description
Bit 0=’1’: The serial controller is driven with the external DCL
input clock.
________________________________________
Semiconductor Group
5-17
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.3
IOM-2 Mode 2
________________________________________
Transmission and Reception of Data in the Circular Buffer
Circular Buffer
Memory
16 15
31
0
31
16 15
Don´t care
0000h
0004h
0008h
0038h
003Ch
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
TX data 1
TX data 2
TX data 3
TX data 4
TX data 5
TX data 6
TX data 7
TX data 8
TX data 9
TX data 10
TX data 11
TX data 12
TX data 13
TX data 14
TX data 15
RX data 1
RX data 2
RX data 3
RX data 4
TX data 20
TX data 21
TX data 22
TX data 23
31
8 7
B1
16 15
Don´t care
0
B2
8 7
Monitor 0
0
D, C/I, MR, MX
________________________________________
Data in Circular Buffer and on Serial DMA Interface
Direction
Buffer
Offset
Data in Circular Buffer
Data on Serial DMA
Interface
Transmit
0, 2, 4,
...
Bits from circular buffer:
[31:16] = don’t care
[15:8] = B1 [7:0]
[7:0] = B2 [7:0]
Write to serial DMA
interface:
B1 [7:0]
B2 [7:0]
Semiconductor Group
5-18
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Data in Circular Buffer and on Serial DMA Interface (cont’d)
Direction
Buffer
Offset
Data in Circular Buffer
Data on Serial DMA
Interface
Transmit
1, 3, 5,
...
Bits from circular buffer:
[31:16] = don’t care
[15:8] = Monitor 0 [7:0]
[7:0] =
D,C/I0,MR,MX [7:0]
Write to serial DMA
interface:
Monitor 0 [7:0]
D,C/I0,MR,MX [7:0]
Receive
0, 2, 4,
...
Bits to circular buffer:
[31:16] = don’t care
[15:8] = B1 [7:0]
[7:0] = B2 [7:0]
Read from serial DMA
interface:
B1 [7:0]
B2 [7:0]
1, 3, 5,
...
Bits to circular buffer:
[31:16] = don’t care
[15:8] = Monitor 0 [7:0]
[7:0] =
D,C/I0,MR,MX [7:0]
Read from serial DMA
interface:
Monitor 0 [7:0]
D,C/I0,MR,MX [7:0]
________________________________________
Timing Diagram
125 us
FSC (i)
DCL (i)
TXD (o)
8 bit B1 channel DU
8 bit B2 channel DU
8 bit Monitor 0 channel DU
2 bit D
4 bit C/I 0
MR MX
RXD (i)
8 bit B1 channel DD
8 bit B2 channel DD
8 bit Monitor 0 channel DD
2 bit D
4 bit C/I 0
MR MX
16 bit B1, B2 frame, double clock
16 bit MON0, D, C/I0, MR, MX frame
________________________________________
Semiconductor Group
5-19
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Internal Registers: 04h
Bit 5:0
DMA Select
Type
RW
Default Value
000000b
Description
The DMA Control Register includes the 6 bit parameter DMA
Select.
Used to define the mode for the next DMA transfer:
Mode 5 (’010000’): IOM-2 Mode 2
With the DMA_Start bit the DMA transfer can be started or
stopped.
________________________________________
Internal Register: 20h
Bit 1
DCL_Out_En
Type
RW
Default Value
0b
Description
Bit 1=’0’: The DCL signal is configured as input, i.e. not
driven by the PITA.
Bit 0
Serial_Clock_Select
Type
RW
Default Value
0b
Description
Bit 0=’1’: The serial controller is driven with the external DCL
input clock.
________________________________________
Semiconductor Group
5-20
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.4
IOM-2 Mode 3
________________________________________
Transmission and Reception of Data in the Circular Buffer
Circular Buffer
Memory
16 15
31
0
31
16 15
Don´t care
0000h
0004h
0008h
0038h
003Ch
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
don't care
TX data 1
TX data 2
TX data 3
TX data 4
TX data 5
TX data 6
TX data 7
TX data 8
TX data 9
TX data 10
TX data 11
TX data 12
TX data 13
TX data 14
TX data 15
RX data 1
RX data 2
RX data 3
RX data 4
TX data 20
TX data 21
TX data 22
TX data 23
31
8 7
B1
16 15
Don´t care
0
B2
8 7
IC1
0
IC2
________________________________________
Data in Circular Buffer and on Serial DMA Interface
Direction
Buffer
Offset
Data in Circular Buffer
Data on Serial DMA
Interface
Transmit
0, 2, 4,
...
Bits from circular buffer:
[31:16] = don’t care
[15:8]
= B1 [7:0]
[7:0]
= B2 [7:0]
Bits to serial DMA
interface:
B1 [7:0]
B2 [7:0]
Semiconductor Group
5-21
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Data in Circular Buffer and on Serial DMA Interface (cont’d)
Direction
Buffer
Offset
Data in Circular Buffer
Data on Serial DMA
Interface
Transmit
1, 3, 5,
...
Bits from circular buffer:
[31:16] = don’t care
[15:8]
= IC1 [7:0]
[7:0]
= IC2 [7:0]
Write to serial DMA
interface:
IC1 [7:0]
IC2 [7:0]
Receive
0, 2, 4,
...
Bits to circular buffer:
[31:16] = don’t care
[15:8]
= B1 [7:0]
[7:0]
= B2 [7:0]
Read from serial DMA
interface:
B1 [7:0]
B2 [7:0]
1, 3, 5,
...
Write to circular buffer:
[31:16] = don’t care
[15:8]
= IC1 [7:0]
[7:0]
= IC2 [7:0]
Read from serial DMA
interface:
IC1 [7:0]
IC2 [7:0]
________________________________________
Timing Diagram
125 us
FSC (i)
DCL (i)
TXD (o)
8 bit B1 channel DU
8 bit B2 channel DU
8 bit IC1 channel DU
8 bit IC2 channel DU
RXD (i)
8 bit B1 channel DD
8 bit B2 channel DD
8 bit IC1 channel DD
8 bit IC2 channel DD
16 bit B1, B2 frame, double clock
16 bit IC1, IC2 frame
________________________________________
Semiconductor Group
5-22
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Internal Registers: 04h
Bit 5:0
DMA Select
Type
RW
Default Value
000000b
Description
The DMA Control Register includes the 6 bit parameter DMA
Select.
Used to define the mode for the next DMA transfer:
Mode 6 (’100000’): IOM-2 Mode 3
With the DMA_Start bit the DMA transfer can be started or
stopped.
________________________________________
Internal Register: 20h
Bit 1
DCL_Out_En
Type
RW
Default Value
0b
Description
Bit 1=’0’: The DCL signal is configured as input, i.e. not
driven by the PITA.
Bit 0
Serial_Clock_Select
Type
RW
Default Value
0b
Description
Bit 0=’1’: The serial controller is driven with the external DCL
input clock.
________________________________________
Semiconductor Group
5-23
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.5
IOM-2 Modes - Supplementary Description
________________________________________
Selection of IOM-2 Time Slots
The MISC register contains four bits. They are used for masking the time slot on
IOM-2.
If Bx_MSK (x := [1,4]) is set:
•
•
•
•
The corresponding value from the TX FIFO is not written to the DU line.
FFh is written to this time slot.
In IOM-2 mode 1 the bits B3_MSK and B4_MSK have no effect.
Data is always transferred from the IOM-2 time slot to the RX-FIFO.
________________________________________
Timing Diagram for all IOM-2 Modes
tFSW
FSC (i)
tFSS
tFSH
tFSS
tFSH
DCL (i)
t:+
RXD (i)
tIIS
t:/
tIIH
tCYC
tIOD
tIOD
TXD (o)
________________________________________
Semiconductor Group
5-24
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Abbreviations for the Timing Diagram
Parameter
Symbol
Limit Values
min.
Unit
max.
FSC pulse width
tFSW
40
ns
FSC setup time
tFSS
40
ns
FSC hold time
tFSH
40
ns
DCL cycle time
tCYC
244
ns
DCL HIGH time
tWH
100
ns
DCL LOW time
tWL
100
ns
IOM output data
delay
tIOD
IOM input data
setup
tIIS
20
ns
IOM input data hold
tIIH
20
ns
100
ns
________________________________________
Figure of the MISC Register B1 - B4 Mask Bits
MISC
Register:
B1_MSK
B2_MSK
B3_MSK
B4_MSK
IOM-2
Mode 1
B1
B2
IOM-2
Mode 2
B1
B2
Monitor 0
D,C/I0,MR,MX
IOM-2
Mode 3
B1
B2
IC1
IC2
________________________________________
Semiconductor Group
5-25
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Masking of IOM-2 Time slots (Example for IOM-2 Mode 2)
IOM-2 DU line
TXD (0)
B1
B2
B1_MSK
’FFh’
D,C/I0,MR,MX
Monitor 0
B3_MSK
B4_MSK
’FFh’
’FFh’
B2_MSK
’FFh’
RX FIFO
MON0
D,C/I0,
MR,MX
MON0
D,C/I0,
MR,MX
B1
B2
B1
B2
TX FIFO
IOM-2 DD line
RXD (i)
B1
B2
Monitor 0
D,C/I0,MR,MX
Circular Buffer
Memory
Data 3
Next IOM-2 frame
Data 3
Data 2
Data 2
Don’t care
Monitor 0
D,C/I0,MR,MX
Don’t care
B1
B2
Data 1
Data 1
Previous IOM-2 frame
________________________________________
Semiconductor Group
5-26
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Internal Register: 1Ch
Bit 31:0
MISC (Miscellaneous Register)
Bit 31
IOM_B1_masking
Type
RW
Default Value
0b
Description
Bit 31=’0’: Byte B1 is generated out of the circular buffer.
Bit 31=’1’: FFh is transmitted on the B1 time slot.
Bit 30
IOM_B3_masking
Type
RW
Default Value
0b
Description
Bit 30=’0’: Byte B1 is generated out of the circular buffer.
Bit 30=’1’: FFh is transmitted on the B2 time slot.
Bit 29
IOM_Monitor_0 / IC1_masking
Type
RW
Default Value
0b
Description
Bit 29=’0’: Byte Monitor 0 or IC1 is generated out of the
circular buffer.
Bit 29=’1’: FFh is transmitted on the Monitor/IC1 time slot.
Monitor is used in IOM-2 mode 2.
IC1 is used in IOM-2 mode 3.
Semiconductor Group
5-27
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Register: 1Ch (cont’d)
Bit 28
IOM_Supl_masking / IC2_masking
Type
RW
Default Value
0b
Description
Address:=’0’: Byte D, C/I0, MR, MX or IC2 is generated out
of the circular buffer.
Address:=’1’: FFh is transmitted on the D, C/I0, MR, MX or
IC2 time slot.
D, C/I0, MR, MX: Used in IOM-2 mode 2.
IC2: Used in IOM-2 mode 3
________________________________________
Semiconductor Group
5-28
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.6
Single Modem Mode V2.1
________________________________________
Data in Circular Buffer and on Serial DMA Interface
Direction
Data in Circular Buffer
Data on Serial DMA
Interface
Transmit
Bits from circular buffer:
[31:16] = don’t care
[15:0] = data frame [15:0]
Write to serial DMA
interface:
data frame [15:0]
Receive
Bits to circular buffer:
[31:16] = don’t care
[15:0] = data frame [15:0]
Read from serial DMA
interface:
data frame [15:0]
________________________________________
Timing diagrams
125 us
FSC (i)
DCL (o)
TXD (o)
16 bit data
RXD (i)
16 bit data
16 bit data frame
tFSW
FSC (i)
tDCI
tDCD
DCL (o)
tWH
RXD (i)
tWL
tISU tIHO
tCYC
tOD
high-Z
TXD (o)
________________________________________
Semiconductor Group
5-29
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Abbreviations for the Timing Diagram
Parameter
Symbol
FSC pulse width
tFSW
DCL delay
tDCD
DCL idle time
tDCI
DCL cycle time
tCYC
DCL HIGH time
DCL LOW time
PCI
Clock
Cycles
16
Limit Values
min.
typ.
Unit
max.
40
ns
480
ns
105
µs
40
1200
ns
tWH
20
600
ns
tWL
20
600
ns
DCL duty cycle
45
50
55
%
Input data setup
tISU
10
ns
Input data hold
tIHO
10
ns
Output data delay
tOD
10
ns
________________________________________
Configuration of the Single Modem Mode V2.1 after a System/Soft Reset
• The configuration of the PSB4596 V2.1 in single modem mode is realized by
software using the 4-bit General Purpose I/O Interface of the PITA (See
“General Purpose I/O Interface” on page 5-65.).
• After a system/soft reset the FSC is an input pin both for
– the PITA
– the ALIS V2.1
• After a system reset the DCL_Out_En bit must be set to ’1’ by the host.
________________________________________
Semiconductor Group
5-30
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
PITA Configuration for ALIS V2.1 after a System Reset
Serial DMA Interface
Mode
Ser_Clock_Sel (clock
input to Serial DMA
interface)
ALIS V2.1
0
PCI clock/
40
DCL_Out_En (DCL
Direction)
1
DCL
output
________________________________________
Note
A Pull Down resistor is required on the board to avoid a floating FSC signal in this
situation.
________________________________________
Internal Registers: 04h
Bit 5:0
DMA Select
Type
RW
Default Value
000000b
Description
The DMA Control Register includes the 6 bit parameter DMA
Select.
Used to define the mode for the next DMA transfer:
Mode 1 (’000001’): Single Modem Mode V2.1
With the DMA_Start bit the DMA transfer can be started or
stopped.
________________________________________
Semiconductor Group
5-31
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Internal Register: 20h
Bit 1
DCL_Out_En
Type
RW
Default Value
0b
Description
Bit 1=’1’: The DCL signal is output (open drain) and driven
by the PITA.
Bit 0
Serial_Clock_Select
Type
RW
Default Value
0b
Description
Bit 0=’0’: The serial controller is driven with the clock signal
generated by the internal clock divider.
________________________________________
Semiconductor Group
5-32
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.7
Single Modem Mode ALIS V3.X
________________________________________
Overview
Overview
Page
Information about the Single Modem Mode ALIS V3.X
5-34
Internal Registers of the Single Modem Mode V3.X
5-36
________________________________________
Semiconductor Group
5-33
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.7.1
Information about the Single Modem Mode ALIS V3.X
________________________________________
Data in Circular Buffers, on Serial DMA Interface
Direction
Data in Circular Buffer
Transmit
Read from circular buffer:
[31:16] = don’t care
[15:0] = data frame [15:0]
Write to serial DMA interface:
Write to circular buffer:
[31:16] = don’t care
[15:0] = data frame [15:0]
Read from serial DMA interface:
Receive
Data on Serial DMA Interface
data frame [15:0]
data frame [15:0]
________________________________________
Timing Diagram
125 us
FSC (i)
DCL (i)
TXD (o)
16 bit data
RXD (i)
16 bit data
8 bit CMD
8 bit write data
8 bit read data
32 bit data / command frame
________________________________________
Semiconductor Group
5-34
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Note
The timing characteristics of the serial DMA interface in Single modem mode
V3.X mode are identical to the IOM-2 modes with the only difference that the DCL
signal is not a double bit clock, but a single bit clock, similar to Single Modem
mode V2.1.
________________________________________
Configuration of the Single Modem Mode V3.X after a System/Soft Reset
• Realized by starting the DMA transfer.
– Separate from this transfer the command byte and command data byte are
written to the ALIS Command Registers in the PITA on addresses 10h.
• After a system/soft reset the single modem mode V3.X is in the multiplexed
mode because the non multiplexed mode is not supported.
________________________________________
PITA Configuration for ALIS V3.X after a System Reset
Serial DMA Interface
Mode
Ser_Clock_Sel (clock
input to Serial DMA
interface
ALIS V3.X
1
2×ALIS V3.X
1
ALIS V3.X + second
codec
1
DCL_Out_En (DCL
Direction)
0
DCL input
clock
0
DCL_Out
_En
0
________________________________________
Semiconductor Group
5-35
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.7.2
Internal Registers of the Single Modem Mode V3.X
________________________________________
Internal Registers: 04h
Bit 5:0
DMA Select
Type
RW
Default Value
000000b
Description
The DMA Control Register includes the 6 bit parameter DMA
Select.
Used to define the mode for the next DMA transfer:
Mode 2 (’000010’): Single Modem Mode V3.X
With the DMA_Start bit the DMA transfer can be started or
stopped.
________________________________________
Internal Register: 10h
Bit 31:0
ALIS Command Register 1
Description
This command register is used for the first command
structure in the FSC time slot by the serial controller.
Bit 31:25
Reserved
Type
H
Default Value
0b
Description
Reserved
Semiconductor Group
5-36
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Register: 10h (cont’d)
Bit 24
New_ALIS_Command_1
Type
RW
Default Value
0b
Description
Bit 24=’1’: The host has written a new command to the ALIS
Command Resister 1.
Bit 24=’0’: Last command written to the ALIS Command
Register 1 by the host is processed and the received data is
available in the ALIS Received Data 1 register.
This bit is set by software if there is a new command in the
ALIS Command 1 Register. After the serial DMA interface
has transmitted the new command and the received data is
written to the ALIS_Received_Data_1 bits, this bit is reset by
the serial DMA interface.
Bit 23:16
ALIS_Received_Data_1
Type
RW
Default Value
00h
Description
During a DMA transfer in mode 2 or 3 every time a new
command is transferred through the serial DMA interface,
the received data is fetched and saved in this register.
New command means: The command was written through
the PCI interface to the ALIS command register.
Transferring a NOP command (FFh or 00h) leads to skipping
of the received data.
Semiconductor Group
5-37
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Register: 10h (cont’d)
Bit 15:8
ALIS_Command_1
Type
RW
Default Value
00h
Description
During a DMA transfer in mode 2 or 3 the contents of this
register are transferred as command through the serial DMA
interface.
After transferring the new command through the serial DMA
interface, the register is set to NOP (FFh).
Bit 7:0
ALIS_Transmit_Data_1
Type
RW
Default Value
00h
Description
During a DMA transfer in mode 2 or 3 the contents of this
register are transferred as data through the serial DMA
interface.
________________________________________
Semiconductor Group
5-38
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Internal Register: 14h
Bit 31:0
ALIS Command Register 2
Default Value
00000000h
Bit 31:25
Reserved
Type
H
Default Value
000h
Description
Reserved
Bit 24
New_ALIS_Command_2
Type
RW
Default Value
0b
Description
Bit 24=’1’: The host has written a new command to the ALIS
Command 2 Register.
Bit 24=’0’: Last command written to the ALIS Command 2
Register by the host is processed and the received data is
available in the ALIS Received Data 2 Register.
This bit is set by software if there is a new command in the
ALIS Command 2 Register. After the serial controller has
transmitted the new command and the received data is
written in the ALIS Received Data 2 Register, this bit is reset
by the serial controller.
Semiconductor Group
5-39
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Register: 14h (cont’d)
Bit 23:16
ALIS_Received_Data_2
Type
RW
Default Value
00h
Description
During a DMA transfer in mode 3 every time a new
command is transferred through the serial DMA interface,
the received data is fetched and saved in this register.
New command means: The command was written through
the PCI interface to the ALIS V3.X command register.
If only a NOP command (FFh or 00h) is transferred the
received data is skipped.
Bit 15:8
ALIS_Command_2
Type
RW
Default Value
00h
Description
During a DMA transfer in mode 3 the contents of this register
are transferred as command through the serial DMA
interface.
After transferring the new command through the serial DMA
interface, the register is set to NOP (FFh).
Bit 7:0
ALIS_Transmit_Data_2
Type
RW
Default Value
00h
Description
During a DMA transfer in mode 3 the contents of this register
are transferred as data through the serial interface.
________________________________________
Semiconductor Group
5-40
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Internal Register: 20h
Bit 1
DCL_Out_En
Type
RW
Default Value
0b
Description
Bit 1=’0’: The DCL signal is input and driven by the PITA.
Bit 0
Serial_Clock_Select
Type
RW
Default Value
0b
Description
Bit 0=’1’: The serial controller is driven with the external DCL
input clock.
________________________________________
Semiconductor Group
5-41
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.8
Dual Modem/Modem+Voice Mode
________________________________________
Description
• The PITA transmits and receives two 32 bit frames per FSC time slot.
• Each 32 bit frames consists of 16 bit data and 16 bit command/data
information.
• For each of the 32 bit frames the 16 bit transmitted data is read out of the TX
FIFO.
• The 16 bit transmitted data is written to the RX FIFO.
• The command read/write data for the first 32 bit frame is read out/written to the
ALIS Command Register 1 (10h)
• The command read/write data for the second 32 bit frame is read out/written to
the ALIS Command Register 2 (14h).
• The internal DMA write counter is incremented every second write transfer to
the circular buffer.
• A new frame transmission starts if the FSC is sampled ’1’ at a negative edge
of the DCL signal.
• The PITA starts driving the TXD line with the first bit of the transmitted data at
the next positive DCL edge.
• During the transmission the rising DCL edge indicates the start of a bit on the
TXD while the falling edge of the DCL is used to latch the RXD signal.
• The PITA stops driving the TXD signal with the positive DCL edge when bit 32
of the first or second transmitted frame is on the TXD line.
________________________________________
Semiconductor Group
5-42
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Data Organization in the Circular Buffer
Circular Buffer
Memory
31
16 15
0
31
16 15
8 7
TX Data 1 Modem 1
0
16 15
8 7
TX Data 1 Modem 2
0
Don´t care
0000h
0004h
0008h
0038h
003Ch
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
TX data 1
TX data 2
TX data 3
TX data 4
TX data 5
TX data 6
TX data 7
TX data 8
TX data 9
TX data 10
TX data 11
TX data 12
TX data 13
TX data 14
TX data 15
RX data 1
RX data 2
RX data 3
RX data 4
TX data 20
TX data 21
TX data 22
TX data 23
31
Don´t care
________________________________________
Timing Diagram for the Dual Modem Mode
125 us
FSC (i)
DCL (i)
TXD (o)
16 bit data
RXD (i)
16 bit data
8 bit CMD
8 bit write data
16 bit data
8 bit read data
16 bit data
32 bit data / command frame
8 bit CMD
8 bit write data
8 bit read data
32 bit data / command frame
________________________________________
Semiconductor Group
5-43
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Timing Diagram for the Dual Modem+Voice Mode
125 us
FSC (i)
DCL (i)
TXD (o)
16 bit data
RXD (i)
16 bit data
8 bit CMD
8 bit write data
16 bit data
8 bit read data
16 bit data
32 bit data / command frame
32 bit data frame
stuffing pattern ’FFh’
16 bit stuffing ’FFh’
________________________________________
Description of the Timing Diagram
•
•
•
•
The second 32 bit frame only consists of the 16 bit voice data.
The voice data is read out the TX FIFO.
The voice data is transmitted through the serial DMA interface (MSB first).
During this transmission the received 16 bit voice data (MSB first) is written to
the RX FIFO.
________________________________________
Internal Registers: 04h
Bit 5:0
DMA Select
Type
RW
Default Value
000000b
Description
The DMA Control Register includes the 6 bit parameter DMA
Select.
Used to define the mode for the next DMA transfer:
Mode 3 (’000100’): Single Dual Modem/Modem + Voice
Mode V3.X
With the DMA_Start bit the DMA transfer can be started or
stopped.
________________________________________
Semiconductor Group
5-44
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.1.9
Loop Back Mode
________________________________________
Description
If Loop_Back_Mode is set to ’1’ transmit data is transferred from the TX FIFO
back to the RX FIFO.
________________________________________
Mode Diagram
Circular Buffer
Memory
Data 3
Serial Controller
Data 3
Data 2
TX FIFO
DMA
Controller
Data 2
Loop
closed
RX FIFO
Data 1
PITA
Data 1
________________________________________
Semiconductor Group
5-45
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Internal Register: 28h
Bit 0
Loop_Back_Mode
Type
RW
Default Value
0b
Description
• Bit 0=’0’: The serial controller transmits and receives data/
commands through the serial DMA interface (normal
operation mode).
• Bit 0=’1’: The serial controller is in loop back mode.
– The serial DMA interface reads the data in the
transmitting FIFO and writes them in the receiving
FIFO.
– No data/command transmission will take place on the
serial DMA interface.
– The serial DMA interface is clocked with the defined
Ser_Clock_Sel bit.
________________________________________
Semiconductor Group
5-46
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.2
Parallel Interface
________________________________________
Description
The PITA has an 8 bit parallel interface to support three external components.
This parallel interface is implemented in multiplexed and non multiplexed mode.
It works in Siemens/Intel bus mode.
The parallel interface is by default in the non multiplexed mode.
________________________________________
Internal Register: 1Ch
Bit 26
Parallel_ interface_mode
Type
RW
Default Value
0b
Description
Bit 26=’0’: non multiplexed mode
Bit 26=’1’: multiplexed mode
Bit 24
Softreset_parallel_mode
Type
RW
Default Value
0b
Description
Bit 24=’0’: Deactivates the reset signal PRST to the
application.
Bit 24=’1’: Activates the high active reset signal PRST to the
application.
________________________________________
Semiconductor Group
5-47
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Mapping between PCI Data and Parallel Interface Data
Data on the
PCI bus AD31-0
PCI Byte
Enables
C/BE3-0
Data on the
Parallel Interface Data bus
PAD7-0
AD[31-8] = Don’t Care
AD[7-0] = Parallel
Interface Data
“XXX0”
PAD[7-0] = AD[7-0]
AD[31-8] = Don’t Care
AD[7-0] = Parallel
Interface Data
“XXX1”
No transaction, PCI interface
disconnects with Target Abort.
________________________________________
Address Mapping of the 4-kbyte PCI Address Space to the Parallel
Interface
Address on
the
PCI address
bus AD11-0
Chip Select on
the
parallel interface
Address on the
parallel interface address bus
PAD7-0 = AD9-2 (mux mode)
PA7-0 = AD9-2 (non-mux mode)
3FFh - 000h
CS2-0 = “110”
FFh - 00h
7FFh - 400h
CS2-0 = “101”
FFh - 00h
BFFh - 800h
CS2-0 = “011”
FFh - 00h
FFFh - C00h
CS2-0 = “111”
(not used)
________________________________________
Semiconductor Group
5-48
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Modes and Timing of the Parallel Interface
Modes and Timing
Page
ALE after System Reset
5-50
ALE after internal Software Reset
5-51
ALE after setting the Parallel Interface Mode Bit
5-52
Non Multiplexed Mode (Write Transaction)
5-53
Non Multiplexed Mode (Read Transaction)
5-54
Multiplexed Mode (Write Transaction)
5-55
Multiplexed Mode (Read Transaction)
5-56
Transaction Disconnect with Target Abort
5-57
Transaction Termination with Retry
5-60
Timing of the Parallel Interface
5-62
________________________________________
Semiconductor Group
5-49
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.2.1
ALE after System Reset
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
RST
PRST
ALE
WR
RD
________________________________________
Description
Both ALE and PRST are high during RST and remain high for a maximum of 4
cycles after RST goes deasserted.
________________________________________
Semiconductor Group
5-50
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.2.2
ALE after internal Software Reset
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
PRST
ALE
WR
RD
________________________________________
Description
• After the internal Soft Reset is deasserted the same behavior as in „ALE after
System Reset“ generated.
• The soft reset bit in the internal registers can only be set or reset if the parallel
interface is in idle state.
• If ALE is high before PAR_RST is asserted, it goes to low one cycle after PRST
and takes the new value depending on the PAR_MOD bit in the 6th cycle after
PRST is deasserted.
________________________________________
Semiconductor Group
5-51
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.2.3
ALE after setting the Parallel Interface Mode Bit
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
______
FRAME
____
IRDY
_____
TRDY
_______
DEVSEL
AD31-0
_______
C/BE3-0
_____
STOP
ADR1
DATA
ADR
DATA
CMD1
0000
CMD
0000
ALE
________________________________________
Description
• The parallel interface is in non multiplexed mode by default.
• To set the parallel interface into multiplexed mode:
The Parallel_Interface_Mode bit has to be set to ’1’ after reset.
• Two PCI clocks after finishing this data phase the ALE signal is asserted.
________________________________________
Semiconductor Group
5-52
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.2.4
Non Multiplexed Mode (Write Transaction)
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
FRAME
IRDY
TRDY
DEVSEL
AD31-0
ADR
DATA
C/BE3-0
CMD
XXX0
STOP
CS2-0
ALE
WR
RD
PA7-0
PAD7-0
XXXX
PCI-ADR[9-2]
XXXX
PCI-DATA[7-0]
________________________________________
Description
• After the address phase on the PCI bus (clock3) and the C/BE0=0 verification
the address decoding phase of the target (clocks 3 to 4) is active.
• The byte address for the transaction on the parallel interface is generated out
of the PCI address AD9-2 by mapping it to the parallel interface address bus
PA7-0.
• One PCI clock after the PCI data phase is finished the data from the PCI bus
is placed on the data bus PAD7-0 (clock 5) and the write transaction starts.
• The data is placed from the PCI bus on PAD7-0 asserting the WR signal and
a CS2-0 signal.
• A new access to the parallel interface could be accepted with an address
phase at clock 9. Any access before would be cancelled with Retry because
the PCI Interface is processing the last access.
________________________________________
Semiconductor Group
5-53
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.2.5
Non Multiplexed Mode (Read Transaction)
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
FRAME
IRDY
TRDY
DEVSEL
AD31-0
ADR
C/BE3-0
CMD
DATA
XXX0
STOP
CS2-0
ALE
WR
RD
PA7-0
XXXX
PCI-ADR[9-2]
PAD7-0
XXXX
DATA[7-0]
________________________________________
Description
• After the address phase on the PCI bus (clock3) and the C/BE0=0 verification
the address decoding phase of the target (clocks 3 to 4) is active.
• The byte address for the transaction on the parallel interface is generated out
of the PCI address AD9-2 by mapping it to the parallel interface address bus
PA7-0 (clock 5).
• The following PCI clock asserts the signals RD and CS2-0.
• After 5 clocks the RD signal is deasserted.
• The data from PAD7-0 is fetched.
• With the next clock the data is placed on the PCI bus and the data phase is
finished by deasserting the TRDY signal.
• The 8 bit data from the parallel interface is placed an the last significant byte
of the PCI data bus AD7-0.
________________________________________
Semiconductor Group
5-54
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.2.6
Multiplexed Mode (Write Transaction)
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
FRAME
IRDY
TRDY
DEVSEL
AD31-0
ADR
DATA1
C/BE3-0
CMD
XXX0
STOP
CS2-0
ALE
WR
RD
PAD7-0
PCI-ADR[9-2]
PCI-DATA1[7-0]
________________________________________
Description
• After the address phase on the PCI bus (clock 3) and the C/BE0=0 verification
the address decoding phase of the target (clocks 3 to 4) is active.
• The byte address for the transaction on the parallel interface address is
generated out of the PCI address AD9-2 by mapping it to the parallel interface
address bus PA7-0.
• One PCI clock after the PCI data phase is finished the data from the PCI bus
is placed on the data bus PAD7-0 (clock 5) and the write transaction starts.
• The data is placed from the PCI bus on PAD7-0 asserting the CS2-0 signal.
• The ALE signal is deasserted.
• With the following PCI clock the data from the PCI bus is placed on PAD7-0
(clock5).
• The WR signal is asserted.
• A new access to the parallel interface could be accepted with an address
phase at clock 11. Any access before would be cancelled with Retry because
the PCI Interface is processing the last access.
________________________________________
Semiconductor Group
5-55
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.2.7
Multiplexed Mode (Read Transaction)
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FRAME
IRDY
TRDY
DEVSEL
AD31-0
C/BE3-0
DATA1
$'5
CMD
XXX0
STOP
CS2-0
ALE
WR
RD
PAD7-0
PCI-ADR[9-2]
DATA1[23-16]
________________________________________
Description
• After the address phase on the PCI bus (clock 3) and the C/BE0=0 verification
the address decoding phase of the target (clocks 3 to 4) is active.
• The byte address for the transaction on the parallel interface is generated out
of the PCI address AD9-2 by mapping it to the parallel interface address bus
PA7-0 (clock 5).
• The following PCI clock asserts the ALE signal.
• After 2 clocks the ALE signal is deasserted.
• The address is held for one more clock.
• After 5 clocks the RD signal is deasserted.
• At the same time the data is latched in die PCI output registers.
• TRDY is asserted on the PCI bus to finish the data phase.
• At the next clock the CS2-0 and ALE signals are deasserted.
________________________________________
Semiconductor Group
5-56
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.2.8
Transaction Disconnect with Target Abort
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
FRAME
IRDY
TRDY
DEVSEL
AD31-0
ADR
DATA
ADR
DATA
C/BE3-0
CMD
XXX1
CMD
XXX1
STOP
CS2-0
ALE
WR
RD
PAD7-0
________________________________________
Description
C/BE0 = 1: No transaction is started on selected parallel interface, due to the
wrong byte enable. The PCI Master Target Controller disconnects the transaction
with target abort.
________________________________________
Semiconductor Group
5-57
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Configuration Space Register: 04h
Bit 30
System_Error_Signaled
Type
RC
Default Value
0b
Description
This bit is set by the PITA’s PCI Master, if the master asserts
the system error signal on the PCI bus. This occurs if a
transaction initiated by the PITA is disconnected with target
abort.
Bit 29
Master_Abort_Detected
Type
RC
Default Value
0b
Description
If no fast/medium/slow or subtractive slave reacts to a PCI
transaction initiated by the PCI Master, the master will
discard the transaction and set this bit.
Bit 28
Master_Abort_Detected
Type
RC
Default Value
0b
Description
If a PCI transaction initiated by the PCI Master is
disconnected with Target Abort, the PCI master will set this
bit. The PCI Master is not allowed to start a new PCI
transaction, until this bit is deasserted.
Semiconductor Group
5-58
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Configuration Space Register: 04h (cont’d)
Bit 27
Target_Abort_Signaled
Type
RC
Default Value
0b
Description
This bit is set by the PCI interface if a transaction was
disconnected with Target Abort. The PITA will disconnect
transactions with Target Abort if illegal byte enables are
detected.
Bit 8
System_Error_Enable
Type
RW
Default Value
0b
Description
If this bit is asserted, the PCI Master will assert the System
Error Signal (SERR) if it receives a target abort during a
transaction initiated by itself.
Bit 2
Master_Enable
Type
RW
Default Value
0b
Description
If this bit is set to ’0’ the PCI Master is not allowed to start any
transaction on the PCI Bus.
________________________________________
Semiconductor Group
5-59
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.2.9
Transaction Termination with Retry
________________________________________
Description’
Retry means that the PITA finishes a transaction without a data transfer by
asserting the signal STOP, because the parallel interface processes another
transaction.
The PCI Master Target Controller has to repeat the transaction until a slave
accepts the transaction with data transfer or target abort. This sequence is
invisible for the software.
________________________________________
Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
FRAME
IRDY
TRDY
DEVSEL
AD31-0
ADR1
DATA1
ADR2
DATA2
C/BE3-0
CMD1
XXX0
CMD2
XXX0
STOP
CS2-0
ALE
WR
RD
PAD7-0
PCI-ADR[9-2]
PCI-DATA1[7-0]
________________________________________
Semiconductor Group
5-60
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Explanation of ADR/CMD and ADR2/CMD2
ADR/CMD: The PCI Master Target Controller accepts the write transaction
ADR2/CMD2: The second transaction is retried.
________________________________________
Semiconductor Group
5-61
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.2.10
Timing of the Parallel Interface
________________________________________
Read Timing
tRR
tRI
RD x CS
tRD
tDF
AD0-AD7
Data
________________________________________
Write Timing
tWW
tWI
WR x CS
tWD
tDW
AD0-AD7
Data
________________________________________
Multiplexed Address Timing
tAA
tAD
ALE
WR x CS or
RD x CS
tALS
tAL
AD0-AD7
tLA
Address
________________________________________
Semiconductor Group
5-62
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Non Multiplexed Address Timing
WR x CS or
RD x CS
tAS
A0-A7
tAH
Address
________________________________________
Application Reset and Interrupt Timing
tROD
Host write
access to
the register
PRST, SRST
previous state
valid state
tIOD
INTO (i)
INT1 (i)
INTA (o)
________________________________________
Semiconductor Group
5-63
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Abbreviations of the Timing Diagrams
Parameter
Symbol
PCI
Clock
Cycles
Limit
Values
min.
Unit
max
.
ALE pulse width
tAA
5
150
ns
Address setup time to ALE
tAL
1
30
ns
Address hold time from ALE
tLA
1
30
ns
Address latch setup time to WR,
RD
tALS
1
30
ns
Address setup time
tAS
1
30
ns
Address hold time
tAH
1
30
ns
ALE guard time
tAD
1
30
ns
RD pulse width
tRR
5
150
ns
Data output delay from RD
tRD
5
150
ns
Data float from RD
tDF
1
30
ns
RD control interval
tRI
5
150
ns
W pulse width
tWW
3
90
ns
Data setup time to W x CS
tDW
2
60
ns
Data hold time W x CS
tWD
1
30
ns
W control interval
tWI
3
90
ns
Reset Output Delay
tROD
3
90
ns
Interrupt Output Delay
tIOD
2
60
ns
________________________________________
Semiconductor Group
5-64
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.3
General Purpose I/O Interface
________________________________________
Overview
Overview
Page
Information about the GP I/O Interface
5-66
Timing of the GP I/O Interface
5-68
Internal Registers of the GP I/O Interface
5-69
Input Mode
5-76
Output Mode
5-78
Interrupt Mode
5-80
Usage of the GP I/O Interface as ALIS V2.1 Control Interface
5-82
________________________________________
Semiconductor Group
5-65
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.3.1
Information about the GP I/O Interface
________________________________________
Description
For additional access to external devices with a slow interface behavior a 4 bit
General Purpose I/O interface is implemented in the PITA.
________________________________________
Pinning
Pin
Pin Name
General Purpose I/O
Function
SPI EEPROM
Function
2
GP0
I/O/Int.
SO
3
GP1
I/O/Int.
SI
4
GP2
I/O/Int.
SCK
5
GP3
I/O/Int.
–
________________________________________
Application Interrupt
• The PCI interface supports 2 separate interrupt inputs.
• Four pins of the general purpose I/O interface can be used as additional
interrupt inputs.
• Each of these 6 interrupts has an Interrupt_Enable bit and an
Interrupt_Control_Status bit.
• For the two separate inputs (INT0 and INT1) the enable bit is located in the
Interrupt Control Register.
• For the General Purpose I/O the enable bit is located in the Interface Control
Register.
________________________________________
Semiconductor Group
5-66
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Control Registers for GPx Pins
Register
Register Bit
Description
Interrupt Control Register
- ICR
GPx_INT
GP Interrupt Status
GPx_INT_En
GP Interrupt Enable
GPx_OUT_En
GP Output Enable
GPx_OUT
GP Output Value
GPx_IN
GP Input Value
GP I/O Interface Control
Register
________________________________________
Semiconductor Group
5-67
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.3.2
Timing of the GP I/O Interface
________________________________________
Timing Diagram
tOD
Host write
access
GPx configured
as output
GP0-3 (o)
valid state
tISU
tIHO
Host read
access
GP0-3 (i)
GPx configured
as input
valid state
tIOD
GP0-3 (i)
GPx configured
as interrupt input
INTA (o)
________________________________________
Abbreviations of the Timing Diagram
Parameter
Symbol
Limit Values
min.
Unit
max.
90
ns
GPx Output Data Delay
tOD
GPx Input Data Setup
tISU
30
ns
GPx Input Data Hold
tIHO
30
ns
GPx Interrupt Output
Delay
tIOD
Semiconductor Group
5-68
90
ns
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.3.3
Internal Registers of the GP I/O Interface
________________________________________
Internal Register: 00h
Bit 5
GP3_INT
Type
RC
Default Value
0b
Description
The GP3 pin can be used as ’active low’ interrupt input if
GP3_Int_En=’1’ and GP3_Out_En=’0’.
The bit is set to ’1’ if both are true and low is detected at this
pin.
Bit 4
GP2_INT
Type
RC
Default Value
0b
Description
The GP2 pin can be used as ’active low’ interrupt input if
GP2_Int_En=’1’ and GP2_Out_En=’0’.
The bit is set to ’1’ if both are true and low is detected at this
pin.
Bit 3
GP1_INT
Type
RC
Default Value
0b
Description
The GP1 pin can be used as ’active low’ interrupt input if
GP1_Int_En=’1’ and GP1_Out_En=’0’.
Semiconductor Group
5-69
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Register: 00h (cont’d)
Bit 2
GP0_INT
Type
RC
Default Value
0b
Description
The GP0 pin can be used as ’active low’ interrupt input if
GP0_Int_En=’1’ and GP0_Out_En=’0’.
________________________________________
Internal Register: 18h
Bit 31:0
GP I/O Interface Control Register
Type
00000000h
Bit 31:28
Reserved
Type
H
Default Value
0h
Description
Reserved
Bit 27
GP3_Int_En
Type
RW
Default Value
0b
Description
Bit 27=’1’: GP3 is configured as input, the pin is used as an
interrupt input with GP3_Int_en as corresponding bit in the
Interrupt Control Register.
Bit 27=’1’: GP3 is not used as an interrupt pin.
Semiconductor Group
5-70
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Register: 18h (cont’d)
Bit 26
GP2_Int_En
Type
RW
Default Value
0b
Description
Bit 26=’1’: GP2 is configured as input, the pin is used as an
interrupt input with GP2_Int_en as corresponding bit in the
Interrupt Control Register.
Bit 26=’0’: GP2 is not used as an interrupt pin.
Bit 25
GP1_Int_En
Type
RW
Default Value
0b
Description
Bit 25=’1’: GP1 is configured as input, the pin is used as an
interrupt input with GP1_Int_en as corresponding bit in the
Interrupt Control Register.
Bit 25=’0’: GP1 is not used as an interrupt pin.
Bit 24
GP0_Int_En
Type
RW
Default Value
0b
Description
Bit 24=’1’: GP0 is configured as input, the pin is used as an
interrupt input with GP0_Int_en as corresponding bit in the
Interrupt Control Register.
Bit 24=’0’: GP0 is not used as an interrupt pin.
Semiconductor Group
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Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Register: 18h (cont’d)
Bit 23:20
Reserved
Type
H
Default Value
000b
Description
Reserved
Bit 19
GP3_Out_En
Type
RW
Default Value
0b
Description
Bit 19=’1’: GP_3 is configured as output pin.
Bit 19=’0’: GP_3 is configured as input pin.
Bit 18
GP2_Out_En
Type
RW
Default Value
0b
Description
Bit 18=’1’: GP_2 is configured as output pin.
Bit 18=’0’: GP_2 is configured as input pin.
Bit 17
GP1_Out_En
Type
RW
Default Value
0b
Description
Bit 17=’1’: GP_1 is configured as output pin.
Bit 17=’0’: GP_1 is configured as input pin.
Semiconductor Group
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Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Register: 18h (cont’d)
Bit 16
GP0_Out_En
Type
RW
Default Value
0b
Description
Bit 16=’1’: GP_0 is configured as output pin.
Bit 16=’0’: GP_0 is configured as input pin.
Bit 15:12
Reserved
Type
H
Default Value
000b
Description
Reserved
Bit 11
GP3_IN
Type
R
Default Value
0b
Description
Actual Value on the GP3 pin (pin feedback)
Bit 10
GP2_IN
Type
R
Default Value
0b
Description
Actual Value on the GP2 pin (pin feedback)
Semiconductor Group
5-73
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Register: 18h (cont’d)
Bit 9
GP1_IN
Type
R
Default Value
0b
Description
Actual Value on the GP1 pin (pin feedback)
Bit 8
GP0_IN
Type
R
Default Value
0b
Description
Actual Value on the GP0 pin (pin feedback)
Bit 7:4
Reserved
Type
H
Default Value
0000b
Description
Reserved
Bit 3
GP3_OUT
Type
RW
Default Value
0b
Description
The GP3 pin is driven with the value written to this output
register if the GP3_OUT_En is set to ’1’.
Semiconductor Group
5-74
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Register: 18h (cont’d)
Bit 2
GP2_OUT
Type
RW
Default Value
0b
Description
The GP2 pin is driven with the value written to this output
register if the GP2_OUT_En is set to ’1’.
Bit 1
GP1_OUT
Type
RW
Default Value
0b
Description
The GP1 pin is driven with the value written to this output
register if the GP1_OUT_En is set to ’1’.
Bit 0
GP0_OUT
Type
RW
Default Value
0b
Description
The GP0 pin is driven with the value written to this output
register if the GP0_OUT_En is set to ’1’.
________________________________________
Semiconductor Group
5-75
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.3.4
Input Mode
________________________________________
Description
For using a general purpose I/O pin as input pin, the control register must be
configured as follows:
GPx_OUT_En = ‘0’
(Output disabled)
GPx_INT_En
(Interrupt disabled)
= ‘0’
(x := [0, 3])
Description of the internal register 18h on page 5-70.
The GPx_OUT and GPx_INT bits can be treated as don’t care in this mode. The
current signal value at the pin GPx can be read from register bit GPx_IN.
________________________________________
Internal Structure of a GPx Input Pin
D
Q
GPx
Q
GPx_IN
________________________________________
Timing Diagram
tISU
tIHO
Host read
access
GP0-3 (i)
GPx configured
as input
valid state
________________________________________
Semiconductor Group
5-76
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Abbreviations of the Timing Diagram
Parameter
Symbol
Limit Values
min.
Unit
max.
GPx Input Data Setup
tISU
30
ns
GPx Input Data Hold
tIHO
30
ns
________________________________________
Semiconductor Group
5-77
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.3.5
Output Mode
________________________________________
Description
For using a general purpose I/O pin as output pin, the control register must be
configured as follows:
GPx_OUT_En = ‘1’
(Output enabled)
GPx_INT_En
‘don’t care’
=
(x := [0, 3])
Description of the internal register 18h on page 5-70.
The GPx_IN and GPx_INT register bits can be treated as don’t care in this mode.
The GPx pin will drive the connected signal line with the value defined in the
GPx_OUT register bit, which is programmed by the host.
________________________________________
Internal Structure of a GPx Output Pin
D
Q
GPx
Q
En
GPx_Out
D
Q
Q
GPx_Out_En
________________________________________
Semiconductor Group
5-78
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Timing Diagram
tOD
Host write
access
GPx configured
as output
GP0-3 (o)
valid state
________________________________________
Abbreviation of the Timing Diagram
Parameter
Symbol
Limit Values
min.
GPx Output Data Delay
tOD
Unit
max.
90
ns
________________________________________
Semiconductor Group
5-79
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.3.6
Interrupt Mode
________________________________________
Description
For using a general purpose I/O pin as output pin, the control register must be
configured as follows:
GPx_OUT_En = ‘1’
(Output disabled)
GPx_INT_En
(Interrupt enabled)
= ‘1’
(x := [0, 3])
Description of the internal register 18h on page 5-70.
The GPx_OUT register bit can be treated as don’t care in this mode. The GPx pin
acts as an active low interrupt input pin.
If the device detects ’0’ at the GPx pin
• the GPx_INT register is set to ’1’
• an interrupt on the PCI bus is generated
• the current state of the GPx pin can be read from GPx_IN bit or can be treated
as don’t care.
________________________________________
Internal Structure of a GPx Interrupt Input pin
D
Q
GPx
1
x
3
Q
>=1
0
INTA
4
GPx_IN
________________________________________
Timing Diagram
tIOD
GP0-3 (i)
GPx configured
as interrupt input
INTA (o)
________________________________________
Semiconductor Group
5-80
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Abbreviation of the Timing Diagram
Parameter
Symbol
Limit Values
min.
GPx Interrupt Output
Delay
tIOD
Unit
max.
90
ns
________________________________________
Semiconductor Group
5-81
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.3.7
Usage of the GP I/O Interface as ALIS V2.1 Control
Interface
________________________________________
The serial control interface of the ALIS V2.1 can be realized by software using the
General Purpose I/O pins.
The GP3 pin is used as CS pin while the other three GPx pins are shared with the
SPI EEPROM Interface.
The GP3 pin is driven high during the automatic EEPROM configuration phase
after a system reset to disable the ALIS V2.1 control interface.
Pin description on page 7-7.
________________________________________
Description
PITA Signals
ALIS Signals
Description
GP3
Out
CS
Chip select (active low), for enabling
the PSB4596 Control Interface.
GP2
Out
DCLK
Clock signal for the Control
Interface.
(PSB4596 accepts 1 kHz to 1024
kHz)
GP1
In
DOUT
Data input for PITA, data output from
PSB4596.
Data input is latched at the negative
DCLK edge.
GP0
Out
DIN
Data output from PITA, data input for
PSB4596.
Data output changes with the rising
DCLK edge.
INT1
In
INT
Interrupt signal (high active)
SRST
Out
RESET
Reset signal (low active)
________________________________________
Semiconductor Group
5-82
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Timing Diagram for a Write Transaction with two Data Bytes transmitted
Control Frame
GP3 (o) / CS (i)
GP2 (o) / DCLK (i)
GP1 (i) / DOUT (o)
GP0 (o) / DIN (i)
High `Z´
76543210 76 54321 07654 32 10
Control
Data Byte 1
Data Byte 2
________________________________________
Timing Diagram for a Read Access with one Data Byte received via DOUT
Control Frame
GP3 (o) / CS (i)
GP2 (o) / DCLK (i)
GP1 (i) / DOUT (o)
GP0 (o) / DIN (i)
High `Z´
76 54321 07654 32 10
High `Z´
76543210
Control
Identification
Data Byte 1
________________________________________
Semiconductor Group
5-83
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.4
SPI EEPROM Interface
________________________________________
Overview
Overview
Page
Information about the SPI EEPROM Interface
5-85
Timing of the SPI EEPROM Interface
5-88
Internal Registers for the SPI EEPROM Interface
5-90
________________________________________
Semiconductor Group
5-84
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.4.1
Information about the SPI EEPROM Interface
________________________________________
Description
Three pins are used to provide an SPITM-compatible serial interface to a 256 x 8
bit EEPROM. These pins also do double-duty as part of the General Purpose
Interface. Two other pins are also used to select the EEPROM chip and to enable/
disable the automatic reconfiguration of the configuration space by the EEPROM.
This would occur after a system reset.
The EEPROM can be used for:
• Automatic reconfiguration of the PITA.
• Customer specific purposes (e.g. storage of serial board numbers).
________________________________________
Automatic reconfiguration of the PITA
Parts of the PCI Configuration Space can be configured with data from this
external EEPROM after system reset. The following sequence is processed by
the PITA:
• The PITA checks:
– Whether the ELD (EEPROM_Load) pin is clamped to ’1’.
– Whether the first byte in the EEPROM (address location 00h) is AAh.
• If the first step was successful, the PITA starts:
– Reading out four bytes starting with address 01h.
– Writing the read values in the configuration space address 00h.
– Reading out the next four bytes.
– Writing the read values in the configuration space address 04h.
– And so on.
________________________________________
Note
During the configuration phase, all access to the PCI interface are answered with
’Retry’ by the PITA.
________________________________________
Semiconductor Group
5-85
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
Using the EEPROM for customer specific purposes
The contents of the EEPROM can be programmed by writing a command to the
EEPROM Control Register and initiating a read/write transaction to the
EEPROM.
________________________________________
Note
If the automatic reconfiguration of the PITA is used (ELD pin clamped to ’1’), only
those addresses in the EEPROM not mapped to the PCI configuration space
should be used.
________________________________________
Starting a read or write transaction
The contents of the EEPROM can be programmed by writing a command to the
EEPROM Control Register and initiating a read/write transaction to the
EEPROM.
• The host writes
– The EEPROM Command value before the next EEPROM transfer is started.
– The EEPROM Byte Address value for read or write access.
– The EEPROM Data value for the ’Write Status Register’ and ’Write Data to
Memory Array’.
• The host sets the EEPROM_Start bit.
• If the EEPROM interface detects the asserted EEPROM_Start bit; it
– Interprets the EEPROM Command.
• Starts the read or write transaction to the connected EEPROM.
• If the transactions are started via the EEPROM Control register, then the
EEPROM interface does not check for a connected EEPROM.
________________________________________
Semiconductor Group
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Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
________________________________________
After finishing the transaction:
• The EEPROM control module:
– Deasserts the EEPROM_Start bit.
– Generates an interrupt in the EEPROM Control Int Register, if the
EEPROM_Control_Int_en bit is set to ’1’.
• If The EEPROM Command Register is set to RDSR or READ, then the value
of the EEPROM is available in the EEPROM Data Register.
________________________________________
Connection of an ALIS V2.1 device to the Serial Control Interface
For the connection of an ALIS V2.1 device to the Serial Control Interface of the
PITA the GP3 pin is additionally used as low active chip select signal CS to the
ALIS V2.1.
The GP3 pin is always driven ’high’ and therefore the ALIS V2.1 interface is
inactive during the phase of automatic initialization of the PCI Configuration
Space.
________________________________________
Semiconductor Group
5-87
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.4.2
Timing of the SPI EEPROM Interface
________________________________________
Timing Diagram
tCSI
EPCS (o)
tCSS
tCYC
tOR
tOF
tCSH
SCK (o)
tCLH
tCLL
tISU
tIHO
SO (i)
LSB in
tOSU
tOHO
tOD
SI (o)
high-Z
LSB out
________________________________________
Abbreviations of the Timing Diagram
Parameter
Symbol
Limit Values
min.
Unit
max.
Chip Select Setup Time
tCSS
500
ns
Chip Select Hold Time
tCSH
500
ns
Chip Select Inactive
tCSI
500
ns
Clock Cycle Time
tCYC
1000
ns
Clock HIGH Time
tCLH
410
ns
Clock LOW Time
tCLL
410
ns
Clock Output Rise Time
tOR
2
µs
Clock Output Fall Time
tOF
2
µs
Input Data Setup Time
tISU
100
ns
Input Data Hold Time
tIHO
100
ns
Output Data Setup Time
tOSU
Semiconductor Group
5-88
500
ns
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Abbreviations of the Timing Diagram (cont’d)
Parameter
Symbol
Limit Values
min.
Output Data Hold Time
tOHO
0
Unit
max.
500
ns
Output Disable Time
tOD
500
ns
Write Cycle Time
tWC
10
ms
________________________________________
Note
The SCK is a strobed clock signal (i.e. it is only active as long as valid data is
transferred on SI/SO line) and output data is written on the falling edge and input
data is latched on the rising edge. Although the first SCK edge is positive, the
PITA drives the first valid bit on SI (output) with the falling edge of EPCS, so the
minimum setup time with respect to the first SCK rising edge is guaranteed.
________________________________________
Semiconductor Group
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Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
5.4.3
Internal Registers for the SPI EEPROM Interface
________________________________________
Internal Register: 00h
Bit 28
EEPROM_Control_Int_En
Type
RW
Default Value
0b
Description
Enable for the EEPROM_Control_Int interrupt bit
Bit 12
EEPROM_Control_Int
Type
RC
Default Value
0b
Description
The EEPROM_Control_Int_En bit and the EEPROM are set
to ’1’ if the transaction is finished.
________________________________________
Internal Register: 24h
Bit 31:0
EEPROM Control Register
Default Value
00000000h
Bit 31:25
Reserved
Type
H
Default Value
0000h
Description
Reserved
Semiconductor Group
5-90
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Register: 24h (cont’d)
Bit 24
EEPROM_Start
Type
RW
Default Value
0b
Description
Bit 24=’1’: An EEPROM transaction is started with the
EEPROM Command, EEPROM Data and EEPROM Byte
Address.
BIT 24=’0’: An EEPROM transaction can be started.
Bit 23:16
EEPROM Command
Type
RW
Default Value
00h
Description
The following SPI commands are supported:
’00000110’: WREN
Set Write Enable Latch
’00000100’: WRDI
Reset Write Enable Latch
’00000101’: RDSR
Read Status Register
’00000001’: WRSR
Write Status Register
’00000011’: READ
Read Data from Memory Array
’00000010’: WRITE
Write Data to Memory Array
’OTHERS’:
No action
Bit 15:8
EEPROM Byte Address
Type
RW
Default Value
00h
Description
Byte Address for the next EEPROM read or write
transaction.
Semiconductor Group
5-91
Preliminary Data Sheet 12.98
PSB 4600
Communication with external Components
Internal Register: 24h (cont’d)
Bit 7:0
EEPROM Data
Type
RW
Default Value
00h
Description
• Transaction with a read command:
After the transaction has been finished this register
contains the byte that has been read from the EEPROM.
• Transaction with a write command:
The contents of this register will be written to the
EEPROM Byte Address if the connected EEPROM after
the EEPROM_Start bit is set.
________________________________________
Semiconductor Group
5-92
Preliminary Data Sheet 12.98
PSB 4600
Configuration of the PITA
6
Configuration of the PITA
________________________________________
Pinstrapping
Pinstrapping is used for:
• Loading the Subsystem Vendor ID.
• Loading the least significant 4 bits of the Subsystem ID to the PCI
Configuration Space.
Several output pins from the parallel microcontroller interface and the general
purpose I/O interface are implemented as tristate output pins.
During PCI reset they are driven in tristate mode and the external logic value is
latched in the Subsystem ID (4 LSBs) and the Subsystem Vendor ID. This means
that the signals on board, connected to these pins, must be forced with pullup/
pulldown resistors to the desired value if they are not driven by the PITA.
________________________________________
Pins Used for Pinstrapping During PCI Reset
Signal Name
Usage during PCI Reset
(pinstrapping)
I/O
PAD(7:0)
Subsystem Vendor ID(15:8)
IO
PA(7:0)
Subsystem Vendor ID(7:0)
OTS
GP3
Subsystem ID(3)
IO
GP2
Subsystem ID(2)
IO
GP1
Subsystem ID(1)
IO
GP0
Subsystem ID(0)
IO
________________________________________
Automatic reconfiguration of the PITA with the serial EEPROM
The PITA can also be configured by the EEPROM after system reset. Pinstrap
values are overwritten by this process if the procedure described in “Automatic
reconfiguration of the PITA” on page 85 was successful.
________________________________________
Semiconductor Group
6-1
Preliminary Data Sheet 12.98
PSB 4600
Pinning
7
Pinning
________________________________________
PITA Pinout
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
CS1
CS2
INTA
VDD3
VSS
VDD5
VDD3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
C/BE0
AD8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
This illustration shows the numbered pins and their respective signals:
PRST
76
50
AD9
PAD7
77
49
AD10
PAD6
78
48
AD11
PAD5
79
47
AD12
PAD4
80
46
AD13
PAD3
81
45
AD14
PAD2
82
44
AD15
PAD1
83
43
C/BE1
PAD0
84
42
PAR
RD
85
41
SERR
WR
86
40
PERR
39
STOP
38
DEVSEL
37
TRDY
PITA
T-QFP-100-1
17
18
19
20
21
22
23
24
25
AD29
AD28
AD27
AD26
AD25
AD24
C/BE3
IDSEL
AD23
16
26
AD30
100
AD31
AD22
ECS
15
AD21
27
VDD3
28
99
14
98
ELD
13
INT1
VSS
AD20
VDD5
AD19
29
12
30
97
VDD3
96
FSC
11
TXD
10
AD18
GNT
31
REQ
95
9
AD17
RXD
CLK
AD16
32
8
33
94
7
93
DCL
RST
SRST
PME
C/BE2
6
34
CLKRUN
92
5
FRAME
INT0
4
IRDY
35
GP0
36
91
GP1
90
ALE
3
VDD5
GP2
89
2
VSS
1
88
GP3
87
TEST
CS0
VDD3
________________________________________
Semiconductor Group
7-1
Preliminary Data Sheet 12.98
PSB 4600
Pinning
________________________________________
Overview
The following table lists the interfaces and their respective pins:
Interface
Total
In
Out
I/O
Page
PCI bus
52
4
5
43
7-3
Parallel Interface
23
3
14
8
7-4
Serial Interface
5
2
2
1
7-6
GP I/O Interface
4
0
0
4
7-7
Special EEPROM
Signals
2
1
1
0
7-8
Test IF
1
1
0
7-8
Power Supply
11
11
0
7-8
Total
100
11
22 (+11
Power
Supply)
56
-
________________________________________
Description of PIN Types
Type
Description
O
Output Pin
I
Input Pin
IO
Bidirectional Input/Output Pin
(OD)
Open Drain
________________________________________
Semiconductor Group
7-2
Preliminary Data Sheet 12.98
PSB 4600
Pinning
________________________________________
This table lists the Pins Characteristics of the PCI Bus
Pin No.
Signal
Name
Pin Count
Type
Function
9
CLK
1
I
PCI - Clock (max. 33
MHz)
8
RST
1
I
PCI - Reset
16 - 23,
26 - 33,
44 - 51,
53 - 60
AD(31:0)
32
IO
PCI - Address-/Data
bus
24, 34,
43, 52
C/BE(3:0)
4
IO
PCI - Command/Byte
Enable Bus
(Byte Enables are low
active)
42
PAR
1
IO
PCI - Parity
65
INTA
1
OD
PCI - Interrupt Signal
25
IDSEL
1
I
PCI - Initialization
Device Select Signal
For CardBus boards
this signal must set to
‘1’
35
FRAME
1
IO
PCI - Frame
36
IRDY
1
IO
PCI - Initiator Ready
37
TRDY
1
IO
PCI -Target Ready
38
DEVSEL
1
IO
PCI - Device Select
39
STOP
1
IO
PCI - Stop
11
REQ
1
OTS
10
GNT
1
I
Semiconductor Group
7-3
PCI - Bus Request
PCI - Bus Grant
Preliminary Data Sheet 12.98
PSB 4600
Pinning
This table lists the Pins Characteristics of the PCI Bus (cont’d)
Pin No.
Signal
Name
Pin Count
Type
Function
40
PERR
1
IO
PCI - Parity Error
41
SERR
1
OD
PCI - System Error
7
PME
1
OD
PCI - Power
Management Event
6
CLKRUN
1
I
Clock Run
________________________________________
This table lists the Pins Characteristics of the Parallel Interfaces
Pin No.
Signal
Name
Pin Count
Type
Function
76
PRST
1
O
Active high reset
66, 67,
87
CS(2:0)
3
O
Chip Select Signals for
three devices
connected to the
parallel microcontroller
interface.
84 - 77
PAD(7:0)
8
IO
- Multiplexed Bus
Mode:
Address/Data bus for
the parallel interface.
- Non-Multiplexed Bus
Mode:
Data bus for the parallel
interface.
Semiconductor Group
7-4
Preliminary Data Sheet 12.98
PSB 4600
Pinning
This table lists the Pins Characteristics of the Parallel Interfaces (cont’d)
Pin No.
Signal
Name
Pin Count
Type
Function
75 - 68
PA(7:0)
8
OTS
- Multiplexed Bus
Mode:
Not used; pins can be
left not connected.
- Non-Multiplexed Bus
Mode:
Address bus for the
parallel interface.
91
ALE
1
O
Address Latch Enable
Signal, active high.
In non-multiplexed
mode the ALE input of
peripheral devices
must be connected to
VSS.
86
WR
1
O
Write Signal, active low
85
RD
1
O
Read Signal, active low
92
INT0
1
I
Standard active low
interrupt input for
connected devices,
which is forwarded to
the PCI interface
(INTA).
98
INT1
1
I
Standard Active High
Interrupt Input for
connected devices,
which is forwarded to
the PCI interface
(INTA).
________________________________________
Semiconductor Group
7-5
Preliminary Data Sheet 12.98
PSB 4600
Pinning
________________________________________
This table list the Pins Characteristics of the Serial Interface
Pin No.
Signal
Name
Pin Count
Type
Function
93
SRST
1
O
Active low reset output.
97
FSC
1
I
Frame Synchronisation
Clock signal, 8 kHz.
94
DCL
1
I
O (OD)
Serial Data Clock
Signal.
The direction of this pin
can be controlled by the
DCL_Out_En bit in the
internal registers. By
default this pin is input.
For PSB4596 V2.1
mode, this pin must
configured as output
(open drain), for all
other modes this pin
must be input.
95
RXD
1
I
Serial Data Input Signal
96
TXD
1
O (OD)
Serial Data Output
Signal
________________________________________
Semiconductor Group
7-6
Preliminary Data Sheet 12.98
PSB 4600
Pinning
________________________________________
This table lists the Pins Characteristics of the General Purpose I/O
Interface
Pin No.
Signal
Name
Pin Count
Type
Function
2
GP3
1
IO
General Purpose I/O
Pin 3
This pin is driven high
during the automatic
EEPROM configuration
if ELD = ‘1’.
3
GP2
1
IO
General Purpose I/O
Pin 2
Serial EEPROM
Interface : SCK - Serial
Clock Signal.
4
GP1
1
IO
General Purpose I/O
Pin 1
Serial EEPROM
Interface : SO - Serial
Data Output from
EEPROM (input to the
PITA).
5
GP0
1
IO
General Purpose I/O
Pin 0
Serial EEPROM
Interface : SI - Serial
Data Input to the
EEPROM (output from
the PITA).
________________________________________
Semiconductor Group
7-7
Preliminary Data Sheet 12.98
PSB 4600
Pinning
________________________________________
This table lists the Pins Characteristics of the Special EEPROM Signals
Pin No.
Signal
Name
Pin Count
Type
Function
99
ELD
1
I
EEPROM Load
’1’ -> EEPROM
Configuration is
enabled.
’0’ -> EEPROM
Configuration is
disabled.
100
ECS
1
O
EEPROM Chip Select
(SPI Signal)
________________________________________
This table lists the Pins Characteristics of the Test IF
Pin No.
1
Signal
Name
TEST
Pin Count
1
Type
I
Function
Test Input
________________________________________
Semiconductor Group
7-8
Preliminary Data Sheet 12.98
PSB 4600
Pinning
________________________________________
This table lists the Pins Characteristics of the Power Supply
Pin No.
12, 15,
Signal
Name
Pin Count
Type
Function
VDD3
5
I
Positive Power Supply
3.3V ± 10%
VDD5
3
I
Positive Power Supply
5V ± 10%
VSS
3
I
Ground 0V
61, 64,
88
14, 62,
90
13, 63, 89
________________________________________
Semiconductor Group
7-9
Preliminary Data Sheet 12.98
PSB 4600
Package Outlines
8
Package Outlines
Semiconductor Group
8-1
Preliminary Data Sheet 12.98
PSB 4600
Precaution
9
Precaution
________________________________________
Overview:
Overview
Page
Absolute Maximum Ratings
9-2
DC Characteristics
9-3
AC Characteristics
9-5
Capacitances
9-6
________________________________________
Semiconductor Group
9-1
Preliminary Data Sheet 12.98
PSB 4600
Precaution
9.1
Absolute Maximum Ratings
________________________________________
This Table shows the Parameters for the Absolute Maximum Ratings
Parameter
Limit Values
Unit
Voltage on any pin
with respect to ground
VS
– 0.3 to VDD5 + 0.3
V
Ambient temperature under bias
TA
0 to 70
°C
Storage temperature
Tst
– 65 to 150
°C
7
V
g
Maximum voltage on VDD3/VDD5
VD
D
________________________________________
Note:
Stresses above those listed under ’Absolute Maximum Ratings’ may cause
permanent damage to the device.
Exposure to conditions beyond those indicated in the recommended operational
conditions of this specification may affect device reliability.
This is a stress rating only and functional operation of the device under these
conditions or at any other condition beyond those indicated in the operational
conditions of this specification is not implied.
________________________________________
Semiconductor Group
9-2
Preliminary Data Sheet 12.98
PSB 4600
Precaution
9.2
DC Characteristics
________________________________________
Description
The following DC characteristics are valid for all pins of the PITA except the PCI
Interface.
________________________________________
Conditions
TA = 0 to 70 °C; VDD5 = 5 V ± 10 %, VDD3 = 3.3 V ± 10 %, VSS = 0 V;
________________________________________
DC Characteristics
Parameter
Sym
Limit Values
min
typ
Unit
Test Condition
max
L-input
voltage
VIL
–0.3
0.8
V
H-input
voltage
VIH
2.0
VDD5
+ 0.3
V
L-output
voltage
VOL
0.45
V
IOL = 7 mA (TXD,
RXD)
IOL = 2 mA (all others)
H-output
voltage
VOH
V
IOH = – 400 µA
VDD3
Power
supply
current
Icc
19
mA
All power states
except D3cold (power
off state)
VDD5
Power
supply
current
Icc
1
mA
All power states
except D3cold (power
off state)
Semiconductor Group
Rem.
2.4
9-3
Preliminary Data Sheet 12.98
PSB 4600
Precaution
DC Characteristics (cont’d)
Parameter
Sym
Limit Values
min
1)
typ
Unit
Test Condition
Rem.
1)
max
Input
leakage
current
ILI
1
uA
0 V < VIN < VDD5
Output
leakage
current
ILO
1
uA
0 V < VOUT < VDD5
(except for TEST, INT0 which are internally pulled up (ILI = 300 uA) and INT1, CLKRUN which are
internally pulled down (ILIh = 500 uA)
________________________________________
Semiconductor Group
9-4
Preliminary Data Sheet 12.98
PSB 4600
Precaution
9.3
AC Characteristics
________________________________________
Description
Inputs are driven to 2,4 V for a logical ’1’ and to 0.45 V for a logical ’0’. Timing
measurements are made at 2.0 V for a logical ’1’ and 0.8 V for a logical ’0’.
________________________________________
Conditions
TA = 0 to 70 °C, VDD5 = 5 V ± 10%, VDD3 = 3.3 V ± 10%, VSS = 0 V.
________________________________________
AC Testing Input/Output Waveform
2.4
2.0
2.0
Device
Under
Test
Test Points
0.8
0.8
CLoad=100pF
0.45
________________________________________
Semiconductor Group
9-5
Preliminary Data Sheet 12.98
PSB 4600
Precaution
9.4
Capacitances
________________________________________
Conditions
TA = 25 °C, VDD5 = 5 V ± 10%, VDD3 = 3.3 V ± 10%, VSS = 0 V, unmeasured pins
grounded.
________________________________________
Capacitances
Parameter
Symbol
Limit Values
min.
Unit
Rem.
max.
Input Capacitance
CIN
7
pF
I/O Capacitance
CI/O
7
pF
________________________________________
Semiconductor Group
9-6
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
10 Configuration Space Register of the PITA
________________________________________
Overview
Page
Description of the Register Types
10-2
Configuration Space Register
10-3
Registers which do not occur elsewhere in the Data Sheet
10-13
________________________________________
Semiconductor Group
10-1
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
10.1
Description of the Register Types
________________________________________
Type
Description
R
read only
• these bits are initialized by pinstrapping during PCI reset
H
read only
• hardwired
RC
read clear
• these bits are set by the internal logic
• these bits can be read out and reset by writing logical “1”
to them
• writing logical “0” doesn’t influence the states of these bits
RW
read write
• these bits can be read out and written via the PCI bus
EW
EEPROM write
• these bits can be set by an external EEPROM after a
system reset
________________________________________
Semiconductor Group
10-2
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
10.2
Configuration Space Register
________________________________________
00h
Ad.
Bit
Type
Default
Value
Register Name
Page
00h
31:16
H/EW
2104h
Device ID
10-13
15:0
H/EW
110Ah
Vendor ID of Siemens AG.
10-13
________________________________________
04h
Ad.
Bit
04h
31:0
Type
Default
Value
Register Name
Page
0290
0000h
PCI Status Register
10-13
31
RC
0b
Parity Error Detected
10-13
30
RC
0b
System Error Signaled
5-58
29
RC
0b
Master Abort Detected
5-58
28
RC
0b
Target Abort Detected
5-58
27
RC
0b
Target Abort Signaled
5-58
26:25
H
01b
DEVSEL Timing
4-19
4-21
24
RC
0b
Data Parity Error
Reported
10-13
23
H
1b
Fast Back-to-Back
Capability
4-23
22
H
0b
User Defined Functions
10-13
21
H
0b
66 MHz Capability
10-13
Semiconductor Group
10-3
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
04h (cont’d)
Ad.
Bit
Type
Default
Value
Register Name
Page
20
H/EW
1b
Capabilities
10-13
19:16
H
0000b
Reserved
10-13
Command Register
10-13
15:0
15:10
H
000000b
Reserved
10-13
9
H
0b
Fast Back-to-Back Enable
4-23
8
RW
0b
System Error Enable
5-58
7
H
0b
Address/Data Stepping
Enable (not used)
10-13
6
RW
0b
Parity Error Response
10-13
5:3
H
000b
The PITA does not
support the Special Cycle
Command.
10-13
2
RW
0b
Master Enable
5-58
1
RW
0b
Memory Access Enable
4-8
0
H
0b
I/O Access Enable
10-13
________________________________________
08h
Ad.
Bit
Type
Default
Value
Register Name
Page
08h
31:8
H/EW
028000h
Class Code/PCI network
device
10-16
7:0
H
01h
Revision ID
10-16
________________________________________
Semiconductor Group
10-4
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
________________________________________
0Ch
Ad.
Bit
Type
Default
Value
Register Name
Page
0Ch
31:24
H
00h
BIST
10-17
23:16
H
00h
Header Type
10-17
15:8
H
00h
Master Latency Timer
10-17
7:0
H
00h
Cache Line Size
10-17
________________________________________
10h
Ad.
Bit
10h
31:0
31:12
11:0
Type
Default
Value
Register Name
Page
00000000h
Base Register 0
4-8
RW
H
________________________________________
14h
Ad.
Bit
14h
31:0
31:12
11:0
Type
Default
Value
Register Name
Page
00000000h
Base Register 1
4-9
RW
H
________________________________________
Semiconductor Group
10-5
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
________________________________________
18h
Ad.
Bit
Type
Default
Value
Register Name
18h
31:0
H
00000000h
Base Address Register 2
(not used)
Page
4-9
________________________________________
1Ch
Ad.
Bit
Type
Default
Value
Register Name
1Ch
31:0
H
00000000h
Base Address Register 3
(not used)
Page
4-9
________________________________________
20h
Ad.
Bit
Type
Default
Value
Register Name
Page
20h
31:0
H
00000000h
Base Address Register 4
(not used)
4-10
________________________________________
24h
Ad.
Bit
Type
Default
Value
Register Name
Page
24h
31:0
H
00000000h
Base Address Register 5
(not used)
4-10
________________________________________
Semiconductor Group
10-6
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
________________________________________
28h
Ad.
Bit
28h
31:0
Type
Default
Value
Register Name
Page
0000 02C0
CardBus CIS Pointer
4-11
31:28
H
0000b
ROM Image Number
4-11
27:3
H
000058h
Address Space Offset
4-11
2:0
H
000b
Address Space Indicator
4-12
________________________________________
2Ch
Ad.
Bit
Type
Default
Value
Register Name
Page
2Ch
31:20
H/EW
000h
Subsystem Device ID
4-12
19:16
R
or
EW
pinstrap
value or
EEPROMvalue
15:0
R/EW
pinstrap
value
or
EEPROMvalue
Subsystem Vendor ID
4-12
________________________________________
Semiconductor Group
10-7
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
________________________________________
30h
Ad.
Bit
Type
Default
Value
Register Name
Page
30h
31:0
H
00000000h
Reserved
10-18
________________________________________
34h
Ad.
Bit
Type
Default
Value
Register Name
Page
34h
31:8
H
00h
Reserved
4-28
7:0
H
40h
Capabilities Pointer
4-28
________________________________________
38h
Ad.
Bit
Type
Default
Value
Register Name
Page
38h
31:0
H
00000000h
Reserved
10-18
________________________________________
3Ch
Ad.
Bit
Type
Default
Value
Register Name
Page
3Ch
31:24
H
00h
Max_Lat
10-19
23:16
H
00h
Min_Gnt
10-19
Semiconductor Group
10-8
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
3Ch (cont’d)
Ad.
Bit
Type
Default
Value
Register Name
Page
15:8
H
01h
Interrupt pin
10-19
7:0
RW
FFh
Interrupt Line
10-19
________________________________________
40h
Ad.
Bit
40h
31:0
Type
Default
Value
Register Name
Page
1229 0001
Power Management
Capabilities (PMC)
4-28
PME_Support
4-28
31:30
H
00b
29:28
H/EW
01b
27
H
0b
26
H/EW
0b
D2_Support
4-28
25
H/EW
1b
D1_Support
4-28
24:22
H
000b
Reserved
4-28
21
H
1b
DSI
4-28
20
H
0b
Reserved
4-28
19
H/EW
1b
PME Clock
4-28
18:16
H
001b
Version
The value 001b indicates
that the device complies
with the Revision 1.0 of the
PCI Power Management
Interface Specification.
4-28
15:8
H
00h
Next Item Ptr
4-28
Semiconductor Group
10-9
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
40h (cont’d)
Ad.
Bit
Type
Default
Value
Register Name
Page
7:0
H
01h
Capability ID
4-28
________________________________________
44h
Ad.
Bit
Type
Default
Value
Register Name
Page
44h
31:24
H
00h
DATA Register
4-32
23:16
H
00h
PMCSR_BSE Bridge
Support Extensions
4-32
15:8
H
00h
Power Management
Control/Status register
4-32
15
RC
0b
PME Status
4-32
14:13
H
00b
Data Scale
4-32
12:9
RW
0h
Data Select
4-32
8
RW
0b
PME_En
4-32
7:2
H
00h
Reserved
4-32
1:0
RW
00b
Power State
4-32
________________________________________
48h
Ad.
Bit
48h
31:0
Semiconductor Group
Type
Default
Value
10-10
Register Name1
Page
Power Data Register 1
10-20
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
48h (cont’d)
Ad.
Bit
Type
Default
Value
Register Name1
Page
31:30
H
00b
Reserved
10-20
29:28
H/EW
00b
Data_Scale in
Data_Select = 2
10-20
27:20
H/EW
00h
DATA in Data_Select = 2
10-20
19:18
H/EW
00b
Data_Scale in
Data_Select = 1
10-20
17:10
H/EW
00h
DATA in Data_Select = 1
10-20
9:8
H/EW
00b
Data_Scale in
Data_Select = 0
10-20
7:0
H/EW
00h
DATA in Data_Select = 0
10-20
________________________________________
4Ch
Ad.
Bit
4Ch
31:0
Type
Default
Value
Register Name
Page
Power Data Register 2
10-22
31:30
H
00b
Reserved
10-22
29:28
H/EW
00b
Data_Scale in
Data_Select = 5
10-22
27:20
H/EW
00h
DATA in Data_Select = 5
10-22
19:18
H/EW
00b
Data_Scale in
Data_Select = 4
10-22
17:10
H/EW
00h
DATA in Data_Select = 4
10-22
9:8
H/EW
00b
Data_Scale in
Data_Select = 3
10-22
Semiconductor Group
10-11
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
4Ch (cont’d)
Ad.
Bit
Type
Default
Value
Register Name
Page
7:0
H/EW
00h
DATA in Data_Select = 3
10-22
________________________________________
50h
Ad.
Bit
50h
31:0
Type
Default
Value
Register Name
Page
Power Data Register 3
10-24
31:20
H
000h
Reserved
10-24
19:18
H/EW
00b
Data_Scale in
Data_Select = 7
10-24
17:10
H/EW
00h
Data_Value in
Data_Select = 7
10-24
9:8
H/EW
00b
Data_Scale in
Data_Select = 6
10-24
7:0
H/EW
00h
Data_Value in
Data_Select = 6
10-24
________________________________________
54h
Ad.
Bit
Type
Default
Value
Register Name
Page
54h
31:0
H
00h
CardBus CIS
10-25
________________________________________
Semiconductor Group
10-12
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
10.3
Registers which do not occur elsewhere in the Data
Sheet
________________________________________
00h
Bit 31:16
Device ID
Type
H or EW
Default Value
2104h
Description
Identifies the PITA within all PCI devices from Siemens
Semiconductors.
Bit 15:0
Vendor ID
Type
H or EW
Default Value
110Ah
Description
110A is the Vendor ID of Siemens AG.
________________________________________
04h
Bit 31:0
PCI Status Register
Default Value
02900000h
Bit 31
Parity_Error_Detected
Type
RC
Default Value
0b
Description
This bit is set, if a parity error is detected during a transaction
with the PITA. This is done independently from the status of
the ‘Parity Error Response’ bit.
Semiconductor Group
10-13
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
04h (cont’d)
Bit 24
Data_Parity_Error_Reported
Type
RC
Default Value
0b
Description
The PCI Master asserts this bit if it detects the PERR signal
on the PCI bus asserted during a PCI transaction initiated by
itself.
Bit 22
User_Defined_Functions
Type
H
Default Value
0b
Description
The PITA has no user defined functions.
Bit 21
66_MHz_Capability
Type
H
Default Value
0b
Description
The PITA is not a 66 MHz device (0 - 33 MHz supported.)
Bit 20
Capabilities
Type
H or EW
Default Value
1b
Description
If this bit is set, the PCI device has additional capabilities
defined in the PCI Configuration Space Header. Additional
capabilities can be found in the Cap_Ptr under address 34h.
Semiconductor Group
10-14
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
04h (cont’d)
Bit 19:16
Reserved
Type
H
Default Value
0000b
Description
Bit 15:0
Command Register
Bit 15:10
Reserved
Type
H
Default Value
000000b
Description
Bit 7
Address/Data_Stepping_Enable
Type
H
Default Value
0b
Description
not used
Bit 6
Parity_Error_Response
Type
RW
Default Value
0b
Description
If this bit is set to ‘1’, the PCI interface reports data parity
errors by asserting the PERR signal.
Semiconductor Group
10-15
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
04h (cont’d)
Bit 5:3
Type
RW
Default Value
0b
Description
The PITA does not support the Special Cycle Command.
The PITA does not generate Memory Write and invalidate
transactions.
The PITA does not support VGA Palette snooping.
Bit 0
I/O_Access_Enable
Type
H
Default Value
0b
Description
The PCI interface does not support I/O commands.
________________________________________
08h
Bit 31:8
Class_Code
Type
H or EW
Default Value
028 000h
Description
PCI network device
Bit 7:0
Revision ID
Type
H
Default Value
01h
Description
Revision of the PCI device
________________________________________
Semiconductor Group
10-16
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
________________________________________
0Ch
Bit 31:24
BIST
Type
H
Default Value
00h
Description
The PITA has no built-in self test.
Bit 23:16
Header_Type
Type
H
Default Value
00h
Description
Bit 15:8
Master_Latency_Timer
Type
H
Default Value
00h
Description
Unused
Bit 7:0
Cache_Line_Size
Type
H
Default Value
00h
Description
The PITA does not support the cache line size register
because it supports only single data transactions.
________________________________________
Semiconductor Group
10-17
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
________________________________________
30h
Bit 31:0
Reserved
Type
H
Default Value
0000 0000h
Description
Reserved
________________________________________
38h
Bit 31:0
Reserved
Type
H
Default Value
0000 0000h
Description
________________________________________
Semiconductor Group
10-18
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
________________________________________
3Ch
Bit 31:24
Max_Lat
Type
H
Default Value
00h
Description
Set to ’0’ because only single data transactions are
supported.
Bit 23:16
Mint_Gnt
Type
H
Default Value
00h
Description
Set to ’0’ because only single data transactions are
supported.
Bit 15:8
Interrupt_Pin
Type
H
Default Value
01h
Description
As a single function device, the PITA uses the INTA signal.
Bit 7:0
Interrupt_Line
Type
RW
Default Value
FFh
Description
These Bits show the interrupt line which is used by this
system. For a x86 system the value FF means unknown.
These registers are written during the initialization of the
operating system.
________________________________________
Semiconductor Group
10-19
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
________________________________________
48h
Bit 31:0
Power Data Register 1
Bit 31:30
Reserved
Type
H
Default Value
00b
Description
Reserved
Bit 29:28
Data_Scale in Data_Select=2
Type
H or EW
Default Value
00b
Description
This register is mapped to the Data_Scale field if
Data_Select_field is set to 2.
Bit 27:20
DATA in Data_Select=2
Type
H or EW
Default Value
00h
Description
This register is mapped to the DATA register if the
Data_Select field is set to 2
Semiconductor Group
10-20
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
48h (cont’d)
Bit 19:18
Data_Scale in Data_Select=1
Type
H or EW
Default Value
00b
Description
This register is mapped to the Data_Scale field if
Data_Select field is set to1.
Bit 17:10
DATA in Data_Select=1
Type
H or EW
Default Value
00h
Description
This register is mapped to the DATA register if the
Data_Select field is set to 1.
Bit 9:8
Data_Scale in Data_Select=0
Type
H or EW
Default Value
00b
Description
This register is mapped to the Data_Scale field if
Data_Select field is set to 0.
Bit 7:0
DATA in Data_Select=0
Type
H or EW
Default Value
00h
Description
This register is mapped to the DATA register if the
Data_Select field is set to 0.
________________________________________
Semiconductor Group
10-21
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
________________________________________
4Ch
Bit 31:0
Power Data Register 2
Bit 31:30
Reserved
Type
H
Default Value
00b
Description
Reserved
Bit 29:28
Data_Scale in Data_Select=5
Type
H or EW
Default Value
00b
Description
This register is mapped to the Data_Scale field if
Data_Select_field is set to 5.
Bit 27:20
DATA in Data_Select=5
Type
H or EW
Default Value
00h
Description
This register is mapped to the DATA register if the
Data_Select field is set to 5.
Semiconductor Group
10-22
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
4Ch (cont’d)
Bit 19:18
Data_Scale in Data_Select=4
Type
H or EW
Default Value
00b
Description
This register is mapped to the Data_Scale field if
Data_Select field is set to 4
Bit 17:10
DATA in Data_Select=4
Type
H or EW
Default Value
00h
Description
This register is mapped to the DATA register if the
Data_Select field is set to 4.
Bit 9:8
Data_Scale in Data_Select=3
Type
H or EW
Default Value
00b
Description
This register is mapped to the Data_Scale field if
Data_Select field is set to 3-
Bit 7:0
DATA in Data_Select=3
Type
H or EW
Default Value
00h
Description
This register is mapped to the DATA register if the
Data_Select field is set to 3.
________________________________________
Semiconductor Group
10-23
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
________________________________________
50h
Bit 31:0
Power Data Register 3
Bit 31:30
Reserved
Type
H
Default Value
00b
Description
Reserved
Bit 19:18
Data_Scale in Data_Select=7
Type
H or EW
Default Value
00b
Description
This register is mapped to the Data_Scale field if
Data_Select field is set to 7.
Bit 17:10
DATA in Data_Select=7
Type
H or EW
Default Value
00h
Description
This register is mapped to the DATA register if the
Data_Select field is set to 7.
Semiconductor Group
10-24
Preliminary Data Sheet 12.98
PSB 4600
Configuration Space Register of the PITA
50h (cont’d)
Bit 9:8
Data_Scale in Data_Select=6
Type
H or EW
Default Value
00b
Description
This register is mapped to the Data_Scale field if
Data_Select field is set to 6.
Bit 7:0
DATA in Data_Select=6
Type
H or EW
Default Value
00h
Description
This register is mapped to the DATA register if the
Data_Select field is set to 6.
________________________________________
54h
Bit 31:0
Cardbus_CIS
Type
H
Default Value
00h
Description
Default Value: 00h
Up from this register, the Cardbus CIS structure is
implemented (not supported in this version of PITA)
________________________________________
Semiconductor Group
10-25
Preliminary Data Sheet 12.98
PSB 4600
Internal Register of the PITA
11 Internal Register of the PITA
________________________________________
Overview
Page
Description of the Register Types
11-2
Internal Register
11-3
Registers which do not occur elsewhere in the Data Sheet
11-10
________________________________________
Semiconductor Group
11-1
Preliminary Data Sheet 12.98
PSB 4600
Internal Register of the PITA
11.1
Description of the Register Types
________________________________________
Type
Description
R
read only
• these bits are initialized by pinstrapping during PCI reset
H
read only
• hardwired
RC
read clear
• these bits are set by the internal logic
• these bits can be read out and reset by writing logical “1”
to them
• writing logical “0” doesn’t influence the states of these bits
RW
read write
• these bits can be read out and written via the PCI bus
EW
EEPROM write
• these bits can be set by an external EEPROM after a
system reset
________________________________________
Semiconductor Group
11-2
Preliminary Data Sheet 12.98
PSB 4600
Internal Register of the PITA
11.2
Internal Register
________________________________________
00h
Ad.
Bit
00h
31:0
Type
Default
Value
Register Name
Page
00000000h
ICR - Interrupt Control
Register
11-10
31:29
H
000b
Reserved
11-10
28
RW
0b
EEPROM_Control_Int_En
5-90
27
RW
0b
Retry_Counter_Down_
Int_En
4-35
26
RW
0b
FIFO_Overflow_Empty_
Int_En
5-10
25
RW
0b
DMA_Write_Counter_
Overflow_Int_En
5-10
24
RW
0b
DMA_Write_Counter_Int_
En
5-10
23:18
H
000000b
Reserved
11-10
17
RW
0b
INT0_En
11-10
16
RW
0b
INT1_ En
11-10
15:13
H
000b
Reserved
11-10
12
RC
0b
EEPROM_Control_Int
5-90
11
RC
0b
Retry_Counter_Int
4-35
10
RC
0b
FIFO_Overflow_Empty_
Int
5-10
9
RC
0b
DMA_Write_Counter_
Overflow_Int
5-10
8
RC
0b
DMA_Write_Counter_Int
5-10
Semiconductor Group
11-3
Preliminary Data Sheet 12.98
PSB 4600
Internal Register of the PITA
00h (cont’d)
Ad.
Bit
Type
Default
Value
Register Name
Page
7:6
H
0b
Reserved
11-10
5
RC
0b
GP3_INT
5-69
4
RC
0b
GP2_INT
5-69
3
RC
0b
GP1_INT
5-69
2
RC
0b
GP0_INT
5-69
1
RC
0b
INT0
11-10
0
RC
0b
INT1
11-10
________________________________________
04h
Ad.
Bit
04h
31:0
Type
Default
Value
Register Name
Page
00000000h
DMA Control Register
5-11
31:09
H
0000000h
Reserved
5-11
8
RW
0b
DMA Start
5-11
7:6
H
00b
Reserved
5-11
5:0
RW
000000b
DMA Select - all modes
IOM-2 Mode 1
IOM-2 Mode 2
IOM-2 Mode 3
Single Modem Mode V2.1
Single Modem Mode V3.X
Dual Modem+Voice Mode
5-11
5-16
5-20
5-23
5-31
5-36
5-44
Semiconductor Group
11-4
Preliminary Data Sheet 12.98
PSB 4600
Internal Register of the PITA
________________________________________
08h
Ad.
Bit
Type
Default
Value
Register Name
Page
08h
31:12
RW
00000h
Circular Buffer Start
Address
5-13
11:0
H
000h
________________________________________
0Ch
Ad.
Bit
Type
Default
Value
Register Name
Page
0Ch
31:02
R
00000000h
Actual Circular Buffer
Pointer
5-13
1:0
H
00b
________________________________________
10h
Ad.
Bit
10h
31:0
Type
Default
Value
Register Name
Page
00000000h
ALIS Command Register 1
5-36
31:25
H
00h
Reserved
5-36
24
RW
0b
New_ALIS_Command_1
5-36
23:16
RW
00h
ALIS_Received_Data_1
5-36
15:8
RW
00h
ALIS_Command_1
5-36
7:0
RW
0b
ALIS_Transmit_Data_1
5-36
________________________________________
Semiconductor Group
11-5
Preliminary Data Sheet 12.98
PSB 4600
Internal Register of the PITA
________________________________________
14h
Ad.
Bit
14h
31:0
Type
Default
Value
Register Name
Page
00000000h
ALIS Command Register 2
5-39
32:25
H
000h
Reserved
5-39
24
RW
0b
New_ALIS_Command_2
5-39
23:16
RW
00h
ALIS_Received_Data_2
5-39
15:8
RW
00h
ALIS_Command_2
5-39
7:0
RW
00h
ALIS_Transmit_Data_2
5-39
________________________________________
18h
Ad.
Bit
18h
31:0
Type
Default
Value
Register Name
Page
00000000h
GP I/O Interface Control
Register
5-70
31:28
H
0h
Reserved
5-70
27
RW
0b
GP3_Int_En
5-70
26
RW
0b
GP2_Int_En
5-70
25
RW
0b
GP1_Int_En
5-70
24
RW
0b
GP0_Int_En
5-70
23:20
H
0000b
Reserved
5-70
19
RW
0b
GP3_Out_En
5-70
18
RW
0b
GP2_Out_En
5-70
Semiconductor Group
11-6
Preliminary Data Sheet 12.98
PSB 4600
Internal Register of the PITA
18h (cont’d)
Ad.
Bit
Type
Default
Value
Register Name
Page
17
RW
0b
GP1_Out_En
5-70
16
RW
0b
GP0_Out_En
5-70
15:12
H
0000b
Reserved
5-70
11
R
0b
GP3_IN
5-70
10
R
0b
GP2_IN
5-70
9
R
0b
GP1_IN
5-70
8
R
0b
GP0_IN
5-70
7:4
H
0000b
Reserved
5-70
3
RW
0b
GP3_OUT
5-70
2
RW
0b
GP2_OUT
5-70
1
RW
0b
GP1_OUT
5-70
0
RW
0b
GP0_OUT
5-70
________________________________________
1Ch
Ad.
Bit
1Ch
31:0
Type
Default
Value
Register Name
Page
00000000h
MISC - Miscellaneous
Register
5-27
31
RW
0b
IOM B1 Masking
5-27
30
RW
0b
IOM B2 Masking
5-27
29
RW
0b
IOM MON0/IC1 Masking
5-27
28
RW
0b
IOM D+C/I0+MR+MX /
IC2 Masking
5-27
Semiconductor Group
11-7
Preliminary Data Sheet 12.98
PSB 4600
Internal Register of the PITA
1Ch (cont’d)
Ad.
Bit
Type
Default
Value
Register Name
Page
27
RW
1b
Serial Interface Buffer
Mode
11-12
26
RW
0b
Parallel Interface Mode
5-47
25
RW
0b
Soft reset Serial Interface
11-12
24
RW
0b
Soft reset Parallel
Interface
5-47
23:16
RW
00h
Retry Count Register
4-36
15:12
H
0000b
Reserved
11-12
11:0
RW
0000h
DMA Write Count Register
5-14
________________________________________
20h
Ad.
Bit
20h
31:0
Type
Default
Value
Register Name
00000000h
Serial Clock Select
Register
Page
31:2
H
00000000h
Reserved
1
RW
0b
DCL_Out_En
5-17
5-20
5-23
5-32
5-41
0
RW
0b
Serial_Clock_Sel
5-17
5-20
5-23
5-32
5-41
Semiconductor Group
11-8
Preliminary Data Sheet 12.98
PSB 4600
Internal Register of the PITA
________________________________________
24h
Ad.
Bit
24h
31:0
Type
Default
Value
Register Name
Page
00000000h
EEPROM Control Register
5-90
31:25
H
0000h
Reserved
5-90
24
RW
0b
EEPROM Start
5-90
23:16
RW
00h
EEPROM Command
5-90
15:8
RW
00h
EEPROM Byte Address
5-90
7:0
RW
00h
EEPROM Data
5-90
________________________________________
28h
Ad.
Bit
28h
31:0
Type
Default
Value
Register Name
Page
00000000h
DMA TEST Register
11-12
31:01
H
00000000h
Reserved
11-12
0
RW
0b
Loop_Back_Mode
5-46
________________________________________
Semiconductor Group
11-9
Preliminary Data Sheet 12.98
PSB 4600
Internal Register of the PITA
11.3
Registers which do not occur elsewhere in the Data
Sheet
________________________________________
00h
Bit 31:0
ICR - Interrupt Control Register
Default Value
00000000h
Description
The interrupt enable bits for GP3-0 are placed in the GP I/O
Interface Control Register.
All interrupt enables are high active:
Int_En=’0’ -> corresponding interrupt (bit) is disabled
Int_En=’1’ -> corresponding interrupt (bit) is enables
Bit 31:29
Reserved
Type
H
Default Value
000b
Description
Reserved
Bit 23:18
Reserved
Type
H
Default Value
000000b
Description
Reserved
Bit 17
INT0_En
Type
RW
Default Value
0b
Description
Enable for the INT0 interrupt bit.
Semiconductor Group
11-10
Preliminary Data Sheet 12.98
PSB 4600
Internal Register of the PITA
00h (cont’d)
Bit 16
INT_En
Type
RW
Default Value
0b
Description
Enable for the INT1 interrupt bit.
Bit 23:18
Reserved
Type
H
Default Value
000000b
Description
Reserved
Bit 1
INT0
Type
RC
Default Value
0b
Description
An interrupt is detected on pin INT0 (low active).
Bit 0
INT1
Type
RC
Default Value
0b
Description
An interrupt is detected on pin INT1 (low active).
________________________________________
Semiconductor Group
11-11
Preliminary Data Sheet 12.98
PSB 4600
Internal Register of the PITA
________________________________________
1Ch
Bit 27
Serial Interface Buffer Mode
Type
RW
Default Value
1b
Description
Bit 27=’0’: The TXD pin is configured as PUSH/PULL output
pin.
Bit 27=’1’: The TXD pin is configured as OPEN DRAIN
output pin.
Bit 25
Soft Reset Serial Interface
Type
RW
Default Value
0b
Description
Bit 25=’0’: Activates the low active reset signal SRST to the
application.
Bit 25=’1’: Deactivates the reset signal SRST to the
application. Before asserting this bit the DMA_Start bit has
to be reset.
________________________________________
28h
Bit 31:0
DMA Test Register
Default Value
00000000h
Bit 31:1
Reserved
Type
H
Default Value
00000000h
Description
Reserved
Semiconductor Group
11-12
Preliminary Data Sheet 12.98
PSB 4600
Abbreviations
12 Abbreviations
AC
Alternating Current.
A/D
Analog to digital.
ADC
Analog to digital converter.
ALE
Address latch enable.
ALIS
Analog Line Interface Solution. Chip set consisting of PSB4595 and
PSB4596.
DC
Direct Current.
DCL
Double Bit Clock. (In this context, only in the IOM-2 modes of the
serial interface of the PITA, single bit in all other modes).
DMA
Direct Memory Access.
DD
Data Downstream.
DU
Data Upstream.
EEPROM =
E2PROM
Electrically erasable programmable read only memory.
FIFO
RX FIFO
TX FIFO
First in first out.
FSC
Frame Sync.
I/O
In/out.
IOM
ISDN Oriented Modular.
ISDN
Integrated Services Digital Network.
MSB
Most Significant Bit.
PITA
PCI Interface for Telephony/Data Applications.
PCI
Peripheral Component Interconnect.
RXD
Receive Direction.
TXD
Transmit Direction.
Semiconductor Group
13
Preliminary Data Sheet 12.98
PSB 4600
Index
13 Index
Numerics
3PAC
2-2
A
Absolute Maximum Ratings 9-2
AC Characteristics 9-5
ALE after internal Softreset 5-51
ALE after setting the Parallel Interface
Mode Bit 5-52
ALE after System Reset 5-50
ALIS V2.1 1-2
Connection to the Serial Control
Interface 5-87
PITA Configuration after a System
Reset 5-31
ALIS V3.X 1-2
PITA Configuration after a System
Reset 5-35
ALIS-A 2-2
ALIS-D 2-2
B
Base Address Register 4-7
Structure of the Address Space
4-7
C
Capacitances 9-6
Configuration Space Register
00h 10-3
04h 10-3
08h 10-4
0Ch 10-5
10h 10-5
14h 10-5
18h 10-6
1Ch 10-6
20h 10-6
24h 10-6
28h 10-7
2Ch 10-7
Semiconductor Group
10-3
13-1
30h 10-8
34h 10-8
38h 10-8
3Ch 10-8
40h 10-9
44h 10-10
48h 10-10
50h 10-12
54h 10-12
Base Address Register 0
10h 4-8
Base Address Register 1
14h 4-9
Base Address Register 2
18h 4-9
Base Address Register 3
1Ch 4-9
Base Address Register 4
20h 4-10
Base Address Register 5
28h 4-10
Base Address Registert
04h 4-8
Burst Read
04h 4-19
Burst Write
04h 4-21
Disconnect with Target Abort
04h 5-58
do not occur in the data sheet
00h 10-13
04h 10-13
08h 10-16
0Ch 10-17
30h 10-18
38h 10-8, 10-18
3Ch 10-19
48h 10-20
4Ch 10-22
50h 10-24
Preliminary Data Sheet 12.98
PSB 4600
Index
54h 10-25
Fast Back to Back
04h 4-23
PCI Configuration Space
Special Qualities
28h 4-11
2Ch 4-12
Power Management
34h 4-28
40h 4-28
44h 4-32
D
DC Characteristics 9-3
DMA Algorithm
Function 5-6
DMA Controller 5-4
Function 5-5
DMA Start bit 5-7
DMA Write Counter 5-6
Dual Modem/Modem+Voice Mode
5-42
E
Electrical Characteristics
Power Management States
4-27
G
General Purpose I/O Interface
Input Mode 5-76
Interrupt Mode 5-80
Output Mode 5-78
Pinning 7-7
5-65
I
IEC-Q TE 1-2, 2-2
Interfaces
General Purpose I/O Interface 5-65
Parallel Interface 5-47
Serial DMA Interface 5-2
SPI EEPROM Interface 5-84
Internal Register
00h 10-5, 11-3
04h 11-4
Semiconductor Group
13-2
08h 11-5
0Ch 11-5
10h 11-5
14h 11-6
18h 11-6
1Ch 11-7
20h 11-8
24h 11-9
28h 11-9
4Ch 10-11
ALIS
10h 5-36
14h 5-39
DMA Controller
00h 5-10
04h
5-11, 5-13, 5-31, 5-36, 538, 5-44
08h 5-13
0Ch 5-13, 5-14, 5-46, 5-47, 5-70
1Ch 5-14
do not occur in the data sheet
00h 11-10
1Ch 11-12
28h 11-12
GP I/O Interface
00h 5-69
18h 5-70
IOM-2 Mode 1
04h 5-16, 5-20, 5-23
IOM-2 Modes
1Ch 5-27
Loopback Mode
28h 5-46
Parallel Interface
1Ch 5-47
Retry Counter
00h 4-35
1Ch 4-36
Single Modem Mode V2.1
20h 5-41
Single Modem Mode v2.1
20h 5-17, 5-20, 5-23, 5-32
SPI EEPROM Interface
Preliminary Data Sheet 12.98
PSB 4600
Index
00h 5-36, 5-39, 5-90
24h 5-90
Interrupt Control Register 4-35
Interrupts
FIFO Overflow/Empty 5-9
Write Counter 5-9
IOM-2 Mode 1 5-15
IOM-2 Mode 2 5-18
IOM-2 Mode 3 5-21
IOM-2 Modes
General Description 5-24
Masking of IOM-2 Timeslots 5-26
Selection of IOM-2 Timeslots 5-24
IPAC 1-2, 2-1
ISAC 1-2
ISAR 1-2, 2-3
ISDN
Modem using ISAR 2-3
-S with IPAC 2-1
-U with 3PAC and IEC-Q TE 2-2
L
Loopback Mode
5-45
M
Multiplexed Mode
Read Transaction 5-56
Multiplexed Mode Write Transaction 5-55
N
Non Multiplexed Mode
Read Transaction 5-54
Write Transaction 5-53
P
Parallel Interface 5-47
Pinning 7-4
PC98 1-1
PCI Bus
Pinning 7-3
PCI Commands 4-14
PCI Configuration Space
Access to the 4-6
Semiconductor Group
4-2
Construction of 4-4
PCI Master Controller
Supported PCI Commands 4-14
PCI Master Target Controller 4-13
PCI Target Controller
Supported PCI Commands 4-14
Pinning
Description of PIN Types 7-2
GP I/O Interface 7-7
Parallel Interfaces 7-4
Power Supply 7-9
Serial Interface 7-6
Special EEPROM Signals 7-8
Test IF 7-8
Pinstrapping 6-1
Power Management 4-24
Power Management State
D0 4-25
D1 4-25
D2 4-25
D3 4-26
D3cold 4-26
D3hot 4-26
Power Management States
Electrical Characteristics 4-27
Power Supply
Pinning 7-9
S
Serial DMA Interface 5-2
Serial Interface
Pinning 7-6
Single Modem Mode V2.1 5-29
Configuration after a System/Soft
Reset 5-30
Single Modem Mode V3.X 5-33
Configuration after a System/Soft
Reset 5-35
Software Modem
using ALIS-A and ALIS-D 2-2
Special EEPROM Signals
Pinning 7-8
SPI EEPROM Interface 5-84
13-3
Preliminary Data Sheet 12.98
PSB 4600
Index
After finishing the transaction 5-87
Starting a read or write transaction 586
T
Transaction Disconnect 5-57
Transaction Termination 5-60
Transaction Disconnect 5-57
Transaction Termination with Retry 5-60
Test IF
Pinning 7-8
Timing 5-57
Timing Diagram
ALE after internal Softreset 5-51
ALE after setting the Parallel Interface
Mode Bit 5-52
ALE after System Reset 5-50
Burst Read 4-18
Burst Write 4-20
Dual Modem/Modem+Voice Mode
5-43
Fast Back to Back 4-22
GP I/O Interface
ALIS V2.1 Read 5-83
ALIS V2.1 Write 5-83
Input Mode 5-76
Interrupt Mode 5-80
Output Mode 5-79
IOM-2 all Modes 5-24
IOM-2 Mode 1 5-16
IOM-2 Mode 2 5-19
IOM-2 Mode 3 5-22
Loopback Mode 5-45
Multiplexed Mode Read 5-56
Multiplexed Mode Write 5-55
Non Multiplexed Mode Read 5-54
Non Multiplexed Mode Write 5-53
Parallel Interface
Multiplexed Address 5-62
Non Mulitplexed Address 5-63
Read 5-62
Write 5-62
Single Data Read 4-16
Single Data Write 4-17
Single Modem Mode V2.1 5-29
Single Modem Mode V3.X 5-34
SPI EEPROM Interface 5-88
Semiconductor Group
13-4
Preliminary Data Sheet 12.98