IDT IDT7M1003S35C

128K x 8
64K x 8
CMOS DUAL-PORT
STATIC RAM MODULE

Integrated Device Technology, Inc.
IDT7M1001
IDT7M1003
FEATURES
DESCRIPTION:
• High-density 1M/512K CMOS Dual-Port Static RAM
module
• Fast access times:
—Commercial 35, 40ns
—Military 40, 50ns
• Fully asynchronous read/write operation from either port
• Full on-chip hardware support of semaphore signaling
between ports
• Surface mounted LCC (leadless chip carriers) components on a 64-pin sidebraze DIP (Dual In-line Package)
• Multiple Vcc and GND pins for maximum noise immunity
• Single 5V (±10%) power supply
• Input/outputs directly TTL-compatible
The IDT7M1001/IDT7M1003 is a 128K x 8/64K x 8 highspeed CMOS Dual-Port Static RAM module constructed on a
multilayer ceramic substrate using eight IDT7006 (16K x 8)
Dual-Port RAMs and two IDT FCT138 decoders or depopulated using only four IDT7006s and two decoders.
This module provides two independent ports with separate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory. System performance is enhanced by facilitating
port-to-port communication via semaphore (SEM) “handshake” signaling. The IDT7M1001/1003 module is designed
to be used as stand-alone Dual-Port RAM where on-chip
hardware port arbitration is not needed. It is the users responsibility to ensure data integrity when simultaneously
accessing the same memory location from both ports.
The IDT7M1001/1003 module is packaged on a multilayer
co-fired ceramic 64-pin DIP (Dual In-line Package) with dimensions of only 3.2" x 0.62" x 0.38". Maximum access times
as fast as 35ns over the commercial temperature range are
available.
All inputs and outputs of the IDT7M1001/1003 are TTLcompatible and operate from a single 5V supply. Fully asynchronous circuitry is used, requiring no clocks or refreshing for
operation of the module.
All IDT military module semiconductor components are
manufacured in compliance with the latest revision of MILSTD-883, Class B, making them ideally suited to applications
demanding the highest level of performance and reliability.
PIN CONFIGURATION(1)
VCC
R/WL
OEL
CSL
SEML
A0L
A1L
GND
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
A15L
A16L
I/O 0L
I/O 1L
I/O 2L
I/O 3L
I/O 4L
I/O 5L
I/O 6L
I/O 7L
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
R/WR
OER
CSR
SEMR
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
A16R
GND
I/O 0R
I/O 1R
I/O 2R
I/O 3R
I/O 4R
I/O 5R
I/O 6R
I/O 7R
VCC
PIN NAMES
Left Port
Right Port
A (0–16)L
A (0–16)R
Address Inputs
I/O (0–7)L
I/O (0–7)R
Data Inputs/Outputs
R/WL
R/WR
Read/Write Enables
CSL
CSR
Chip Select
OEL
OER
Output Enable
SEMR
Semaphore Control
SEML
2804 drw 01
Description
VCC
Power
GND
Ground
2804 tbl 01
DIP
TOP VIEW
NOTE:
1. For the IDT7M1003 (64K x 8) version, Pins 23 and 43 must be connected
to GND for proper operation of the module.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1995 Integrated Device Technology, Inc.
MARCH 1995
DSC-7066/5
7.5
1
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
7M1001
7006
7006
7025
7006
7006
R_I/O0-7
CS L
CS R
CS L
CSR
CS L
CSR
CS L
CS R
L_A16
L_A15
L_A14
L_CS
R_R/W
R_OE
R_A0-13
74FCT138
74FCT138
L_A0-13
L_OE
R_CS
R_A14
L_R/W
R_A15
R_A16
L_I/O0-7
CS L
CS R
7006
CS L
CSR
CS L
7006
CSR
CS L
7006
CS R
7006
R_SEM
L_SEM
2804 drw 02
7M1003
R_I/O0-7
L_A15
L_A14
L_CS
R_R/W
R_OE
R_A0-13
74FCT138
74FCT138
L_A0-13
L_OE
L_R/W
L_I/O0-7
R_CS
R_A14
R_A15
CS L
CS R
7006
CS L
CS L
CSR
7006
CSR
7006
CS L
CS R
7006
R_SEM
L_SEM
2804 drw 03
7.5
2
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
Military
Unit
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0
–0.5 to +7.0
V
TA
Operating
Temperature
0 to +70
–55 to +125
°C
TBIAS
Temperature
Under Bias
–55 to +125
–65 to +135
°C
TSTG
Storage
Temperature
–55 to +125
–65 to +150
°C
IOUT
DC Output
Current
50
50
mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Military
–55°C to +125°C
0V
5.0V ± 10%
0°C to +70°C
0V
5.0V ± 10%
Symbol
Test Conditions
Max.
Unit
CIN1
Input Capacitance
VIN = 0V
15
pF
VIN = 0V
100
pF
VOUT = 0V
100
pF
Parameter
VCC
Supply Voltage
GND
Supply Voltage
VIH
Input High Voltage
VIL
Parameter
VCC
RECOMMENDED DC OPERATING
CONDITIONS
CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
Symbol
GND
2804 tbl 04
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CIN2
Ambient
Temperature
Commercial
2804 tbl 02
(CS or
Grade
Input Low Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
-
6.0
V
-
0.8
(1)b
–0.5
b
V
2804 tbl 05
NOTE:
1. VIL (min.) = –3.0V for pulse width less than 20ns.
)
SEM
Input Capacitance
(Data, Address,
All Other Controls)
COUT
Output Capacitance
(Data)
NOTE:
1. This parameter is guaranteed by design but not tested.
2804 tbl 03
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V ± 10%, TA = –55°C to +125°C or 0°C to +70°C)
Commercial
Test Conditions
Min. Max.
(1)
Military
Max.
(2)
Min. Max.(1) Max.(2) Unit
Symbol
Parameter
ICC2
Dynamic Operating
Current (Both Ports Active)
VCC = Max., CS ≤ VIL, SEM ≥ VIH
Outputs Open, f = fMAX
—
940
660
—
1130
790
mA
ICC1
Standby Supply
Current (One Port Active)
VCC = Max., L_CS or R_CS ≥ VIH
Outputs Open, f = fMAX
—
750
470
—
905
565
mA
ISB1
Standby Supply
Current (TTL Levels)
VCC = Max., L_CS and R_CS ≥ VIH
Outputs Open, f = fMAX
—
565
285
—
685
345
mA
—
125
65
—
245
125
mA
L_SEM and R_SEM ≥ VCC –0.2V
ISB2
Full Standby Supply
Current (CMOS Levels)
L_CS and R_CS ≥ VCC –0.2V
VIN > VCC 0.2V or < 0.2V
L_SEM and R_SEM ≥ VCC –0.2V
2804 tbl 06
NOTES:
1. IDT7M1001 (128K x 8) version only.
2. IDT7M1003 (64K x 8) version only.
7.5
3
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(VCC=5.0V ± 10%, TA = –55°C to +125°C and 0°C to +70°C)
Symbol
Parameter
IDT7M1001
Min.
Max.
Test Conditions
IDT7M1003
Min.
Max.
Unit
|ILI|
Input Leakage
(Address, Data & Other Controls)
VCC = Max.
VIN = GND to VCC
—
80
—
40
µA
|ILI|
Input Leakage
(CS and SEM)
VCC = Max.
VIN = GND to VCC
—
10
—
10
µA
|ILO|
Output Leakage
(Data)
VCC = Max.
≥ VIH, VOUT = GND to VCC
—
80
—
40
µA
CS
VOL
Output Low Voltage
VCC = Min.
IOL = 4mA
—
0.4
—
0.4
V
VOH
Output High Voltage
VCC = Min.
IOH = –4mA
2.4
—
2.4
—
V
2804 tbl 07
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2804 tbl 08
+5 V
+5 V
480 Ω
480 Ω
DATAOUT
DATAOUT
255Ω
255Ω
30 pF*
5 pF*
2804 drw 04
2804 drw 05
Figure 2. Output Load
(for tCLZ, tCHZ, tOLZ. tOHZ, tWHZ, tOW)
Figure 1. Output Load
*Including scope and jig.
7.5
4
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%, TA = -55°C to +125°C and 0°C to +70°C)
–35
Symbol
–40
–50
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
35
—
40
—
50
—
ns
tAA
Address Access Time
—
35
—
40
—
50
ns
tACS(2)
Chip Select Access Time
—
35
—
40
—
50
ns
tOE
Output Enable Access Time
—
20
—
25
—
30
ns
tOH
Output Hold From Address Change
3
—
3
—
3
—
ns
Read Cycle
tCLZ(1)
Chip Select to Output in Low-Z
3
—
3
—
3
—
ns
(1)
Chip Deselect to Output in High-Z
—
20
—
20
—
25
ns
(1)
Output Enable to Output in Low-Z
3
—
3
—
3
—
ns
(1)
tCHZ
tOLZ
tOHZ
Output Disable to Output in High-Z
—
20
—
20
—
25
ns
tPU(1)
Chip Select to Power-Up Time
0
—
0
—
0
—
ns
tPD(1)
Chip Disable to Power-Down Time
—
50
—
50
—
50
ns
tSOP
SEM
15
—
15
—
15
—
ns
Write Cycle Time
35
—
40
—
50
—
ns
Chip Select to End-of-Write
30
—
35
—
40
—
ns
tAW
Address Valid to End-of-Write
30
—
35
—
40
—
ns
tAS1(3)
Address Set-up to Write Pulse Time
5
—
5
—
5
—
ns
tAS2
Address Set-up to CS Time
0
—
0
—
0
—
ns
tWP
Write Pulse Width
30
—
35
—
40
—
ns
Write Recovery Time
0
—
0
—
0
—
ns
tDW
Data Valid to End-of-Write
25
—
30
—
35
—
ns
tDH(4)
Data Hold Time
0
—
0
—
0
—
ns
tOHZ(1)
Output Disable to Output in High-Z
—
20
—
20
—
25
ns
tWHZ(1)
Write Enable to Output in High-Z
—
20
—
20
—
25
ns
tOW(1, 4)
Output Active from End-of-Write
0
—
0
—
0
—
ns
tSWRD
SEM
Flag Write to Read Time
15
—
15
—
15
—
ns
tSPS
SEM
Flag Contention Window
15
—
15
—
15
—
ns
Flag Update Pulse (OE or SEM)
Write Cycle
tWC
tCW
tWR
(2)
(4)
Port-to-Port Delay Timing
tWDD(5)
Write Pulse to Data Delay
—
60
—
65
—
70
ns
tDDD(5)
Write Data Valid to Read Data Valid
—
45
—
50
—
55
ns
NOTES:
1. This parameter is guaranteed by design but not tested.
2. To access RAM CS ≤ VIL and SEM ≥ VIH. To access semaphore, CS ≥ VIH and SEM ≤ VIL.
3. tAS1= 0 if R/W is asserted LOW simultaneously with or after the CS LOW transition.
4. For CS controlled write cycles, tWR= 5ns, tDH= 5ns, tOW= 5ns.
5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
7.5
2804 tbl 09
5
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1 (EITHER SIDE)(1,2,4)
t RC
ADDRESS
t OH
t AA
t OH
DATA OUT
DATA VALID
PREVIOUS DATA VALID
2804 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2 (EITHER SIDE)(1,3,5)
t ACS
CS
t CHZ
(6)
t OE
OE
t OHZ
t OLZ (6)
DATA OUT
(6)
DATA VALID
t CLZ
t PU
(6)
(6)
t PD
(6)
ICC
CURRENT
50%
50%
ISB
NOTES:
1. R/W is HIGH for Read Cycles
2. Device is continuously enabled. CS = LOW. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition LOW.
4. OE = LOW.
5. To access RAM, CS = LOW, SEM = H. To access semaphore, CS = HIGH and SEM = LOW.
6. This parameter is guaranteed by design but not tested.
7.5
2804 drw 07
6
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/W CONTROLLED TIMING)(1,3,5,8)
t
WC
ADDRESS
t OHZ (9)
OE
t AW
CS
t AS (6)
t WR (7)
t WP(2)
R/W
t OW (9)
t WHZ (9)
DATA OUT
(4)
(4)
t DW
DATA
t DH
DATA VALID
IN
2804 drw 08
NOTES:
1. R/W is HIGH for Read Cycles
2. Device is continuously enabled. CS = LOW. UB or LB = LOW. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition low.
4. OE = LOW.
5. To access RAM, CS = LOW, UB or LB = LOW, SEM = H. To access semaphore, CS = HIGH and SEM = LOW.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse width
be as short as the specified tWP.
9. This parameter is guaranteed by design but not tested.
TIMING WAVEFORM OF WRITE CYCLE NO. 2 ( CS CONTROLLED TIMING)(1,3,5,8)
t
WC
ADDRESS
t AW
CS
t AS (6)
UB or LB
t WR (7)
t WP (2)
R/W
t DW
DATA
t DH
DATA VALID
IN
2804 drw 09
NOTES:
1. R/W must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW UB or LB and a LOW CS and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CS or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. This parameter is guaranteed by design but not tested.
7.5
7
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING (EITHER SIDE)(1)
t OH
t AA
VALID ADDRESS
A 0 - A2
t AW
VALID ADDRESS
t
t WR
ACS
t WP
SEM
t SOP
t DW
DATA 0
DATA OUT
VALID
DATA IN VALID
t AS
t WP
t DH
R/W
t OE
t SWRD
t SOP
OE
READ CYCLE
WRITE CYCLE
2804 drw 10
NOTE:
1. CS = HIGH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE CONTENTION(1,3,4)
MATCH
A 0A - A 2A
SIDE
(2)
“A”
R/W A
SEM A
t SPS
A 0B - A 2B
SIDE
(2)
“B”
MATCH
R/W B
SEM B
2804 drw 11
NOTES:
1. D0R = D0L = LOW, L_CS = R_CS = HIGH. Semaphore Flag is released form both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "B" is the opposite port from "A".
3. This parameter is measured from R/WA or SEMA going HIGH to R/ WB or SEMB going HIGH.
4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
7.5
8
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY(1)
t WC
ADDR
R
R/W
R
MATCH
t WP
t DH
t DW
DATA IN
VALID
R
ADDR L
MATCH
t WDD
DATA
OUT L
VALID
t DDD
NOTE:
1. L_CS = R_CS = LOW.
WRITE CYCLE LEFT PORT
READ CYCLE
RIGHT PORT
2804 drw 12
TRUTH TABLES
TABLE I: NON-CONTENTION READ/WRITE CONTROL(1)
Inputs(1)
Outputs
R/W
OE
SEM
I/O0 - I/O7
Mode
X
X
H
High-Z
Deselected: Power Down
L
L
X
H
DATAIN
Write to Both Bytes
L
H
L
H
DATAOUT
Read Both Bytes
X
X
H
X
High-Z
Outputs Disabled
CS
H
NOTE:
1. AOL — A12 ≠ A0R — A12R
2804 tbl 10
TABLE II: SEMAPHORE READ/WRITE CONTROL(1)
Inputs
CS
H
R/W
H
X
L
X
Outputs
OE
SEM
I/O0 - I/O7
Mode
L
L
DATAOUT
Read Data in Semaphore Flag
X
L
DATAIN
Write DIN0 into Semaphore Flag
X
L
—
Not Allowed
NOTE:
1. AOL — A12 ≠ A0R — A12R
2804 tbl 11
SEMAPHORE OPERATION
For more details regarding semaphores & semaphore operations, please consult the IDT7006 datasheet.
7.5
9
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
PACKAGE DIMENSIONS
7M1001
MILITARY AND COMMERCIAL TEMPERATURE RANGES
3.190
3.210
0.615
0.635
0.605
0.625
TOP VIEW
PIN1
0.330
MAX.
0.010
0.050
0.380
MAX.
0.007
0.013
SIDE VIEW
0.035
0.060
0.015
0.022
0.100
TYP.
0.125
0.175
SIDE VIEW
BOTTOM VIEW
2804 drw 13
7M1003
3.190
3.210
0.615
0.635
0.605
0.625
TOP VIEW
PIN1
0.310
MAX.
0.380
MAX.
0.010
0.070
0.007
0.013
SIDE VIEW
0.035
0.060
0.015
0.022
0.100
TYP.
0.125
0.175
SIDE VIEW
BOTTOM VIEW
2804 drw 14
7.5
10
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXX
Device
type
A
Power
999
Speed
A
Package
A
Process/
Temperature
range
BLANK Commercial (0°C to +70°C)
B
Military (-55°C to +125°C)
Semiconductor components compliant to
MIL-STD-883, Class B
C
Sidebraze DIP (Dual In-line Package)
35
40
50
(Commercial Only)
S
Standard Power
Nanoseconds
(Military Only)
7M1001 128K x 8 Dual-Port Static RAM Module
7M1003 64K x 8 Dual-Port Static RAM Module
2804 drw 15
7.5
11