DATASHEET 9DBL411B Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI Recommended Application: Features/Benefits: PCI-Express Gen2 or QPI fanout buffer • Low power differential outputs for PCIExpress and QPI clocks • Power down mode when all OE# are high • Available in I-temp • 20-pin MLF or TSSOP packaging Output Features: • 4 - low power differential output pairs • Individual OE# control of each output pair General Description: The 9DBL411B is a 4 output lower power differential buffer. Each output has its own OE# pin. It has a maximum operating frequency of 150 MHz. Key Specifications: • Output cycle-cycle jitter < 15ps additive • Output to output skew: < 50ps Power Groups Pin Number (TSSOP) VDD GND 9,18 10,17 4 5 Pin Number (MLF) VDD GND 6,15 7,14 1 2 Description VDD_IO for DIF(3:0) 3.3V Analog VDD & GND Description VDD_IO for DIF(3:0) 3.3V Analog VDD & GND Functional Block Diagram 4 OE#(3:0) DIF_INT STOP LOGIC DIF_INC IDT® Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI 1 4 DIF_LPR(3:0) 1645C—10/18/10 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information OE0# DIF_INC DIF_INT VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR VDD_IO GND 20 19 18 17 16 7 8 9 10 DIF2T_LPR 15 14 13 12 11 VDD_IO GND OE1# DIF1T_LPR DIF1C_LPR OE2# 6 DIF2C_LPR 9DBL411B GND 1 2 3 4 5 VDD_IO VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR 20-pin MLF 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 9DBL411B DIF0C_LPR DIF0T_LPR OE0# DIF_INC DIF_INT Pin Configurations DIF0T_LPR DIF0C_LPR VDD_IO GND OE1# DIF1T_LPR DIF1C_LPR OE2# DIF2T_LPR DIF2C_LPR 20-pin TSSOP Terminations Zo 9DBL411 Rs Zo Rs Zo – 17 = Rs (ohms), where Zo is the single-ended intrinsic impedance of the board transmission line. Single-ended intrinsic impedance is ½ that of the differential impedance. Single Ended Rs Impedance 5% Rs (Zo) tolerance 2% tolerance Notes 50 33 33.2 In general, 5% resistors 45 27 27.4 may be used. All values are 42.5 24 or 27 24.9 in ohms. IDT® Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI 2 1645C—10/18/10 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information TSSOP Pin Description PIN # (TSSOP) PIN NAME 1 OE0# 2 3 4 5 DIF_INC DIF_INT VDDA GNDA 6 OE3# 7 8 9 10 11 12 DIF3C_LPR DIF3T_LPR VDD_IO GND DIF2C_LPR DIF2T_LPR 13 OE2# 14 15 DIF1C_LPR DIF1T_LPR 16 OE1# 17 18 19 20 GND VDD_IO DIF0C_LPR DIF0T_LPR PIN TYPE IN IN IN PWR GND IN OUT OUT PWR GND OUT OUT IN OUT OUT IN GND PWR OUT OUT DESCRIPTION Output Enable for DIF0 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement side of differential input clock True side of differential input clock 3.3V Power for the Analog Core Ground for the Analog Core Output Enable for DIF3 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Power supply for low power differential outputs, nominal 1.05V to 3.3V Ground pin Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF2 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF1 output. Control is as follows: 0 = enabled, 1 = Low-Low Ground pin Power supply for low power differential outputs, nominal 1.05V to 3.3V Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) IDT® Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI 3 1645C—10/18/10 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information MLF Pin Description PIN # (MLF) 1 2 VDDA GNDA PWR GND 3 OE3# IN 4 DIF3C_LPR OUT 5 DIF3T_LPR OUT 6 7 VDD_IO GND PWR GND 8 DIF2C_LPR OUT 9 DIF2T_LPR OUT 10 OE2# 11 DIF1C_LPR OUT 12 DIF1T_LPR OUT 13 OE1# 14 15 GND VDD_IO GND PWR 16 DIF0C_LPR OUT 17 DIF0T_LPR OUT 18 OE0# IN 19 20 DIF_INC DIF_INT IN IN PIN NAME PIN TYPE IN IN DESCRIPTION 3.3V Power for the Analog Core Ground for the Analog Core Output Enable for DIF3 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Power supply for low power differential outputs, nominal 1.05V to 3.3V Ground pin Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF2 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF1 output. Control is as follows: 0 = enabled, 1 = Low-Low Ground pin Power supply for low power differential outputs, nominal 1.05V to 3.3V Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF0 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement side of differential input clock True side of differential input clock IDT® Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI 4 1645C—10/18/10 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS Maximum Supply Voltage VDDA Core Supply Voltage Maximum Supply Voltage VDD_IO Low-Voltage Differential I/O Supply Maximum Input Voltage VIH 3.3V LVCMOS Inputs Minimum Input Voltage MIN 0.99 MAX UNITS Notes 4.6 V 1,7 3.8 V 1,7 4.6 V 1,7,8 V 1,7 VIL Any Input Vss - 0.5 TambCOM Commercial Range 0 70 °C 1 TambIND Industrial Range -40 85 °C 1 Storage Temperature Ts - -65 150 Input ESD protection ESD prot Human Body Model 2000 Ambient Operating Temp ° C 1,7 V 1,7 Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Supply Voltage VDDxxx Supply Voltage 3.000 3.600 V 1 Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 0.99 3.600 V 1 Input High Voltage VIHSE Single-ended inputs 2 VDD + 0.3 V 1 Input Low Voltage VILSE VSS - 0.3 0.8 V 1 Differential Input High Voltage VIHDIF 600 1.15 V 1 Differential Input Low Voltage VILDIF VSS - 0.3 300 V 1 Input Slew Rate - DIF_IN dv/dt Single-ended inputs Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) Measured differentially 0.4 8 V/ns 2 Input Leakage Current IIN VIN = VDD , VIN = GND -5 5 uA 1 Operating Supply Current IDD_3.3V VDDA supply current 20 mA 1 IDD_IO_133M VDD_IO supply @ fOP = 133MHz VDDA supply current, Input stopped, OE# pins all high VDD_IO supply, Input stopped, OE# pins all high VDD = 3.3 V 20 mA 1 750 uA 1 150 uA 1 150 MHz 2 7 nH 1 5 pF 1 6 pF 1 3 periods 1 150 ns 1 10 ns 1 5 ns 1 5 ns 1 Power Down Current (All OE# pins High) IDD_SB_3.3V IDD_SBIO Input Frequency Fi Pin Inductance Lpin Input Capacitance CIN Logic Inputs COUT Output pin capacitance Number of clocks to enable or disable output from assertion/deassertion of OE# Delay from assertion of first OE# to first clock out (assumes input clock running) Output enable after OE# de-assertion OE# latency (at least one OE# is low) TOE#LAT Clock stabilization time (from all OE# high to first OE# low). TSTAB Tdrive_OE# TDROE# Tfall_OE# TFALL Trise_OE# TRISE 15 1.5 Fall/rise time of OE# inputs IDT® Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI 5 1 1645C—10/18/10 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information AC Electrical Characteristics - DIF Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Rising Edge Slew Rate tSLR Differential Measurement 1.5 4 V/ns 1,2 Falling Edge Slew Rate tFLR Differential Measurement 1.5 4 V/ns 1,2 Slew Rate Variation tSLVAR Single-ended Measurement 20 % 1 Maximum Output Voltage VHIGH Includes overshoot mV 1 Minimum Output Voltage VLOW Includes undershoot -300 mV 1 Differential Voltage Swing VSWING Differential Measurement 1200 Crossing Point Voltage VXABS Single-ended Measurement 300 Crossing Point Variation VXABSVAR Duty Cycle Distortion DCYCDIS0 Additive Cycle to Cycle Jitter DIFJ C2CADD DIF[3:0] Skew DIFSKEW Single-ended Measurement Differential Measurement, fIN<=133.33MHz Differential Measurement, Additive Differential Measurement Propagation Delay Additive Phase Jitter - PCIe Gen1 Additive Phase Jitter - PCIe Gen2 High Band Additive Phase Jitter PCIe Gen2 Low Band Additive Phase Jitter QPI133 (6.4GBs, 12 UI) tPD Input to output Delay tphase_addPCIG1 1150 mV 1 550 mV 1,3,4 140 mV 1,3,5 3 % 1,6 15 ps 1 50 ps 1 3.5 ns 1 1.5MHz < 22MHz 6 ps Pk-Pk 1,9 tphase_addPCIG2HI High Band is 1.5MHz to Nyquist (50MHz) 0.16 ps rms 1,9 tphase_addPCIG2LO Low Band is 10KHz to 1.5MHz 0.07 ps rms 1,9 tphase_addQPI6G4 11MHz to 33MHz 0.04 ps rms 1,9 2.5 Notes on Electrical Characteristics (all measurements use 9LRS3187B as clock source and R S=33ohms/CL=2pF test load): 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. 5 6 This figure refers to the maximum distortion of the input wave form. 7 Operation under these conditions is neither implied, nor guaranteed. 8 Maximum input voltage is not to exceed maximum VDD The 9DBL411B has no PLL, so the part itself contributes very little jitter to the input clock. But this also means that the 9DBL411 cannot 'de-jitter' a noisy input clock. Values calculated per PCI SIG and per Intel Clock Jitter tool version 1.5 9 IDT® Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI 6 1645C—10/18/10 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information 20-pin TSSOP Package Drawing and Dimensions 20-Lead, 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 .169 .177 e 0.65 BASIC 0.0256 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° aaa -0.10 -.004 c N L E1 E INDEX AREA 1 2 α D A A2 VARIATIONS A1 -Ce b N SEATING PLANE 20 aaa C D mm. MIN 6.40 D (inch) MAX 6.60 MIN .252 MAX .260 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 IDT® Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI 7 1645C—10/18/10 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information 20-pin MLF Package Drawing and Dimensions (Ref.) Seating Plane (N D -1)x e (Ref.) A1 Index Area ND & N Even A3 N L N 1 Anvil Singulation E2 (Ref.) b (Re f.) A Chamfer 4x 0.6 x 0.6 max OPTIONAL (N -1)x e E2 2 Sawn Singulation D are Even 2 OR Top V iew (T yp.) e 2 If N & N D e D2 2 ND & N Odd Thermal Base D2 0. 08 C C THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS SYMBOL A A1 A3 b e DIMENSIONS MIN. MAX. 0.8 1.0 0 0.05 0.20 Reference 0.18 0.3 0.50 BASIC SYMBOL N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. ICS 20L TOLERANCE 20 5 5 4.00 x 4.00 2.00 / 2.25 2.00 / 2.25 0.45 / 0.65 Ordering Information Part / Order Number 9DBL411BKLF 9DBL411BKLFT 9DBL411BGLF 9DBL411BGLFT 9DBL411BKILF 9DBL411BKILFT 9DBL411BGILF 9DBL411BGILFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 20-pin MLF 20-pin MLF 20-pin TSSOP 20-pin TSSOP 20-pin MLF 20-pin MLF 20-pin TSSOP 20-pin TSSOP Temperature 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C -40 to +85°C -40 to +85°C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. "B" is the device revision designator (will not correlate to the datasheet revision). IDT® Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI 8 1645C—10/18/10 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information Revision History Rev. 0.1 A B C Issue Date Description Initial Release. Compared with A rev the following have changed: 1. Added I-temp version 1/8/2010 2. Updated electrical tables for I-temp 3. Revised Phase Jitter specs and added QPI. 1/8/2010 Released to final. 4/23/2010 Changed Input Frequency from 33 min to 15 MHz min 10/18/2010 Updated Supply Voltage min/max ratings. Page # 5 5 This product is protected by United States Patent NO. 7, 342, 420 and other patents. Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 [email protected] Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA IDT® Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI 9 1645C—10/18/10