ICS9DB202 PCI EXPRESS JITTER ATTENUATOR GENERAL DESCRIPTION FEATURES The ICS9DB202 is a high perfromance 1-to-2 Differential-to-HCSL Jitter Attenuator designed for use in PCI Express™ systems. In some PCI Express™ systems, such as those found in desktop PCs, the PCI Express™ clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter-attenuating device may be necessary in order to reduce high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS9DB202 has two PLL bandwidth modes. In low bandwidth mode, the PLL loop bandwidth is 500kHz. This setting offers the best jitter attenuation and is still high enough to pass a triangular input spread spectrum profile. In high bandwidth mode, the PLL bandwidth is at 1MHz and allows the PLL to pass more spread spectrum modulation. • Two 0.7V current mode differential HCSL output pairs For serdes which have x10 reference multipliers instead of x12.5 multipliers, each of the two PCI Express™ outputs (PCIEX0:1) can be set for 125MHz instead of 100MHz by configuring the appropriate frequency select pins (FS0:1). • 3.3V operating supply ICS • One differential clock input HiPerClockS™ • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 140MHz • Input frequency range: 90MHz - 140MHz • VCO range: 450MHz - 700MHz • Output skew: 110ps (maximum) • Cycle-to-cycle jitter: 110ps (maximum) • RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 2.42ps (typical) • 0°C to 70°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM IREF • Industrial temperature information available upon request 1 HiZ 0 Enabled nOE0 nCLK CLK PIN ASSIGNMENT Current Set + Phase Detector 0 Loop Filter VCO 0 ÷4 1 ÷5 PCIEXT0 nPCIEXC0 1 0 FS1 20 19 18 17 16 15 14 13 12 11 VDDA BYPASS IREF FS1 VDD GND PCIEXT1 PCIEXC1 VDD nOE1 ICS9DB202 Internal Feedback 0 ÷5 1 ÷4 1 2 3 4 5 6 7 8 9 10 20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body G Package Top View FS0 ÷5 PLL_BW CLK nCLK FS0 VDD GND PCIEXT0 PCIEXC0 VDD nOE0 1 PCIEXT1 nPCIEXC1 ICS9DB202 20-Lead, 209-MIL SSOP 5.30mm x 7.20mm x 1.75mm body package F Package Top View BYPASS nOE1 1 HiZ 0 Enabled IDT ™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 1 ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 PLL_BW Input Type 2 CLK Input 3 nCLK Input Pullup Description Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Pullup Frequency select pin. LVCMOS/LVTTL interface levels. 4 FS0 Input 5, 9, 12, 16 VDD Power Core supply pins. 6, 15 GND PCIEXT0, PCIEXC0 Power Power supply ground. Output Differential output pairs. HCSL interface levels. 7, 8 10, 11 nOE0, nOE1 Input 17 PCIEXC1, PCIEXT1 FS1 18 IREF Input 19 BYPASS Power 20 VDDA Power 13, 14 Pulldown Output Input Output enable. When HIGH, forces outputs to HiZ state. When LOW, enables outputs. LVCMOS/LVTTL interface levels. Differential output pairs. HCSL interface levels. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. A fixed precision resistor (475Ω) from this pin to ground provides a reference current used for differential current-mode PCIEX clock outputs. BYPASS pin. When HIGH. bypass mode, when LOW, PLL mode. Pulldown LVCMOS/LVTTL interface levels. Analog supply pin. Requires 24Ω series resistor. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3A. RATIO OF OUTPUT FREQUENCY TO INPUT FREQUENCY FUNCTION TABLE, FS0 TABLE 3B. RATIO OF OUTPUT FREQUENCY TO INPUT FREQUENCY FUNCTION TABLE, FS1 Inputs Outputs Inputs Outputs FS0 PCIEX0 FS1 PCIEX1 0 5/4 0 1 1 1 1 5/4 TABLE 3D. OUTPUT ENABLE FUNCTION TABLE, NOE0 TABLE 3E. OUTPUT ENABLE FUNCTION TABLE, NOE1 TABLE 3C. BYPASS TABLE Inputs BYPASS 0 1 Mode PLL Mode Bypass Mode (output = inputs) TABLE 3F. PLL BANDWIDTH TABLE Inputs Outputs Inputs Outputs Inputs nOE0 PCIEX0 nOE1 PCIEX1 PLL_BW 0 Enabled 0 Enabled 0 500kHz 1 HiZ 1 HiZ 1 1MHz IDT ™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 2 Bandwidth ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 20 Lead TSSOP 73.2°C/W (0 lfpm) 20 Lead SSOP 80.8°C/W (0 lfpm) -65°C to 150°C Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3. 3 3.465 V 3.135 3. 3 VDDA Analog Supply Voltage 3.465 V IDD Power Supply Current 112 mA IDDA Analog Supply Current 22 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions BYPASS, nOE0, nOE1, FS1 FS0, PLL_BW BYPASS, nOE0, nOE1, FS1 FS0, PLL_BW Minimum Maximum Units 2 Typical VDD + 0.3 mV -0.3 0.8 mV 150 µA VDD = VIN = 3.465V 5 VDD = 3.465V, VIN = 0V -5 µA -150 TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω Symbol Parameter IIH Input High Current CLK, nCLK VDD = VIN = 3.465V Test Conditions IIL Input Low Current CLK, nCLK VDD = 3.465V, VIN = 0V VPP Peak-to-Peak Input Voltage Minimum Typical 0.15 VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. IDT ™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 3 Maximum Units 150 µA 150 µA 1.3 V VDD - 0.85 V ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR TABLE 4D. HCSL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω Symbol Parameter IOH Output Current Test Conditions VOH Output High Voltage VOL Output Low Voltage IOZ High Impedance Leakage Current VOX Output Crossover Voltage Minimum Typical Maximum Units 12 14 16 mA 780 mV 65 mV -10 10 µA 250 550 mV Maximum Units 140 MHz 610 TABLE 5. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω Symbol Parameter fMAX Output Frequency tsk(o) Output Skew; NOTE 1, 2 tjit(cc) tjit(Ø) tR / tF Cycle-to-Cycle Jitter RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Test Conditions Minimum Typical 110 ps Outputs @ Different Frequencies 50 110 ps Outputs @ Same Frequencies 50 ps Integration Range: 1.5MHz - 22MHz 20% to 80% 2.42 300 o dc Output Duty Cycle 48 NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot following this section. IDT ™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 4 ps 1100 ps 52 % ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR TYPICAL PHASE NOISE AT 100MHZ ➤ 0 -10 PCI Express™ Filter -20 -30 100MHz -40 RMS Phase Jitter (Random) 1.5MHz to 22MHz = 2.42ps (typical) -70 -80 -90 -100 Raw Phase Noise Data -110 -120 ➤ NOISE POWER dBc Hz -50 -60 -130 -140 ➤ -150 -160 Phase Noise Result by adding PCI Express™ Filter to raw data -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) The illustrated phase noise plot was taken using a low phase noise signal generator, the noise floor of the signal generator is less than that of the device under test. Due to the tracking ability of a PLL, it will track the input signal up to its loop bandwidth. Therefore, if the input phase noise is greater than that of the PLL, it will increase the output phase noise performance of the device. It is recommended that the phase noise performance of the input is verified in order to achieve the above phase noise performance. Using this configuration allows one to see the true spectral purity or phase noise performance of the PLL in the device under test. IDT ™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 5 ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION 3.3V±5% VDD 3.3V±5% nCLK VDD SCOPE Qx V V Cross Points PP VDDA CMR CLK HCSL GND nQx GND 0V 3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PCIEXC0, PCIEXC1 PCIEXCx PCIEXTy PCIEXT0, PCIEXT1 ➤ ➤ PCIEXCx ➤ tcycle n tcycle n+1 ➤ t jit(cc) = tcycle n –tcycle n+1 PCIEXTy 1000 Cycles t sk(o) OUTPUT SKEW CYCLE-TO-CYCLE JITTER PCIEXC0, PCIEXC1 80% 80% PCIEXT0, PCIEXT1 VSW I N G Clock Outputs 20% 20% tR t PW t PERIOD tF odc = t PW x 100% t PERIOD HCSL OUTPUT RISE/FALL TIME IDT ™ / ICS™ PCI EXPRESS JITTER ATTENUATOR OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 6 ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS9DB202 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 24Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA pin. The 10Ω resistor can also be replaced by a ferrite bead. 3.3V VDD .01µF 24Ω VDDA .01µF 10µF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT ™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 7 ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kW resistor can be used. HCSL OUTPUT All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. IDT ™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 8 BY ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR RELIABILITY INFORMATION TABLE 6A. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP PACKAGE θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98°C/W 66.6°C/W 88°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 6B. θJAVS. AIR FLOW TABLE FOR 20 LEAD SSOP PACKAGE θJA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 80.8°C/W 200 73.2°C/W 500 69.2°C/W TRANSISTOR COUNT The transistor count for ICS9DB202 is: 2471 IDT ™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 9 ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP PACKAGE OUTLINE - F SUFFIX FOR 20 LEAD SSOP TABLE 6A. PACKAGE DIMENSIONS SYMBOL TABLE 6B. PACKAGE DIMENSIONS Millimeters Millimeters Minimum N SYMBOL Maximum Minimum 20 N Maximum 20 A -- 1.20 A -- 2.0 A1 0.05 0.15 A1 0.05 -- A2 0.80 1.05 A2 1.65 1.85 b 0.19 0.30 b 0.22 0.38 c 0.09 0.20 D 6.40 6.60 c 0.09 0.25 D 6.90 7.50 E 7.40 8.20 E1 5.0 5.60 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC e 0.65 BASIC L 0.45 0.75 α 0° 8° L 0.55 0.95 0.10 α 0° 8° aaa -- Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ PCI EXPRESS JITTER ATTENUATOR Reference Document: JEDEC Publication 95, MO-150 10 ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS9DB202CG ICS9DB202CG 20 Lead TSSOP Tube 0°C to 70°C ICS9DB202CGT ICS9DB202CG 20 Lead TSSOP 2500 Tape & Reel 0°C to 70°C ICS9DB202CGLF ICS9DB202CGL 20 Lead "Lead-Free" TSSOP Tube 0°C to 70°C ICS9DB202CGLFT ICS9DB202CGL 20 Lead "Lead-Free" TSSOP 2500 Tape & Reel 0°C to 70°C ICS9DB202CF ICS9DB202CF 20 Lead SSOP Tube 0°C to 70°C ICS9DB202CFT ICS9DB202CF 20 Lead SSOP 1000 Tape & Reel 0°C to 70°C ICS9DB202CFLF ICS9DB202CFLF 20 Lead "Lead-Free" SSOP Tube 0°C to 70°C ICS9DB202CFLFT ICS9DB202CFLF 20 Lead "Lead-Free" SSOP 1000 Tape & Reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 11 ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR REVISION HISTORY SHEET Rev Table Page B T4D 4 6 8 B B B T7 T4 D Description of Change Date 12/21/04 11 4 HCSL Table -adjusted VOH min from 680mV to 610mV and added VOH max. Updated HCSL Output Load AC Test Circuit Diagram. Application Information - added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free note. HCSL DC Characteristics - corrected units for VOH & VOL from V to mV. 1 Feature Section - added Input Frequency Range and VCO Range. 7/14/06 IDT ™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 12 3/8/06 5/26/06 ICS9DB202CG REV B JULY 14, 2006 ICS9DB202 PCI EXPRESS JITTER ATTENUATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA