PRELIMINARY IDT709269S/L HIGH-SPEED 16K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 9/12/15ns (max.) Low-power operation – IDT709269S Active: 950mW (typ.) Standby: 5mW (typ.) – IDT709269L Active: 950mW (typ.) Standby: 1mW (typ.) Flow-through or Pipelined output mode on either port via the FT/PIPE pin Counter enable and reset features Dual chip enables allow for depth expansion without additional logic ◆ ◆ ◆ ◆ Full synchronous operation on both ports – 4ns setup to clock and 1ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 9ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 15ns cycle time, 66MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility TTL- compatible, single 5V (±10%) power supply Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in a 100-pin Thin Quad Flatpack (TQFP) package Functional Block Diagram R/WL UBL R/WR UBR CE0L CE1L CE0R CE1R 1 0 0/1 1 0 0/1 LBR OER LBL OEL FT/PIPEL 0/1 1b 0b b a 0a 1a 1a 0a a b 0b 1b 0/1 FT/PIPER I/O8R-I/O15R I/O8L-I/O15L I/O Control I/O Control I/O0R-I/O7R I/O0L-I/O7L A13R A13L A0L CLKL ADSL CNTENL CNTRSTL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A0R CLKR ADSR CNTENR CNTRSTR 3493 drw 01 APRIL 2000 1 ©2000 Integrated Device Technology, Inc. DSC-3493/8 IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Description: The IDT709269 is a high-speed 16K x 16 bit synchronous pipelined Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT709269 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 950mW of power. A8L A7L A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL GND ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R A7R A8R Pin Configuration(1,2,3) Index 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 3 1 2 4 72 71 5 70 69 6 7 68 67 8 9 10 11 IDT709269PF PN100-1(4) 66 100-PIN TQFP TOP VIEW(5) 63 62 12 13 14 65 64 61 60 15 16 17 59 58 57 18 19 56 55 20 21 22 54 53 23 52 24 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O9L I/O8L Vcc I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/OIL I/O0L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R Vcc I/O7R I/O8R I/O9R NC A9L A10L A11L A12L A13L NC NC NC NC LBL UBL CE0L CE1L CNTRSTL Vcc R/WL OEL FT/PIPEL GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 2 6.42 A9R A10R A11R A12R A13R NC NC NC NC LBR UBR CE0R CE1R CNTRSTR GND R/WR OER FT/PIPER GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R 3493 drw 02 , IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A13L A0R - A13R Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output CLKL CLK R Clock UBL UBR Upper Byte Select LBL LBR Lower Byte Select ADSL ADSR Address Strobe CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPER Flow-Through/Pipeline FT/PIPEL VCC Power GND Ground 3493 tbl 01 Truth Table IRead/Write and Enable Control(1,2,3) OE CLK CE0 CE1 UB LB R/W Upper Byte I/O8-15 Lower Byte I/O0-7 X ↑ H X X X X High-Z High-Z Deselected—Power Down X ↑ X L X X X High-Z High-Z Deselected—Power Down X ↑ L H H H X High-Z High-Z Both Bytes Deselected X ↑ L H L H L DIN High-Z Write to Upper Byte Only X ↑ L H H L L High-Z DIN Write to Lower Byte Only X ↑ L H L L L DIN DIN Write to Both Bytes L ↑ L H L H H DOUT High-Z Read Upper Byte Only L ↑ L H H L H High-Z DOUT Read Lower Byte Only L ↑ L H L L H DOUT DOUT Read Both Bytes H X L H L L X High-Z High-Z Outputs Disabled Mode 3493 tbl 02 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 6.42 3 IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges TRUTH TABLE IIAddress Counter Control(1,2) Address Previous Address CLK ADS CNTEN CNTRST I/O(3) X X ↑ H H L DI/O (0) Counter Reset to Address 0 An X ↑ L H H DI/O (n) External Address Utilized X An ↑ H H H DI/O (n) External Address Blocked—Counter Disabled An ↑ H DI/O (n+1) Counter Enable—Internal Address Generation X (4) (5) H L Mode 3493 tbl 03 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH . 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB. Recommended Operating Recommended DC Operating (1,2) Temperature and Supply Voltage Conditions Grade Commercial Industrial Symbol Ambient Temperature GND Vcc 0OC to +70OC 0V 5.0V + 10% -40OC to +85OC 0V 5.0V + 10% Parameter VCC Supply Voltage GND Ground VIH Input High Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 ____ (1) 6.0 V 3493 tbl 04 NOTES: 1. This is the parameter TA. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office. Commercial & Industrial Unit Terminal Voltage with Respect to GND -0.5 to +7.0 V TBIAS Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -55 to +125 o C IOUT DC Output Current VTERM(2) Rating Input Low Voltage -0.5 ____ 0.8 Symbol CIN COUT(3) V 3493 tbl 05 NOTES: 1. VTERM must not exceed VCC + 10%. 2. VIL > -1.5V for pulse width less than 10ns. Capacitance Absolute Maximum Ratings(1) Symbol VIL (2) (TA = +25°C, f = 1.0MHz) Parameter(1) Input Capacitance Output Capacitance Conditions(2) Max. Unit VIN = 3dV 9 pF V OUT = 3dV 10 pF 3493 tbl 07 50 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. mA 3493 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%. 4 6.42 IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (VCC = 5.0V ± 10%) 709269S/L Symbol Parameter Test Conditions (1) Min. Max. Unit 10 µA |ILI| Input Leakage Current VCC = 5.5V, VIN = 0V to V CC ___ |ILO| Output Leakage Current CE0 = VIH or CE1 = VIL, VOUT = 0V to V CC ___ 10 µA IOL = +4mA ___ 0.4 V 2.4 ___ V VOL VOH Output Low Voltage Output High Voltage IOH = -4mA 3493 tbl 08 NOTE: 1. At VCC < 2.0V input leakages are undefined. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6,7) (VCC = 5V ± 10%) 709269X9 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Test Condition CEL and CER= VIL Outputs Open f = fMAX(1) CEL = CER = VIH f = fMAX(1) Version 709269X12 Com'l Only 709269X15 Com'l Only Typ.(4) Max. Typ.(4) Max. Typ. (4) Max. Unit mA COM'L S L 210 210 390 350 200 200 345 305 190 190 325 285 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 50 50 135 115 50 50 110 90 50 50 110 90 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ CE"A" = VIL and CE"B" = VIH(3) Active Port Outputs Open, f=fMAX(3) COM'L S L 140 140 270 240 130 130 230 200 120 120 220 190 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ Both Ports CER and CEL > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(2) COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 130 130 245 225 120 120 205 185 110 110 195 175 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX(1) mA mA mA mA 3493 tbl 09 NOTES: 1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC , using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VCC = 5V, T A = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ). 5. CE X = V IL means CE 0X = V IL and CE1X = VIH CE X = VIH means CE0X = VIH or CE1X = VIL CE X < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CE X > V CC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. 6. 'X' in part number indicates power rating (S or L). 7. Industrial temperature: for specific speeds, packages and powers contact your sales office. 6.42 5 IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1,2 and 3 3493 tbl 10 5V 5V 893Ω 893Ω DATAOUT DATAOUT 30pF 347Ω 347Ω 5pF* , 3493 drw 03 3493 drw 04 Figure 2. Output Test Load (For tCKLZ , tCKHZ, tOLZ , and tOHZ ). *Including scope and jig. Figure 1. AC Output Test load. 8 7 - 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance 6 tCD1, tCD2 (Typical, ns) 5 4 3 2 1 0 -1 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 3493 drw 05 Figure 3. Typical Output Derating (Lumped Capacitive Load). 6 6.42 , IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3,4,5) (VCC = 5V ± 10%, TA = 0°C to +70°C) 709269X 9 Com'l Only Sym bol tCY C 1 Parameter Clo ck Cycle Tim e (Flo w-Thro ug h) (2) (2) 709269X 12 Com'l Only 709269X 15 Com'l Only Min. Max. Min. Max. Min. Max. Unit 25 ____ 30 ____ 35 ____ ns ns 15 ____ 20 ____ 25 ____ tCH1 Clo ck Hig h Tim e (Flo w-Thro ug h) (2) 12 ____ 12 ____ 12 ____ ns tCL 1 Clo ck Lo w Tim e (F lo w-Thro ug h) (2) 12 ____ 12 ____ 12 ____ ns 6 ____ 8 ____ 10 ____ ns 6 ____ 8 ____ 10 ____ ns tCY C 2 tCH2 tCL 2 Clo ck Cycle Tim e (P ip e line d ) Clo ck Hig h Tim e (P ip e line d ) Clo ck Lo w Tim e (2) (P ip e line d ) (2) tR Clo ck Rise Tim e ____ 3 ____ 3 ____ 3 ns tF Clo ck F all Tim e ____ 3 ____ 3 ____ 3 ns 4 ____ 4 ____ 4 ____ ns 1 ____ 1 ____ ns 4 ____ 4 ____ ns ns tS A A d d re ss S e tup Tim e tHA A d d re ss Ho ld Tim e 1 ____ tS C Chip E nab le S e tup Tim e 4 ____ 1 ____ 1 ____ 1 ____ 4 ____ 4 ____ ns 1 ____ 1 ____ ns ns tHC Chip E nab le Ho ld Tim e tS B B y te E nab le S e tup Tim e 4 ____ tHB B yte E nab le Ho ld Tim e 1 ____ 4 ____ 4 ____ 4 ____ 1 ____ 1 ____ ns 4 ____ 4 ____ ns 1 ____ 1 ____ ns ns tS W R/W S e tup Tim e tHW R/W Ho ld Tim e 1 ____ tS D Inp ut Data S e tup Tim e 4 ____ 1 ____ 4 ____ 4 ____ 4 ____ 1 ____ 1 ____ ns 4 ____ 4 ____ ns 1 ____ 1 ____ ns ns tHD Inp ut Data Ho ld Tim e tSA D ADS S e tup Tim e tHA D ADS Ho ld Tim e 1 ____ tSCN CNTEN S e tup Tim e 4 ____ tHCN CNTEN Ho ld Tim e 1 ____ tS RS T CNTRST S e tup Tim e 4 ____ 4 ____ 4 ____ tHRS T CNTRST Ho ld Tim e 1 ____ 1 ____ 1 ____ ns tOE Outp ut E nab le to Data Valid ____ 12 ____ 12 ____ 15 ns tOL Z Outp ut E nab le to O utp ut Lo w-Z(1) 2 ____ 2 ____ 2 ____ ns tO HZ Outp ut E nab le to O utp ut Hig h-Z (1) 1 7 1 7 1 7 ns tCD1 Clo ck to Data Valid (Flo w-Thro ug h)(2) ____ 20 ____ 25 ____ 30 ns tCD2 Clo ck to Data Valid (P ip e line d )(2) ____ 9 ____ 12 ____ 15 ns 2 ____ 2 ____ 2 ____ ns tDC Data Outp ut Ho ld A fte r Clo ck Hig h tCK H Z Clo ck Hig h to Outp ut Hig h-Z (1) 2 9 2 9 2 9 ns tCKL Z Clo ck Hig h to Outp ut Lo w-Z(1) 2 ____ 2 ____ 2 ____ ns Port-to-P ort Delay tCW D D W rite P o rt Clo ck Hig h to Re ad Data De lay ____ 40 ____ 40 ____ 50 ns tCCS Clo ck-to -Clo c k S e tup Tim e ____ 15 ____ 15 ____ 20 ns 3 493 tb l 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = V IH. Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPEX. 4. 'X' in part number indicates power rating (S or L). 5. Industrial temperature: for specific speeds, packages and powers contact your sales office. 6.42 7 IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Flow-through Output on Either Port (FT/PIPEX = VIL)(3) tCYC1 tCH1 tCL1 CLK CE0 tSC tSC tHC tHC (4) CE1 tSB tHB UB, LB R/W tHB tSB tSW tHW tSA tHA (5) ADDRESS An An + 1 An + 2 tCD1 tCKHZ Qn DATAOUT tCKLZ An + 3 tDC Qn + 1 (1) tOHZ (1) Qn + 2 (1) tOLZ tDC (1) (2) OE tOE 3493 drw 06 Timing Waveform of Read Cycle for Pipelined Operation on Either Port (FT/PIPEX = VIH)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC tSC tHC tHC (4) CE1 tSB tSB tHB R/W (5) ADDRESS tHB (6) UB, LB tSW tHW tSA tHA An An + 1 (1 Latency) An + 2 tDC tCD2 DATAOUT Qn tCKLZ An + 3 Qn + 1 Qn + 2 (6) (1) tOHZ (1) tOLZ (1) (2) OE tOE 3493 drw 07 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-impedance state) by CE0 = VIH , CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-impedance state). 8 6.42 IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of a Multi-device Pipelined Read(1,2) tCH2 tCYC2 tCL2 CLK tSA ADDRESS(B1) CE0(B1) tHA A0 tSC tHC tSC tHC tCD2 DATAOUT(B1) A0 tSC tCD2 Q3 tCKLZ (3) tCKHZ (3) tHA A6 A5 A4 A3 A2 A1 tSC CE0(B2) tCKHZ Q1 tDC tDC ADDRESS(B2) (3) tCD2 Q0 tSA A6 A5 A4 A3 A2 A1 tHC tHC (3) tCD2 DATAOUT(B2) tCKLZ (3) tCKHZ Q2 tCD2 Q4 tCKLZ (3) 3493 drw 08 Timing Waveform of Left Port Write to Flow-through Right Port Read(4,5) CLK L tSW tHW tSA tHA R/W L ADDRESS L tSD DATAIN L NO MATCH MATCH tHD VALID tCCS (6) CLK R tCD1 R/W R ADDRESS R tSW tHW tSA tHA NO MATCH MATCH tCWDD (6) tCD1 DATAOUT R VALID VALID tDC tDC 3493 drw 09 NOTES: 1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one 709269 for this waveform, and are set up for depth expansion in this example. ADDRESS(B1) = ADDRESS (B2) in this situation. 2. UB, LB, OE, and ADS = VIL; CE1(B1), CE 1(B2), R/W, CNTEN, and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. t CWDD does not apply in this case. 6.42 9 IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC tHC tSB tHB CE1 UB, LB tSW tHW R/W (4) ADDRESS tSW tHW An tSA tHA An +1 An + 2 An + 3 An + 2 An + 4 tSD tHD DATAIN Dn + 2 tCD2 (2) tCKHZ (1) tCKLZ (1) tCD2 Qn + 3 Qn DATAOUT READ NOP (5) WRITE READ 3493 drw 10 Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3) tCH2 tCYC2 tCL2 CLK CE0 tSC tHC tSB tHB CE1 UB, LB tSW tHW R/W (4) ADDRESS tSW tHW An tSA tHA An +1 An + 2 tSD DATAIN Dn + 2 tCD2 (2) An + 3 An + 4 An + 5 tHD Dn + 3 tCKLZ(1) tCD2 Qn DATAOUT Qn + 4 tOHZ(1) OE READ WRITE READ 3493 drw 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 10 6.42 IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Flow-through Read-to-Write-to-Read (OE = VIL)(3) tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSB tHB UB, LB tSW tHW R/W tSW tHW (4) ADDRESS tSA An tHA An +1 An + 2 An + 4 An + 3 An + 2 tSD tHD DATAIN Dn + 2 tCD1 (2) tCD1 Qn DATAOUT tCD1 tCD1 Qn + 3 Qn + 1 tDC tCKHZ (5) NOP READ (1) tCKLZ WRITE (1) tDC READ 3493 drw 12 Timing Waveform of Flow-through Read-to-Write-to-Read (OE Controlled)(3) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC tSB tHB CE1 UB, LB tSW tHW R/W tSW tHW (4) ADDRESS tSA An tHA An +1 An + 2 DATAIN Dn + 3 Dn + 2 (2) DATAOUT An + 3 An + 4 An + 5 tSD tHD tDC tCD1 Qn tOE tCD1 (1) tOHZ (1) tCKLZ tCD1 Qn + 4 tDC OE READ WRITE READ 3493 drw 13 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals. 3. CE 0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH . 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 11 IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance(1) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD CNTEN tSCN tHCN tCD2 DATAOUT Qx - 1(2) Qn + 2(2) Qn + 1 Qn Qx Qn + 3 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 3493 drw 14 Timing Waveform of Flow-through Read with Address Counter Advance(1) tCH1 tCYC1 tCL1 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tCD1 DATAOUT Qx(2) Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 3493 drw 15 NOTES: 1. CE 0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 12 6.42 IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs)(1) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL(3) ADDRESS An(7) An + 2 An + 1 An + 4 An + 3 tSAD tHAD ADS CNTEN tSD tHD Dn + 1 Dn DATA IN WRITE EXTERNAL ADDRESS Dn + 1 Dn + 4 Dn + 3 Dn + 2 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 3493 drw 16 Timing Waveform of Counter Reset (Pipelined Outputs)(2) tCH2 tCYC2 tCL2 CLK tSA tHA (4) An ADDRESS INTERNAL(3) ADDRESS Ax (6) 0 1 An + 1 An + 2 An + 1 An tSW tHW R/W ADS tSAD tHAD CNTEN tSCN tHCN tSRST tHRST CNTRST tSD tHD D0 DATA IN (5) Q1 Q0 DATAOUT COUNTER RESET (6) WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 READ ADDRESS n Qn READ ADDRESS n+1 3493 drw 17 NOTES: 1. CE 0, UB, LB, and R/W = V IL; CE1 and CNTRST = VIH. 2. CE 0, UB, LB = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR 0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this cycle. 6.42 13 IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Functional Description Depth and Width Expansion The IDT709269 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT709269's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 LOW and CE1 HIGH to reactivate the outputs. The IDT709269 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The 709269 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 32-bit or wider applications. A14 CE0 IDT709269 CE1 CE1 CE1 VCC IDT709269 VCC CE1 CE0 CE0 Control Inputs CE0 Control Inputs Control Inputs IDT709269 IDT709269 Control Inputs 3493 drw 18 Figure 4. Depth and Width Expansion with IDT709269 14 6.42 , CNTRST CLK ADS CNTEN R/W OE LB, UB IDT709269S/L High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX A 99 A A Device Type Power Speed Package Process/ Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PF 100-pin TQFP (PN100-1) 9 12 15 Commercial Only Commercial Only Commercial Only S L Standard Power Low Power Speed in nanoseconds 709269 256K (16K x 16-Bit) Synchronous Dual-Port RAM 3493 drw 19 NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. Preliminary Datasheet: "PRELIMINARY' datasheets contain descriptions for products that are in early release. Datasheet Document History 1/12/99: 6/7/99: 4/17/00: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Page 14 Added Depth & Width Expansion note Changed drawing format Page 4 Deleted note 6 for Table II Replaced IDT logo Added FT/PIPE to left port. Changed ±200mV to 0mV in notes CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 15 for Tech Support: 831-754-4613 [email protected]