IDT 89HPES16T4G2ZABX

89HPES16T4G2
Data Sheet
16-Lane 4-Port
Gen2 PCI Express® Switch
Advance Information*
®
Device Overview
Features
High Performance PCI Express Switch
– Sixteen 5 Gbps Gen2 PCI Express lanes
– Four switch ports
• One x4 upstream port
• Three x4 downstream ports
– Low latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 2.0 compliant
Block Diagram
4-Port Switch Core / 16 PCI Express Lanes
Frame Buffer
Port
Arbitration
Route Table
Scheduler
Transaction Layer
Transaction Layer
Transaction Layer
Transaction Layer
Data Link Layer
Data Link Layer
Data Link Layer
Data Link Layer
Multiplexer / Demultiplexer
Multiplexer / Demultiplexer
Multiplexer / Demultiplexer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
SerDes
SerDes
(Port 0)
(Port 2)
(Port 4)
(Port 6)
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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© 2007 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
September 4, 2007
DSC 6928
Advance Information
The 89HPES16T4G2 is a member of IDT’s PRECISE™ family of PCI
Express® switching solutions. The PES16T4G2 is a 16-lane, 4-port
Gen2 peripheral chip that performs PCI Express Base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and up to
three downstream ports and supports switching between downstream
ports.
◆
Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Ability to load device configuration from serial EEPROM
◆ Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆
Highly Integrated Solution
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates sixteen 5 Gbps embedded SerDes with 8b/10b
encoder/decoder (no separate transceivers needed)
• Receive equalization (RxEQ)
◆
Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC motherboards
– Supports Hot-Swap
◆
IDT 89HPES16T4G2 Data Sheet
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Support PCI Express Power Management Interface specification (PCI-PM 2.0)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI) supporting active link state
◆ Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
◆
Sixteen General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
◆
Packaged in a 23mm x 23mm, 288-ball BGA with 1mm
ball spacing
◆
Utilizing standard PCI Express interconnect, the PES16T4G2
provides the most efficient fan-out solution for applications requiring high
throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 16 GBps (128 Gbps) of aggregated,
full-duplex switching capacity through 16 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base
Specification, Revision 2.0.
The PES16T4G2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 2.0. The PES16T4G2 can operate either as a store and
forward or cut-through switch and is designed to switch memory and I/O
transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
Processor
Memory
Memory
Memory
Memory
North
Bridge
x4
PES16T4G2
x4
x4
x4
PCI Express
Slot
I/O
10GbE
I/O
10GbE
I/O
SATA
I/O
SATA
Figure 2 I/O Expansion Application
SMBus Interface
The PES16T4G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the
PES16T4G2, allowing every configuration register in the device to be
read or written by an external agent. The master interface allows the
default configuration register values of the PES16T4G2 to be overridden following a reset with values programmed in an external serial
EEPROM. The master interface is also used by an external Hot-Plug I/O
expander.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
Bit
Slave
SMBus
Address
Master
SMBus
Address
1
SSMBADDR[1]
MSMBADDR[1]
2
SSMBADDR[2]
MSMBADDR[2]
3
SSMBADDR[3]
MSMBADDR[3]
4
0
MSMBADDR[4]
5
SSMBADDR[5]
1
6
1
0
7
1
1
Table 1 Master and Slave SMBus Address Assignment
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*Notice: The information in this document is subject to change without notice
September 4, 2007
Advance Information
Product Description
Processor
IDT 89HPES16T4G2 Data Sheet
As shown in Figure 2, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
2(a), the master and slave SMBuses are tied together and the PES16T4G2 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES16T4G2 registers supports SMBus arbitration. In some systems, this SMBus
master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To
support these systems, the PES16T4G2 may be configured to operate in a split configuration as shown in Figure 2(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES16T4G2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of
the serial EEPROM.
Serial
EEPROM
...
Other
SMBus
Devices
PES16T4G2
SSMBCLK
SSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
MSMBCLK
MSMBDAT
Processor
SMBus
Master
...
Other
SMBus
Devices
Serial
EEPROM
(b) Split Configuration and Management Buses
(a) Unified Configuration and Management Bus
Figure 2 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES16T4G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES16T4G2
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES16T4G2 generates an SMBus transaction to the I/O expander with the
new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN
input pin (alternate function of GPIO) of the PES16T4G2. In response to an I/O expander interrupt, the PES16T4G2 generates an SMBus transaction
to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES16T4G2 provides 16 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
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September 4, 2007
Advance Information
PES16T4G2
Processor
SMBus
Master
IDT 89HPES16T4G2 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES16T4G2. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
PE0RP[3:0]
PE0RN[3:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PE0TP[3:0]
PE0TN[3:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0. Port 0 is the upstream port.
PE2RP[3:0]
PE2RN[3:0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE2TP[3:0]
PE2TN[3:0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2.
PE4RP[3:0]
PE4RN[3:0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE4TP[3:0]
PE4TN[3:0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4.
PE6RP[3:0]
PE6RN[3:0]
I
PCI Express Port 6 Serial Data Receive. Differential PCI Express receive
pairs for port 6.
PE6TP[3:0]
PE6TN[3:0]
O
PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for port 6.
PEREFCLKP[0]
PEREFCLKN[0]
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
This pin should be static and not change following the negation of
PERSTN.
Advance Information
Note: In the PES16T4G2, the three downstream ports are labeled port 2, port 4, and port 6.
Table 2 PCI Express Interface Pins
Signal
Type
Name/Description
MSMBADDR[4:1]
I
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
Table 3 SMBus Interface Pins (Part 1 of 2)
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September 4, 2007
IDT 89HPES16T4G2 Data Sheet
Signal
Type
Name/Description
SSMBADDR[5,3:1]
I
SSMBCLK
I/O
Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus.
SSMBDAT
I/O
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
Table 3 SMBus Interface Pins (Part 2 of 2)
Type
Name/Description
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2.
GPIO[1]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4.
GPIO[2]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O expander interrupt 0 input.
GPIO[3]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[4]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN2
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 2 input
GPIO[5]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[6]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[7]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
GPIO[9]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[10]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Advance Information
Signal
Table 4 General Purpose I/O Pins (Part 1 of 2)
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September 4, 2007
IDT 89HPES16T4G2 Data Sheet
Signal
Type
Name/Description
GPIO[11]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P6RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 6.
GPIO[12]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[13]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[14]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[15]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Signal
Type
CCLKDS
I
Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be overridden by modifying the SCLK bit in each downstream port’s PCIELSTS register.
CCLKUS
I
Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the P0_PCIELSTS register.
MSMBSMODE
I
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
PERSTN
I
Fundamental Reset. Assertion of this signal resets all logic inside
PES16T4G2 and initiates a PCI Express fundamental reset.
RSTHALT
I
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES16T4G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
SWMODE[2:0]
I
Switch Mode. These configuration pins determine the PES16T4G2 switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0x7 Reserved
These pins should be static and not change following the negation of
PERSTN.
Advance Information
Table 4 General Purpose I/O Pins (Part 2 of 2)
Name/Description
Table 5 System Pins
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September 4, 2007
IDT 89HPES16T4G2 Data Sheet
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Advance Information
Signal
Table 6 Test Pins
Signal
Type
Name/Description
REFRES0
I/O
Port 0 External Reference Resistor. Provides a reference for the Port 0
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground.
REFRES2
I/O
Port 2 External Reference Resistor. Provides a reference for the Port 2
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground.
REFRES4
I/O
Port 4 External Reference Resistor. Provides a reference for the Port 4
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground.
REFRES6
I/O
Port 6 External Reference Resistor. Provides a reference for the Port 6
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground.
VDDCORE
I
Core VDD. Power supply for core logic.
VDDI/O
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPEA
I
PCI Express Analog Power. Serdes analog power supply (1.0V).
VDDPEHA
I
PCI Express Analog High Power. Serdes analog power supply (2.5V).
VDDPETA
I
PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
VSS
I
Ground.
Table 7 Power, Ground, and SerDes Resistor Pins
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September 4, 2007
IDT 89HPES16T4G2 Data Sheet
Pin Characteristics
Note: Some input pads of the PES16T4G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
PCI Express Interface
SMBus
Type
Buffer
I/O
Type
PE0RN[3:0]
I
CML
Serial Link
PE0RP[3:0]
I
PE0TN[3:0]
O
PE0TP[3:0]
O
PE2RN[3:0]
I
PE2RP[3:0]
I
PE2TN[3:0]
O
PE2TP[3:0]
O
PE4RN[3:0]
I
PE4RP[3:0]
I
PE4TN[3:0]
O
PE4TP[3:0]
O
PE6RN[3:0]
I
PE6RP[3:0]
I
PE6TN[3:0]
O
PE6TP[3:0]
O
PEREFCLKN[0]
I
PEREFCLKP[0]
I
REFCLKM
I
LVTTL
Input
pull-down
I
LVTTL
Input
pull-up
Pin Name
MSMBADDR[4:1]
Internal
Resistor1
Diff. Clock
Input
Notes
Refer to Table 9
MSMBCLK
I/O
STI2
pull-up on board
MSMBDAT
I/O
STI
pull-up on board
I
Input
SSMBADDR[5,3:1]
pull-up
SSMBCLK
I/O
STI
pull-up on board
SSMBDAT
I/O
STI
pull-up on board
General Purpose I/O
GPIO[15:0]
I/O
LVTTL
STI,
High Drive
pull-up
System Pins
CCLKDS
I
LVTTL
Input
pull-up
CCLKUS
I
Input
pull-up
MSMBSMODE
I
Input
pull-down
PERSTN
I
STI
RSTHALT
I
Input
pull-down
SWMODE[2:0]
I
Input
pull-down
Table 8 Pin Characteristics (Part 1 of 2)
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September 4, 2007
Advance Information
Function
IDT 89HPES16T4G2 Data Sheet
Type
Buffer
I/O
Type
Internal
Resistor1
JTAG_TCK
I
LVTTL
STI
pull-up
JTAG_TDI
I
STI
pull-up
JTAG_TDO
O
JTAG_TMS
I
STI
pull-up
JTAG_TRST_N
I
STI
pull-up
Function
EJTAG / JTAG
SerDes Reference
Resistors
Pin Name
REFRES0
I/O
REFRES2
I/O
REFRES4
I/O
REFRES6
I/O
Notes
Analog
Table 8 Pin Characteristics (Part 2 of 2)
1. Internal
Schmitt Trigger Input (STI).
Advance Information
2.
resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down.
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September 4, 2007
IDT 89HPES16T4G2 Data Sheet
Logic Diagram — PES16T4G2
Reference Clock
Frequency Selection
PEREFCLKP[0]
PEREFCLKN[0]
REFCLKM
PE0TP[0]
PE0TN[0]
PE0RP[0]
PE0RN[0]
PE0RP[3]
PE0RN[3]
PE0TP[3]
PE0TN[3]
PCI Express
Switch
SerDes Input
Port 2
PE2RP[0]
PE2RN[0]
PE2TP[0]
PE2TN[0]
PE2RP[3]
PE2RN[3]
PE2TP[3]
PE2TN[3]
PCI Express
Switch
SerDes Input
Port 4
PE4RP[0]
PE4RN[0]
PE4TP[0]
PE4TN[0]
PE4RP[3]
PE4RN[3]
PE4TP[3]
PE4TN[3]
PCI Express
Switch
SerDes Input
Port 6
PE6RP[0]
PE6RN[0]
PE6TP[0]
PE6TN[0]
...
...
...
...
...
System
Pins
...
Slave
SMBus Interface
...
Master
SMBus Interface
...
PCI Express
Switch
SerDes Input
Port 0
PE6RP[3]
PE6RN[3]
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
MSMBSMODE
CCLKDS
CCLKUS
RSTHALT
PERSTN
SWMODE[2:0]
PE6TP[3]
PE6TN[3]
PES16T4G2
16
4
GPIO[15:0]
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
4
REFRES0
REFRES2
REFRES4
REFRES6
PCI Express
Switch
SerDes Output
Port 0
PCI Express
Switch
SerDes Output
Port 2
PCI Express
Switch
SerDes Output
Port 4
PCI Express
Switch
SerDes Output
Port 6
General Purpose
I/O
JTAG Pins
SerDes
Reference
Resistors
VDDCORE
3
VDDI/O
VDDPEA
VDDPEHA
Power/Ground
VSS
VDDPETA
Figure 3 PES16T4G2 Logic Diagram
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September 4, 2007
Advance Information
Reference
Clocks
IDT 89HPES16T4G2 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Description
Condition
Min
Typical
Max
Unit
100
1251
MHz
RefclkFREQ
Input reference clock frequency range
TC-RISE
Rising edge rate
Differential
0.6
4
V/ns
TC-FALL
Falling edge rate
Differential
0.6
4
V/ns
VIH
Differential input high voltage
Differential
+150
VIL
Differential input low voltage
Differential
VCROSS
Absolute single-ended crossing point
voltage
Single-ended
VCROSS-DELTA
Variation of VCROSS over all rising clock
edges
Single-ended
VRB
Ring back voltage margin
Differential
-100
TSTABLE
Time before VRB is allowed
Differential
500
TPERIOD-AVG
Average clock period accuracy
-300
2800
ppm
TPERIOD-ABS
Absolute period, including spread-spectrum and jitter
9.847
10.203
ns
TCC-JITTER
Cycle to cycle jitter
150
ps
VMAX
Absolute maximum input voltage
+1.15
V
VMIN
Absolute minimum input voltage
-0.3
Duty Cycle
Duty cycle
40
Rise/Fall Matching
Single ended rising Refclk edge rate versus falling Refclk edge rate
ZC-DC
Clock source output DC impedance
mV
+250
-150
mV
+550
mV
+140
mV
+100
mV
ps
V
60
%
20
%
40
Ω
60
Table 9 Input Clock Requirements
1.
The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
AC Timing Characteristics
Parameter
Gen 1
Description
Gen 2
Min1
Typ1
Max1
Min1
Typ1
Max1
399.88
400
400.12
199.94
200
200.06
Units
PCIe Transmit
UI
Unit Interval
TTX-EYE
Minimum Tx Eye Width
TTX-EYE-MEDIAN-toMAX-JITTER
Maximum time between the jitter median and maximum deviation from the median
TTX-RISE, TTX-FALL
TX Rise/Fall Time: 20% - 80%
TTX- IDLE-MIN
Minimum time in idle
0.75
0.75
0.125
ps
UI
UI
0.125
0.15
UI
20
20
UI
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
11 of 32
September 4, 2007
Advance Information
Parameter
IDT 89HPES16T4G2 Data Sheet
Parameter
TTX-IDLE-SET-TO-
Gen 1
Description
Min1
Typ1
Gen 2
Max1
Min1
Typ1
Max1
Units
8
8
ns
IDLE
Maximum time to transition to a valid Idle after sending
an Idle ordered set
TTX-IDLE-TO-DIFF-
Maximum time to transition from valid idle to diff data
8
8
ns
1.3
1.3
ns
DATA
TTX-SKEW
Transmitter data skew between any 2 lanes
TMIN-PULSED
Minimum Instantaneous Lone Pulse Width
TMEAS-HPF
Transmit Jitter Measurement Filter
TTX-HF-DJ-DD
Transmitter Deterministic Jitter > 1.5MHz Bandwidth
NA
0.15
UI
TRF-MISMATCH
Rise/Fall Time Differential Mismatch
NA
0.1
UI
200.06
ps
NA
0.9
HPF: 1.5MHz
UI
HPF: 1.0MHz
MHz
UI
Unit Interval
399.88
400
400.12
TRX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance)
TRX-EYE-MEDIUM TO
Max time between jitter median & max deviation
0.3
TRX-SKEW
Lane to lane input skew
20
TRX-HF-RMS
1.5 — 100 MHz RMS jitter
TRX-HF-DJ-DD
0.4
199.94
0.4
UI
UI
MAX JITTER
8
ns
NA
4.2
ps
Maximum tolerable DJ by the receiver
NA
8.8
ps
TRX-LF-RMS
10 KHz to 1.5 MHz RMS jitter
NA
4.2
ps
TRX-MIN-PULSE
Minimum receiver instantaneous eye width
NA
0.6
UI
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0
Signal
Symbol
Reference
Min Max Unit
Edge
Timing
Diagram
Reference
GPIO
GPIO[15:0]1
Tpw2
None
50
—
ns
Table 11 GPIO AC Timing Characteristics
1.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
2.
The values for this symbol were determined by calculation, not by testing.
12 of 32
September 4, 2007
Advance Information
PCIe Receive
IDT 89HPES16T4G2 Data Sheet
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
Tper_16a
none
50.0
—
ns
See Figure 4.
10.0
25.0
ns
2.4
—
ns
1.0
—
ns
—
20
ns
—
20
ns
25.0
—
ns
JTAG
JTAG_TCK
Thigh_16a,
Tlow_16a
JTAG_TMS1,
JTAG_TDI
Tsu_16b
JTAG_TCK rising
Thld_16b
JTAG_TDO
Tdo_16c
JTAG_TCK falling
Tdz_16c2
JTAG_TRST_N
Tpw_16d2
none
Table 12 JTAG AC Timing Characteristics
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determined by calculation, not by testing.
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
Thld_16b
Tsu_16b
JTAG_TDI
Thld_16b
Tsu_16b
JTAG_TMS
Tdo_16c
Tdz_16c
JTAG_TDO
Tpw_16d
JTAG_TRST_N
Figure 4 JTAG AC Timing Waveform
13 of 32
September 4, 2007
Advance Information
1.
IDT 89HPES16T4G2 Data Sheet
Recommended Operating Supply Voltages
Symbol
Parameter
Minimum
Typical
Maximum
Unit
0.9
1.0
1.1
V
VDDCORE
Internal logic supply
VDDI/O
I/O supply except for SerDes LVPECL/CML
3.135
3.3
3.465
V
PCI Express Analog Power
0.95
1.0
1.1
V
VDDPEHA
PCI Express Analog High Power
2.25
2.5
2.75
V
VDDPETA
PCI Express Transmitter Analog Voltage
0.95
1.0
1.1
V
VSS
Common ground
0
0
0
V
1
VDDPEA
2
2.
Table 13 PES16T4G2 Operating Voltages
VDDPEA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC value.
VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value.
Power-Up/Power-Down Sequence
During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDI/O at all times. There are no other power-up sequence requirements for the various operating supply voltages.
The power-down sequence can occur in any order.
Recommended Operating Temperature
Grade
Temperature
Commercial
0°C to +70°C Ambient
Table 14 PES16T4G2 Operating Temperatures
14 of 32
September 4, 2007
Advance Information
1.
IDT 89HPES16T4G2 Data Sheet
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13 (and also listed below).
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe Termination Supply
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
3.3V
Max
3.465V
Typ
Power
Max
Power
mA
852
1136
518
688
270
361
362
483
10
10
2.4W
3.5W
Watts
0.85
1.25
0.51
0.75
0.67
0.99
0.36
0.53
0.03
.034
mA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Watts
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
4/4/4/4
4/4/1/1
I/O Supply
Total
Table 15 PES16T4G2 Power Consumption
Thermal Considerations
This section describes thermal considerations for the PES16T4G2 (23mm2 SBGA288 package). The data in Table 16 below contains information
that is relevant to the thermal performance of the PES16T4G2 switch.
Symbol
TJ(max)
TA(max)
Parameter
Value
Units
Conditions
125
oC
Maximum
70
oC
Maximum
Junction Temperature
Ambient Temperature
θJC
Thermal Resistance, Junction-to-Case
1.1
oC/W
P
Power Dissipation of the Device
3.5
Watts
Maximum
Table 16 Thermal Specifications for PES16T4G2, 23x23 mm SBGA288 Package
Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value
specified in Table 16. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be
maintained below the value determined by the formula:
θJA = (TJ(max) - TA(max))/P
Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to
achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value
provided in Table 16), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the
circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 8 or more
layers AND the board size is larger than 4"x12" AND airflow in excess of 0.5 m/s is available. It is strongly recommended that users perform
their own thermal analysis for their own board and system design scenarios.
15 of 32
September 4, 2007
Advance Information
Number of active
Lanes per Port
IDT 89HPES16T4G2 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13.
Note: See Table 8, Pin Characteristics, for a complete I/O listing.
Parameter
Description
Min1
Serial Link
Typ1
Gen 2
Max1
Min1
Typ1
Unit
Conditions
Max1
PCIe Transmit
VTX-DIFFp-p
Differential peak-to-peak output
voltage
800
1200
800
1200
mV
VTX-DIFFp-p-LOW
Low-Drive Differential Peak to
Peak Output Voltage
400
1200
400
1200
mV
VTX-DE-RATIO-
De-emphasized differential output voltage
-3
-4
-3.0
-3.5
-4.0
dB
-5.5
-6.0
-6.5
dB
3.6
V
3.5dB
VTX-DE-RATIO6.0dB
De-emphasized differential output voltage
VTX-DC-CM
DC Common mode voltage
VTX-CM-ACP
RMS AC peak common mode
output voltage
20
VTX-CM-DC-
Abs delta of DC common mode
voltage between L0 and idle
100
100
mV
Abs delta of DC common mode
voltage between D+ and D-
25
25
mV
delta
VTX-Idle-DiffP
Electrical idle diff peak output
20
20
mV
VTX-RCV-Detect
Voltage change during receiver
detection
600
600
mV
RLTX-DIFF
Transmitter Differential Return
loss
10
10dB:
0.05 1.25GHz
8dB:
1.25 2.5GHz
dB
RLTX-CM
Transmitter Common Mode
Return loss
6
6
dB
ZTX-DIFF-DC
DC Differential TX impedance
80
120
Ω
VTX-CM-ACpp
Peak-Peak AC Common
100
mV
VTX-DC-CM
Transmit Driver DC Common
Mode Voltage
3.6
V
600
mV
active-idle-delta
VTX-CM-DC-line-
NA
0
3.6
100
Transmitter Short Circuit Current
Limit
mV
120
NA
0
3.6
VTX-RCV-DETECT The amount of voltage change
allowed during Receiver Detection
ITX-SHORT
0
0
600
0
Advance Information
I/O Type
Gen 1
90
90
mA
Table 17 DC Electrical Characteristics (Part 1 of 3)
16 of 32
September 4, 2007
IDT 89HPES16T4G2 Data Sheet
Parameter
Description
Min1
Serial Link
(cont.)
Typ1
Gen 2
Max1
Min1
1200
120
Typ1
Unit
Conditions
Max1
PCIe Receive
VRX-DIFFp-p
Differential input voltage (peakto-peak)
175
1200
mV
RLRX-DIFF
Receiver Differential Return
Loss
10
10dB:
0.05 1.25GHz
8dB:
1.25 2.5GHz
dB
RLRX-CM
Receiver Common Mode Return
Loss
6
6
dB
ZRX-DIFF-DC
Differential input impedance
(DC)
80
100
120
Refer to return loss spec
Ω
ZRX--DC
DC common mode impedance
40
50
60
40
60
Ω
ZRX-COMM-DC
Powered down input common
mode impedance (DC)
200k
350k
50k
Ω
ZRX-HIGH-IMP-
DC input CM input impedance
for V>0 during reset or power
down
50k
50k
Ω
DC input CM input impedance
for V<0 during reset or power
down
1.0k
1.0k
Ω
DC-NEG
VRX-IDLE-DET-
Electrical idle detect threshold
175
mV
150
mV
DC-POS
ZRX-HIGH-IMP-
65
175
65
Advance Information
I/O Type
Gen 1
DIFFp-p
VRX-CM-ACp
Receiver AC common-mode
peak voltage
150
VRX-CM-ACp
PCIe REFCLK
CIN
Input Capacitance
1.5
—
1.5
—
IOL
—
2.5
IOH
—
IOL
pF
—
—
2.5
—
mA
VOL = 0.4v
-5.5
—
—
-5.5
—
mA
VOH = 1.5V
—
12.0
—
—
12.0
—
mA
VOL = 0.4v
IOH
—
-20.0
—
—
-20.0
—
mA
VOH = 1.5V
Other I/Os
LOW Drive
Output
High Drive
Output
Schmitt
Trigger
Input (STI)
VIL
-0.3
—
0.8
-0.3
—
0.8
V
—
VIH
2.0
—
VDDI/O
+ 0.5
2.0
—
VDDI/O +
0.5
V
—
Input
VIL
-0.3
—
0.8
-0.3
—
0.8
V
—
VIH
2.0
—
VDDI/O
+ 0.5
2.0
—
VDDI/O +
0.5
V
—
Table 17 DC Electrical Characteristics (Part 2 of 3)
17 of 32
September 4, 2007
IDT 89HPES16T4G2 Data Sheet
I/O Type
Capacitance
Leakage
Parameter
Gen 1
Description
Gen 2
Unit
Conditions
Min1
Typ1
Max1
Min1
Typ1
Max1
CIN
—
—
8.5
—
—
8.5
pF
—
Inputs
—
—
+ 10
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK W/O
Pull-ups/downs
—
—
+ 10
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK WITH
Pull-ups/downs
—
—
+ 80
—
—
+ 80
μA
VDDI/O (max)
Table 17 DC Electrical Characteristics (Part 3 of 3)
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0.
Advance Information
1.
18 of 32
September 4, 2007
IDT 89HPES16T4G2 Data Sheet
Package Pinout — 288-BGA Signal Pinout for PES16T4G2
The following table lists the pin numbers and signal names for the PES16T4G2 device.
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
A1
VSS
B13
VDDPEHA
D3
PE2TP00
F21
GPIO_06
A2
VSS
B14
VSS
D4
VDDPETA
F22
PE4RN03
A3
VDDI/O
B15
VSS
D5
VDDPEA
G1
VDDCORE
A4
VDDCORE
B16
VDDPEHA
D6
VSS
G2
VDDPEHA
A5
PE6RP03
B17
VSS
D7
VDDPETA
G3
PE2TP01
A6
PE6RN03
B18
VSS
D8
VDDPEA
G4
VDDPEA
A7
VDDCORE
B19
VSS
D9
VSS
G19
VDDPETA
A8
PE6RP02
B20
REFCLKM
D10
VDDPETA
G20
PE4TP03
A9
PE6RN02
B21
GPIO_13
D11
VDDPEA
G21
GPIO_05
A10
VDDCORE
B22
VSS
D12
VSS
G22
VSS
A11
VSS
C1
SSMBCLK
D13
VDDPEA
H1
PE2RN01
A12
VSS
C2
SSMBDAT
D14
VSS
H2
VSS
A13
VDDCORE
C3
MSMBSMODE
D15
VDDPETA
H3
PE2TN01
A14
PE6RP01
C4
MSMBDAT
D16
VDDPEA
H4
VDDPETA
A15
PE6RN01
C5
MSMBADDR_4
D17
VSS
H19
VDDPEA
A16
VDDCORE
C6
PE6TN03
D18
VDDCORE
H20
VDDI/O
A17
PE6RP00
C7
PE6TP03
D19
VDDPETA
H21
GPIO_04
A18
PE6RN00
C8
VDDI/O
D20
GPIO_09
H22
PE4RP02
A19
VDDI/O
C9
PE6TN02
D21
GPIO_11
J1
PE2RP01
A20
GPIO_15
C10
PE6TP02
D22
VDDCORE
J2
VSS
A21
GPIO_14
C11
VSS
E1
PE2RN00
J3
VSS
A22
VSS
C12
VDDPEHA
E2
VSS
J4
VSS
B1
SSMBADDR_5
C13
VSS
E3
PE2TN00
J19
VSS
B2
SSMBADDR_3
C14
VSS
E4
VDDCORE
J20
PE4TN02
B3
SSMBADDR_2
C15
PE6TN01
E19
VDDPEA
J21
VDDPEHA
B4
SSMBADDR_1
C16
PE6TP01
E20
GPIO_07
J22
PE4RN02
B5
MSMBCLK
C17
VDDPEHA
E21
GPIO_08
K1
VDDCORE
B6
MSMBADDR_3
C18
PE6TN00
E22
PE4RP03
K2
VDDPEHA
B7
MSMBADDR_2
C19
PE6TP00
F1
PE2RP00
K3
VSS
B8
MSMBADDR_1
C20
GPIO_10
F2
VSS
K4
VDDPEA
B9
VDDPEHA
C21
GPIO_12
F3
VDDPEHA
K19
VDDPETA
B10
NC
C22
VDDI/O
F4
VSS
K20
PE4TP02
B11
REFRES6
D1
VSS
F19
VSS
K21
NC
B12
VSS
D2
VDDI/O
F20
PE4TN03
K22
VDDCORE
1
1
Alt
1
Table 18 PES16T4G2 288-pin Signal Pin-Out (Part 1 of 2)
19 of 32
September 4, 2007
Advance Information
Pin
IDT 89HPES16T4G2 Data Sheet
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
L1
VSS
R21
VSS
W13
VDDPETA
AA7
VDDPEHA
L2
VSS
R22
PE4RN01
W14
VSS
AA8
VSS
L3
VDDPEHA
T1
VDDCORE
W15
VDDPEA
AA9
VSS
L4
VSS
T2
JTAG_TRST_N
W16
VDDPETA
AA10
VDDPEHA
L19
VDDPEA
T3
PE2TP03
W17
VSS
AA11
VSS
L20
VSS
T4
JTAG_TDO
W18
VDDPEA
AA12
REFRES0
L21
REFRES4
T19
VDDPEA
W19
VDDPETA
AA13
NC
L22
VSS
T20
PE4TP01
W20
PE4TP00
AA14
VDDPEHA
M1
VSS
T21
VDDPEHA
W21
VDDI/O
AA15
CCLKUS
M2
REFRES2
T22
VDDCORE
W22
VSS
AA16
CCLKDS
M3
VSS
U1
PE2RN03
Y1
JTAG_TDI
AA17
SWMODE_0
M4
VDDPEA
U2
JTAG_TMS
Y2
VDDI/O
AA18
SWMODE_2
M19
VSS
U3
PE2TN03
Y3
VDDI/O
AA19
NC
M20
VDDPEHA
U4
VSS
Y4
PE0TP00
AA20
NC
M21
VSS
U19
VSS
Y5
PE0TN00
AA21
GPIO_00
1
M22
VSS
U20
VDDPEHA
Y6
VDDPEHA
AA22
GPIO_01
1
N1
VDDCORE
U21
VSS
Y7
PE0TP01
AB1
VSS
N2
NC
U22
PE4RP00
Y8
PE0TN01
AB2
VSS
N3
PE2TP02
V1
PE2RP03
Y9
VSS
AB3
VSS
N4
VDDPETA
V2
VSS
Y10
VSS
AB4
VDDCORE
N19
VDDPEA
V3
VSS
Y11
VDDPEHA
AB5
PE0RN00
N20
VSS
V4
VDDPEA
Y12
VSS
AB6
PE0RP00
N21
VDDPEHA
V19
VDDCORE
Y13
PE0TP02
AB7
VDDCORE
N22
VDDCORE
V20
PE4TN00
Y14
PE0TN02
AB8
PE0RN01
P1
PE2RN02
V21
VSS
Y15
VDDI/O
AB9
PE0RP01
P2
VDDPEHA
V22
PE4RN00
Y16
PE0TP03
AB10
VDDCORE
P3
PE2TN02
W1
JTAG_TCK
Y17
PE0TN03
AB11
PEREFCLKP0
P4
VSS
W2
VSS
Y18
SWMODE_1
AB12
PEREFCLKN0
P19
VSS
W3
VSS
Y19
PERSTN
AB13
VDDCORE
P20
VSS
W4
VDDPETA
Y20
RSTHALT
AB14
PE0RN02
P21
VSS
W5
VDDCORE
Y21
GPIO_03
AB15
PE0RP02
P22
PE4RP01
W6
VSS
Y22
GPIO_02
AB16
VDDCORE
R1
PE2RP02
W7
VDDPEA
AA1
VSS
AB17
PE0RN03
R2
VDDI/O
W8
VDDPETA
AA2
VSS
AB18
PE0RP03
R3
VDDPETA
W9
VSS
AA3
VSS
AB19
VSS
R4
VDDPEA
W10
VDDPEA
AA4
VSS
AB20
VDDI/O
R19
VDDPETA
W11
VSS
AA5
VSS
AB21
VSS
R20
PE4TN01
W12
VDDPEA
AA6
VSS
AB22
VSS
1
Table 18 PES16T4G2 288-pin Signal Pin-Out (Part 2 of 2)
20 of 32
September 4, 2007
Advance Information
Pin
IDT 89HPES16T4G2 Data Sheet
Alternate Signal Functions
Pin
GPIO
Alternate
AA21
GPIO_00
P2RSTN
AA22
GPIO_01
P4RSTN
Y22
GPIO_02
IOEXPINTN0
H21
GPIO_04
IOEXPINTN2
E20
GPIO_07
GPEN
D21
GPIO_11
P6RSTN
Table 19 PES16T4G2 Alternate Signal Functions
No Connection Pins
Advance Information
NC Pins
B10
K21
N2
AA13
AA19
AA20
Table 20 PES16T4G2 No Connection Pins
21 of 32
September 4, 2007
IDT 89HPES16T4G2 Data Sheet
VDDCore
VDDI/O
VDDPEA
VDDPEHA
VDDPETA
A4
A3
D5
B9
D4
A7
A19
D8
B13
D7
A10
C8
D11
B16
D10
A13
C22
D13
C12
D15
A16
D2
D16
C17
D19
D18
H20
E19
F3
G19
D22
R2
G4
G2
H4
E4
W21
H19
J21
K19
G1
Y2
K4
K2
N4
K1
Y3
L19
L3
R3
K22
Y15
M4
M20
R19
N1
AB20
N19
N21
W4
N22
R4
P2
W8
T1
T19
T21
W13
T22
V4
U20
W16
V19
W7
Y6
W19
W5
W10
Y11
AB4
W12
AA7
AB7
W15
AA10
AB10
W18
AA14
Advance Information
Power Pins
AB13
AB16
Table 21 PES16T4G2 Power Pins
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IDT 89HPES16T4G2 Data Sheet
Vss
Vss
Vss
Vss
A1
D17
M21
W17
A2
E2
M22
W22
A11
F2
N20
Y9
A12
F4
P4
Y10
A22
F19
P19
Y12
B12
G22
P20
AA1
B14
H2
P21
AA2
B15
J2
R21
AA3
B17
J3
U4
AA4
B18
J4
U19
AA5
B19
J19
U21
AA6
B22
K3
V2
AA8
C11
L1
V3
AA9
C13
L2
V21
AA11
C14
L4
W2
AB1
D1
L20
W3
AB2
D6
L22
W6
AB3
D9
M1
W9
AB19
D12
M3
W11
AB21
D14
M19
W14
AB22
Advance Information
Ground Pins
Table 22 PES16T4G2 Ground Pins
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September 4, 2007
IDT 89HPES16T4G2 Data Sheet
Signals Listed Alphabetically
I/O Type
Location
Signal Category
CCLKDS
I
AA16
System
CCLKUS
I
AA15
GPIO_00
I/O
AA21
GPIO_01
I/O
AA22
GPIO_02
I/O
Y22
GPIO_03
I/O
Y21
GPIO_04
I/O
H21
GPIO_05
I/O
G21
GPIO_06
I/O
F21
GPIO_07
I/O
E20
GPIO_08
I/O
E21
GPIO_09
I/O
D20
GPIO_10
I/O
C20
GPIO_11
I/O
D21
GPIO_12
I/O
C21
GPIO_13
I/O
B21
GPIO_14
I/O
A21
GPIO_15
I/O
A20
JTAG_TCK
I
W1
JTAG_TDI
I
Y1
JTAG_TDO
O
T4
JTAG_TMS
I
U2
JTAG_TRST_N
I
T2
MSMBADDR_1
I
B8
MSMBADDR_2
I
B7
MSMBADDR_3
I
B6
MSMBADDR_4
I
C5
MSMBCLK
I/O
B5
MSMBDAT
I/O
C4
I
C3
MSMBSMODE
No Connection
General Purpose Input/Output
Advance Information
Signal Name
JTAG
SMBus
System
See Table 20
PE0RN00
I
AB5
PE0RN01
I
AB8
PE0RN02
I
AB14
PCI Express
Table 23 89PES16T4G2 Alphabetical Signal List (Part 1 of 4)
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September 4, 2007
Signal Name
I/O Type
Location
Signal Category
PE0RN03
I
AB17
PCI Express (Cont.)
PE0RP00
I
AB6
PE0RP01
I
AB9
PE0RP02
I
AB15
PE0RP03
I
AB18
PE0TN00
O
Y5
PE0TN01
O
Y8
PE0TN02
O
Y14
PE0TN03
O
Y17
PE0TP00
O
Y4
PE0TP01
O
Y7
PE0TP02
O
Y13
PE0TP03
O
Y16
PE2RN00
I
E1
PE2RN01
I
H1
PE2RN02
I
P1
PE2RN03
I
U1
PE2RP00
I
F1
PE2RP01
I
J1
PE2RP02
I
R1
PE2RP03
I
V1
PE2TN00
O
E3
PE2TN01
O
H3
PE2TN02
O
P3
PE2TN03
O
U3
PE2TP00
O
D3
PE2TP01
O
G3
PE2TP02
O
N3
PE2TP03
O
T3
PE4RN00
I
V22
PE4RN01
I
R22
PE4RN02
I
J22
PE4RN03
I
F22
PE4RP00
I
U22
PE4RP01
I
P22
PE4RP02
I
H22
Advance Information
IDT 89HPES16T4G2 Data Sheet
Table 23 89PES16T4G2 Alphabetical Signal List (Part 2 of 4)
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IDT 89HPES16T4G2 Data Sheet
I/O Type
Location
Signal Category
PE4RP03
I
E22
PCI Express (Cont.)
PE4TN00
O
V20
PE4TN01
O
R20
PE4TN02
O
J20
PE4TN03
O
F20
PE4TP00
O
W20
PE4TP01
O
T20
PE4TP02
O
K20
PE4TP03
O
G20
PE6RN00
I
A18
PE6RN01
I
A15
PE6RN02
I
A9
PE6RN03
I
A6
PE6RP00
I
A17
PE6RP01
I
A14
PE6RP02
I
A8
PE6RP03
I
A5
PE6TN00
O
C18
PE6TN01
O
C15
PE6TN02
O
C9
PE6TN03
O
C6
PE6TP00
O
C19
PE6TP01
O
C16
PE6TP02
O
C10
PE6TP03
O
C7
PEREFCLKN0
I
AB12
PEREFCLKP0
I
AB11
PERSTN
I
Y19
System
REFCLKM
I
B20
PCI Express
REFRES0
I/O
AA12
SerDes Reference Resistors
REFRES2
I/O
M2
REFRES4
I/O
L21
REFRES6
I/O
B11
RSTHALT
I
Y20
Advance Information
Signal Name
System
Table 23 89PES16T4G2 Alphabetical Signal List (Part 3 of 4)
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September 4, 2007
IDT 89HPES16T4G2 Data Sheet
I/O Type
Location
Signal Category
SSMBADDR_1
I
B4
SMBus
SSMBADDR_2
I
B3
SSMBADDR_3
I
B2
SSMBADDR_5
I
B1
SSMBCLK
I/O
C1
SSMBDAT
I/O
C2
SWMODE_0
I
AA17
SWMODE_1
I
Y18
SWMODE_2
I
AA18
SMBus
System
VDDCORE, VDDI/O,
VDDPEA, VDDPEHA,
VDDPETA
See Table 21 for a listing of power pins.
VSS
See Table 22 for a listing of ground pins.
Advance Information
Signal Name
Table 23 89PES16T4G2 Alphabetical Signal List (Part 4 of 4)
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September 4, 2007
IDT 89HPES16T4G2 Data Sheet
PES16T4G2 Pinout — Top View
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
A
A
B
B
C
C
X
D
X
X
X
X
D
E
E
F
F
X
G
G
X
H
H
J
J
X
K
K
L
L
M
M
X
N
N
P
P
X
R
X
R
T
T
U
U
V
V
X
X
W
X
X
X
W
Y
Y
AA
AA
AB
AB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
VDDPETA (Transmitter Power)
Signals
VDDI/O (Power)
VDDPEA (Analog Power)
No Connect
Vss (Ground)
VDDPEHA (High Analog Power)
VDDCore (Power)
X
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Advance Information
1
IDT 89HPES16T4G2 Data Sheet
Advance Information
PES16T4G2 Package Drawing — 288-Pin BX288/BXG288
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IDT 89HPES16T4G2 Data Sheet
Advance Information
PES16T4G2 Package Drawing — Page Two
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IDT 89HPES16T4G2 Data Sheet
Revision History
May 4, 2007: Initial publication of Advanced data sheet.
Advance Information
September 4, 2007: Added values to Table 16, Thermal Specifications.
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IDT 89HPES16T4G2 Data Sheet
Ordering Information
A
AAA
NNAN
Product
Family
Operating
Voltage
Device
Family
Product
Detail
AN
AA
AAA
Generation Device
Revision
Series
Legend
A = Alpha Character
N = Numeric Character
A
Package Temp Range
Blank
Commercial Temperature
(0°C to +70°C Ambient)
BX
BX288 288-ball SBGA
BXG
BXG288 288-ball SBGA, Green
ZA
ZA revision
G2
Generation 2
16T4
16-lane, 4-port
PES
PCI Express Switch
H
1.0V +/- 0.1V Core Voltage
89
Serial Switching Product
Valid Combinations
89HPES16T4G2ZABX
288-ball SBGA package, Commercial Temperature
89HPES16T4G2ZABXG
288-ball Green SBGA package, Commercial Temperature
®
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for Tech Support:
email: [email protected]
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September 4, 2007
Advance Information
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