89HPES24NT3
Data Sheet
24-Lane 3-Port Non-Transparent
PCI Express® Switch
Preliminary Information*
®
Device Overview
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin
– Supports automatic per port link width negotiation (x8, x4, x2,
or x1)
– Static lane reversal on all ports
– Automatic polarity inversion on all lanes
– Supports locked transactions, allowing use with legacy software
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
◆ Non-Transparent Port
– Crosslink support on NTB port
– Four mapping windows supported
• Each may be configured as a 32-bit memory or I/O window
• May be paired to form a 64-bit memory window
– Interprocessor communication
• Thirty-two inbound and outbound doorbells
• Four inbound and outbound message registers
• Two shared scratchpad registers
– Allows up to sixteen masters to communicate through the nontransparent port
– No limit on the number of supported outstanding transactions
through the non-transparent bridge
– Completely symmetric non-transparent bridge operation
allows similar/same configuration software to be run
– Supports direct connection to a transparent or non-transparent
port of another switch
◆
The 89HPES24NT3 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions offering the next-generation I/O interconnect standard. The PES24NT3 is a 24-lane, 3-port peripheral chip
that performs PCI Express Base switching with a feature set optimized
for high performance applications such as servers, storage, and communications/networking. It provides high-performance switching functions
between a PCIe® upstream port, a transparent downstream port, and a
non-transparent downstream port.
With non-transparent bridging (NTB) functionality, the PES24NT3
can be used standalone or as a chipset with IDT PCIe System Interconnect Switches in multi-host and intelligent I/O applications such as
communications, storage, and blade servers where inter-domain
communication is required.
Features
◆
High Performance PCI Express Switch
– Twenty-four PCI Express lanes (2.5Gbps), three switch ports
– Delivers 96 Gbps (12 GBps) of aggregate switching capacity
– Low latency cut-through switch architecture
– Support for Max Payload size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– PCI Express Base specification Revision 1.0a compliant
Block Diagram
3-Port Switch Core
Frame Buffer
Port
Arbitration
Route Table
Scheduler
Transaction Layer
Transaction Layer
Transaction Layer
Data Link Layer
Data Link Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
...
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
SerDes
...
NonTransparent
Bridge
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
SerDes
...
Phy
Logical
Layer
SerDes
24 PCI Express Lanes
x8 Upstream Port and Two x8 Downstream Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 31
© 2007 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
April 11, 2007
DSC 6925
IDT 89HPES24NT3 Data Sheet
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates twenty-four 2.5 Gbps embedded full duplex
SerDes, 8B/10B encoder/decoder (no separate transceivers
needed)
◆
Reliability, Availability, and Serviceability (RAS) Features
– Upstream port can be dynamically swapped with non-transparent downstream port to support failover applications
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC pass-through in transparent and non-transparent ports
– Supports Hot-Swap
◆ Power Management
– Supports PCI Power Management Interface specification,
Revision 1.1 (PCI-PM)
– Unused SerDes are disabled
◆
Testability and Debug Features
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
◆ Two SMBus Interfaces
– Slave interface provides full access to all software-visible
registers by an external SMBus master
– Master interface provides connection for an optional serial
EEPROM used for initialization
– Master interface is also used by an external Hot-Plug I/O
expander
– Master and slave interfaces may be tied together so the switch
can act as both master and slave
◆ Eight General Purpose Input/Output pins
◆
Packaged in 27x27mm 420-ball BGA with 1mm ball spacing
◆
Classes (TCs) and one Virtual Channel (VC) with sophisticated
resource management. This includes round robin port arbitration, guaranteeing bandwidth allocation and/or latency for critical traffic classes in
applications such as high throughput 10 GbE I/Os, SATA controllers,
and Fibre Channel HBAs.
Switch Configuration
The PES24NT3 is a three port switch that contains 24 PCI Express
lanes. Each of the three ports is statically allocated 8 lanes with ports
labeled as A, B and C. Port A is the upstream port, port B is the transparent downstream port, and port C is the non-transparent downstream
port.
During link training, link width is automatically negotiated. Each
PES24NT3 port is capable of independently negotiating to a x8, x4, x2
or x1 width. Thus, the PES24NT3 may be used in virtually any three port
switch configuration (e.g., {x8, x8, x8}, {x4, x4, x4}, {x4, x2, x1}, etc.).
The PES24NT3 supports static lane reversal. For example, lane
reversal for upstream port A may be configured by asserting the PCI
Express Port A Lane Reverse (PEALREV) input signal or through serial
EEPROM or SMBus initialization. Lane reversal for ports B and C may
be enabled via a configuration space register, serial EEPROM, or the
SMBus.
Product Description
Utilizing standard PCI Express interconnect, the PES24NT3 provides
the most efficient high-performance I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout
with a minimum number of board layers. With support for non-transparent bridging, the PES24NT3, as a standalone switch or as a chipset
with IDT PCIe System Interconnect Switches, enables multi-host and
intelligent I/O applications requiring inter-domain communication. The
PES24NT3 provides 96 Gbps (12 GBps) of aggregated, full-duplex
switching capacity through 24 integrated serial lanes, using proven and
robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in
both directions and is fully compliant with PCI Express Base specification 1.0a.
The PES24NT3 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 1.0a. The PES24NT3 can operate either as a store and
forward or cut-through switch depending on the packet size and is
designed to switch memory and I/O transactions. It supports eight Traffic
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*Notice: The information in this document is subject to change without notice
April 11, 2007
IDT 89HPES24NT3 Data Sheet
CPU
CPU
CPU
PES24NT3
PES24NT3
PES24NT3
PCIe System Interconnect Switch
PCIe System Interconnect Switch
Embedded
CPU
Embedded
CPU
FC
SATA / SAS
Embedded
CPU
GbE / 10GigE
Figure 2 PCIe System Interconnect Architecture Block Diagram
Controller 1
Controller 2
CPU
CPU
Cache Maint. &
Possible Data Flow
x8 PCIe
x8 PCIe
PES24N3
PES24N3
x8 PCIe
FC
Controller
FC
Controller
Storage
To Server
FC 2Gb/s and
FC 2Gb/s and
4Gb/s
4Gb/s
To Server
Figure 3 Dual Host Storage System
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April 11, 2007
IDT 89HPES24NT3 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES24NT3. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
PEALREV
I
PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modifying the value of the PALREV bit in the PA_SWCTL register.
PEARP[7:0]
PEARN[7:0]
I
PCI Express Port A Serial Data Receive. Differential PCI Express receive
pairs for port A.
PEATP[7:0]
PEATN[7:0
O
PCI Express Port A Serial Data Transmit. Differential PCI Express transmit pairs for port A
PEBLREV
I
PCI Express Port B Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port B are reversed. This value may be overridden by modifying the value of the PBLREV bit in the PA_SWCTL register.
PEBRP[7:0]
PEBRN[7:0]
I
PCI Express Port B Serial Data Receive. Differential PCI Express receive
pairs for port B.
PEBTP[7:0]
PEBTN[7:0]
O
PCI Express Port B Serial Data Transmit. Differential PCI Express transmit pairs for port B
PECLREV
I
PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modifying the value of the PCLREV bit in the PA_SWCTL register.
PECRP[7:0]
PECRN[7:0]
I
PCI Express Port C Serial Data Receive. Differential PCI Express receive
pairs for port C.
PECTP[7:0]
PECTN[7:0]
O
PCI Express Port C Serial Data Transmit. Differential PCI Express transmit pairs for port C
PEREFCLKP[1:0]
PEREFCLKN[1:0]
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. These signals select the frequency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 1 PCI Express Interface Pins
Signal
Type
Name/Description
MSMBADDR[4:1]
I
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROM or I/O Expanders are being accessed.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
Table 2 SMBus Interface Pins (Part 1 of 2)
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IDT 89HPES24NT3 Data Sheet
Signal
Type
Name/Description
SSMBADDR[5,3:1]
I
SSMBCLK
I/O
Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus.
SSMBDAT
I/O
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
Table 2 SMBus Interface Pins (Part 2 of 2)
Signal
Type
Name/Description
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PEBRSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port B
GPIO[1]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PECRSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port C
GPIO[2]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PALINKUPN
Alternate function pin type: Output
Alternate function: Port A link up status output
GPIO[3]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PBLINKUPN
Alternate function pin type: Output
Alternate function: Port B link up status output
GPIO[4]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PCLINKUPN
Alternate function pin type: Output
Alternate function: Port C link up status output
GPIO[5]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: FAILOVERP
Alternate function pin type: Input
Alternate function: NTB upstream port failover
GPIO[6]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[7]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Table 3 General Purpose I/O Pins
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IDT 89HPES24NT3 Data Sheet
Signal
Type
Name/Description
CCLKDS
I
Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a common clock is being used between the downstream device
and the downstream port.
CCLKUS
I
Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common clock is being used between the upstream device and
the upstream port.
MSMBSMODE
I
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
PENTBRSTN
I
Non-Transparent Bridge Reset. Assertion of this signal indicates a reset
on the external side of the non-transparent bridge. This signal is only used
when the switch mode selects a non-transparent mode and has no effect
otherwise.
PERSTN
I
Fundamental Reset. Assertion of this signal resets all logic inside the
PES24NT3 and initiates a PCI Express fundamental reset.
RSTHALT
I
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES24NT3 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is
cleared in the PA_SWCTL register by an SMBus master.
SWMODE[3:0]
I
Switch Mode. These configuration pins determine the PES24NT3 switch
operating mode.
0x0 - Reserved
0x1 - Reserved
0x2 - Non-transparent mode
0x3 - Non-transparent mode with serial EEPROM initialization
0x4 - Non-transparent failover mode
0x5 - Non-transparent failover mode with serial EEPROM initialization
0x6 through 0xF - Reserved
Table 4 System Pins
Signal
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
Table 5 Test Pins (Part 1 of 2)
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April 11, 2007
IDT 89HPES24NT3 Data Sheet
Signal
Type
Name/Description
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 5 Test Pins (Part 2 of 2)
Signal
Type
Name/Description
VDDCORE
I
Core VDD. Power supply for core logic.
VDDIO
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPE
I
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
VDDAPE
I
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
VTTPE
I
PCI Express Termination Power.
VSS
I
Ground.
Table 6 Power and Ground Pins
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April 11, 2007
IDT 89HPES24NT3 Data Sheet
Pin Characteristics
Note: Some input pads of the PES24NT3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function
PCI Express Interface
SMBus
Type
Buffer
I/O Type
Internal
Resistor
PEALREV
I
LVTTL
Input
pull-down
PEARN[7:0]
I
CML
Serial link
PEARP[7:0]
I
PEATN[7:0]
O
PEATP[7:0]
O
PEBLREV
I
LVTTL
Input
PEBRN[7:0]
I
CML
Serial link
Pin Name
PEBRP[7:0]
I
PEBTN[7:0]
O
PEBTP[7:0]
O
PECLREV
I
LVTTL
Input
PECRN[7:0]
I
CML
Serial link
PECRP[7:0]
I
PECTN[7:0]
O
PECTP[7:0]
O
pull-down
pull-down
PEREFCLKN[1:0]
I
PEREFCLKP[1:0]
I
LVPECL/
CML
Diff. Clock
Input
REFCLKM
I
LVTTL
Input
pull-down
MSMBADDR[4:1]
I
LVTTL
Input
pull-up
MSMBCLK
I/O
MSMBDAT
I/O
SSMBADDR[5,3:1]
SSMBCLK
Notes
Refer to
Table 8
STI
I
Input
I/O
STI
pull-up
SSMBDAT
I/O
General Purpose I/O
GPIO[7:0]
I/O
LVTTL
Input,
High Drive
pull-up
System Pins
CCLKDS
I
LVTTL
Input
pull-up
CCLKUS
I
pull-up
MSMBSMODE
I
pull-down
PENTBRSTN
I
PERSTN
I
RSTHALT
I
pull-down
SWMODE[3:0]
I
pull-up
Table 7 Pin Characteristics (Part 1 of 2)
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April 11, 2007
IDT 89HPES24NT3 Data Sheet
Function
JTAG
Type
Buffer
I/O Type
Internal
Resistor
JTAG_TCK
I
LVTTL
STI
pull-up
JTAG_TDI
I
JTAG_TDO
O
Low Drive
JTAG_TMS
I
STI
JTAG_TRST_N
I
Pin Name
Notes
pull-up
pull-up
pull-up
External
pull-down
Table 7 Pin Characteristics (Part 2 of 2)
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IDT 89HPES24NT3 Data Sheet
Logic Diagram — PES24NT3
PEATP[0]
PEATN[0]
PEARP[1]
PEARN[1]
PEATP[1]
PEATN[1]
...
PEALREV
PEARP[0]
PEARN[0]
PEARP[7]
PEARN[7]
PEATP[7]
PEATN[7]
PEBLREV
PEBRP[0]
PEBRN[0]
PEBTP[0]
PEBTN[0]
PEBRP[1]
PEBRN[1]
PEBTP[1]
PEBTN[1]
...
PCI Express
Switch
SerDes Input
Port B
2
...
PCI Express
Switch
SerDes Input
Port A
2
PEREFCLKP
PEREFCLKN
REFCLKM
...
Reference
Clocks
PEBRP[7]
PEBRN[7]
PES24NT3
PECTP[0]
PECTN[0]
PECTP[1]
PECTN[1]
...
...
PECRP[1]
PECRN[1]
PECRP[7]
PECRN[7]
Master
SMBus Interface
Slave
SMBus Interface
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
PCI Express
Switch
SerDes Output
Port B
PEBTP[7]
PEBTN[7]
PECLREV
PECRP[0]
PECRN[0]
PCI Express
Switch
SerDes Input
Port C
PCI Express
Switch
SerDes Output
Port A
PCI Express
Switch
SerDes Output
Port C
PECTP[7]
PECTN[7]
4
8
GPIO[7:0]
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
4
General Purpose
I/O
JTAG
PENTBRSTN
System
Functions
MSMBSMODE
CCLKDS
CCLKUS
RSTHALT
PERSTN
VDDCORE
VDDIO
VDDPE
VDDAPE
VSS
PENTBRSTN
SWMODE[3:0]
VTTPE
4
Power/Ground
Figure 4 PES24NT3 Logic Diagram
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IDT 89HPES24NT3 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13.
Parameter
Description
Min
RefclkFREQ
Input reference clock frequency range
100
RefclkDC2
Duty cycle of input clock
40
TR, TF
Rise/Fall time of input clocks
VSW
Differential input voltage swing4
Tjitter
Input clock jitter (cycle-to-cycle)
Typical
50
0.6
Max
Unit
1251
MHz
60
%
0.2*RCUI
RCUI3
1.6
V
125
ps
Table 8 Input Clock Requirements
1.
The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
2. ClkIn
must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
3.
RCUI (Reference Clock Unit Interval) refers to the reference clock period.
4.
AC coupling required.
AC Timing Characteristics
Parameter
Description
Min1
Typical1
Max1
Units
399.88
400
400.12
ps
0.7
.9
PCIe Transmit
UI
Unit Interval
TTX-EYE
Minimum Tx Eye Width
TTX-EYE-MEDIAN-toMAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median
TTX-RISE, TTX-FALL
D+ / D- Tx output rise/fall time
50
TTX- IDLE-MIN
Minimum time in idle
50
TTX-IDLE-SET-TO-
Maximum time to transition to a valid Idle after sending
an Idle ordered set
20
UI
IDLE
TTX-IDLE-TO-DIFF-
Maximum time to transition from valid idle to diff data
20
UI
500
1300
ps
400
400.12
ps
UI
0.15
90
UI
ps
UI
DATA
TTX-SKEW
Transmitter data skew between any 2 lanes
PCIe Receive
UI
Unit Interval
399.88
TRX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance)
TRX-EYE-MEDIUM TO
Max time between jitter median & max deviation
0.3
UI
Unexpected Idle Enter Detect Threshold Integration Time
10
ms
Lane to lane input skew
20
ns
0.4
UI
MAX JITTER
TRX-IDLE-DET-DIFFENTER TIME
TRX-SKEW
Table 9 PCIe AC Timing Characteristics
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
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IDT 89HPES24NT3 Data Sheet
Signal
Symbol
Reference
Min Max Unit
Edge
Timing
Diagram
Reference
GPIO
GPIO[7:0]1
Tpw_13b2
None
50
—
ns
Table 10 GPIO AC Timing Characteristics
1.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
2.
Signal
The values for this symbol were determined by calculation, not by testing.
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
Tper_16a
none
50.0
—
ns
See Figure 5.
10.0
25.0
ns
2.4
—
ns
1.0
—
ns
—
20
ns
—
20
ns
25.0
—
ns
JTAG
JTAG_TCK
Thigh_16a,
Tlow_16a
JTAG_TMS1,
JTAG_TDI
JTAG_TDO
Tsu_16b
JTAG_TCK rising
Thld_16b
Tdo_16c
JTAG_TCK falling
Tdz_16c2
JTAG_TRST_N
Tpw_16d2
none
Table 11 JTAG AC Timing Characteristics
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determined by calculation, not by testing.
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IDT 89HPES24NT3 Data Sheet
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
Thld_16b
Tsu_16b
JTAG_TDI
Thld_16b
Tsu_16b
JTAG_TMS
Tdo_16c
Tdz_16c
JTAG_TDO
Tpw_16d
JTAG_TRST_N
Figure 5 JTAG AC Timing Waveform
Recommended Operating Supply Voltages
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VDDCORE
Internal logic supply
0.9
1.0
1.1
V
VDDI/O
I/O supply except for SerDes LVPECL/CML
3.0
3.3
3.6
V
VDDPE
PCI Express Digital Power
0.9
1.0
1.1
V
VDDAPE
PCI Express Analog Power
0.9
1.0
1.1
V
VTTPE
PCI Express Serial Data Transmit Termination Voltage
1.425
1.5
1.575
V
VSS
Common ground
0
0
0
V
Table 12 PES24NT3 Operating Voltages
Power-Up Sequence
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the
PES24NT3, the power-up sequence must be as follows:
1. VDDI/O — 3.3V
2. VDDCore, VDDPE, VDDAPE — 1.0V
3. VTTPE — 1.5V
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues
are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the
power-up sequence.
13 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
Recommended Operating Temperature
Grade
Temperature
Commercial
0°C to +70°C Ambient
Table 13 PES24NT3 Operating Temperatures
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 14.
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 14.
All power measurements assume that the part is mounted on a 10 layer printed circuit board with 0 LFM airflow.
Number of
Connected Lanes:
Port-A/Port-B/Port-C
Core (Watts)
(1.0V supply)
PCIe Digital
(Watts)
(1.0V supply)
PCIe Analog
(Watts)
(1.0V supply)
PCIe Termination (Watts)
(1.5V supply)
I/O (Watts)
(3.3V supply)
Total (Watts)
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
8/4/4
0.59
0.84
0.75
1.08
0.33
0.42
0.62
0.78
0.002
0.01
2.3
3.12
8/8/8
0.68
0.95
0.98
1.43
0.38
0.48
0.88
1.01
0.002
0.01
2.92
3.88
Table 14 PES24NT3 Power Consumption
14 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 12.
Note: See Table 7, Pin Characteristics, for a complete I/O listing.
I/O Type
Serial Link
Parameter
Typ1
Max1
Unit
800
1200
mV
-3
-4
dB
3.7
V
Conditions
PCIe Transmit
VTX-DIFFp-p
VTX-DE-RATIO
Differential peak-to-peak output voltage
De-emphasized differential output voltage
VTX-DC-CM
DC Common mode voltage
VTX-CM-ACP
RMS AC peak common mode output voltage
20
mV
VTX-CM-DC-
Abs delta of DC common mode voltage
between L0 and idle
100
mV
Abs delta of DC common mode voltage
between D+ and D-
25
mV
Electrical idle diff peak output
20
mV
Voltage change during receiver detection
600
mV
active-idle-delta
VTX-CM-DC-linedelta
VTX-Idle-DiffP
Serial Link
(cont.)
Min1
Description
VTX-RCV-Detect
-0.1
1
RLTX-DIFF
Transmitter Differential Return loss
12
dB
RLTX-CM
Transmitter Common Mode Return loss
6
dB
ZTX-DEFF-DC
DC Differential TX impedance
80
100
120
Ω
ZOSE
Single ended TX Impedance
40
50
60
Ω
Transmitter Eye
Diagram
TX Eye Height (De-emphasized bits)
505
650
mV
Transmitter Eye
Diagram
TX Eye Height (Transition bits)
800
950
mV
VRX-DIFFp-p
Differential input voltage (peak-to-peak)
175
VRX-CM-AC
Receiver common-mode voltage for AC
coupling
RLRX-DIFF
Receiver Differential Return Loss
15
dB
RLRX-CM
Receiver Common Mode Return Loss
6
dB
Differential input impedance (DC)
80
100
120
Ω
Single-ended input impedance
40
50
60
Ω
200k
350k
PCIe Receive
ZRX-DIFF-DC
ZRX-COMM-DC
ZRX-COMM-HIGH- Powered down input common mode
impedance (DC)
Z-DC
VRX-IDLE-DET-
Electrical idle detect threshold
65
Input Capacitance
1.5
1200
mV
150
mV
Ω
175
mV
DIFFp-p
PCIe REFCLK
CIN
—
pF
Table 15 DC Electrical Characteristics (Part 1 of 2)
15 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
I/O Type
Min1
Typ1
Max1
Unit
Conditions
IOL
—
2.5
—
mA
VOL = 0.4v
IOH
—
-5.5
—
mA
VOH = 1.5V
IOL
—
12.0
—
mA
VOL = 0.4v
IOH
—
-20.0
—
mA
VOH = 1.5V
Parameter
Description
Other I/Os
LOW Drive
Output
High Drive
Output
Schmitt Trigger Input
(STI)
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDIO +
0.5
V
—
Input
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDIO +
0.5
V
—
CIN
—
—
8.5
pF
—
Inputs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK W/O
Pull-ups/downs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK WITH
Pull-ups/downs
—
—
+ 80
μA
VDDI/O (max)
Capacitance
Leakage
Table 15 DC Electrical Characteristics (Part 2 of 2)
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a.
16 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
Package Pinout — 420-BGA Signal Pinout for PES24NT3
The following table lists the pin numbers and signal names for the PES24NT3 device.
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
A1
VSS
B9
MSMBDAT
C17
VDDIO
D25
VSS
A2
VSS
B10
SSMBADDR_2
C18
VSS
D26
PEREFCLKN2
A3
VSS
B11
SSMBADDR_5
C19
VDDIO
E1
VSS
A4
JTAG_TDI
B12
SSMBDAT
C20
VSS
E2
VSS
A5
JTAG_TMS
B13
PEALREV
C21
VDDIO
E3
VSS
A6
MSMBADDR_1
B14
SWMODE_0
C22
VSS
E4
VSS
A7
MSMBADDR_3
B15
SWMODE_2
C23
VDDIO
E5
VSS
A8
MSMBCLK
B16
PECLREV
C24
VSS
E6
VDDCORE
A9
SSMBADDR_1
B17
PENTBRSTN
C25
VSS
E7
VDDCORE
A10
SSMBADDR_3
B18
GPIO_00
1
C26
PEREFCLKP2
E8
VSS
A11
SSMBCLK
B19
GPIO_02
1
D1
PEREFCLKP1
E9
VDDCORE
A12
CCLKUS
B20
GPIO_04
1
D2
VSS
E10
VSS
A13
CCLKDS
B21
GPIO_06
D3
VSS
E11
VDDCORE
A14
PEBLREV
B22
MSMBSMODE
D4
VSS
E12
VSS
A15
SWMODE_1
B23
REFCLKM
D5
VDDCORE
E13
VDDCORE
A16
SWMODE_3
B24
VDDIO
D6
VDDCORE
E14
VSS
A17
PERSTN
B25
VSS
D7
VSS
E15
VDDCORE
A18
RSTHALT
B26
VSS
D8
VDDCORE
E16
VSS
A19
GPIO_01
1
C1
PEREFCLKN1
D9
VSS
E17
VDDCORE
A20
GPIO_03
1
C2
VSS
D10
VDDCORE
E18
VSS
A21
GPIO_05
1
C3
VSS
D11
VSS
E19
VDDCORE
A22
GPIO_07
C4
VDDCORE
D12
VDDCORE
E20
VDDCORE
A23
VSS
C5
VDDIO
D13
VDDCORE
E21
VDDCORE
A24
VSS
C6
VSS
D14
VSS
E22
VSS
A25
VSS
C7
VDDIO
D15
VDDCORE
E23
VSS
A26
VSS
C8
VSS
D16
VSS
E24
VSS
B1
VSS
C9
VDDIO
D17
VDDCORE
E25
VSS
B2
VSS
C10
VSS
D18
VDDCORE
E26
VSS
B3
VDDIO
C11
VDDIO
D19
VDDCORE
F1
VDDCORE
B4
JTAG_TCK
C12
VSS
D20
VSS
F2
VDDCORE
B5
JTAG-TDO
C13
VDDIO
D21
VDDCORE
F3
VDDAPE
B6
JTAG-TRST_N
C14
VDDCORE
D22
VDDCORE
F4
VSS
B7
MSMBADDR_2
C15
VDDIO
D23
VSS
F5
VSS
B8
MSMBADDR_4
C16
VDDCORE
D24
VSS
F22
VSS
Alt
Table 16 PES24NT3 420-pin Signal Pin-Out (Part 1 of 3)
17 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
F23
VSS
K4
VDDAPE
P1
VDDCORE
U24
VDDPE
F24
VDDAPE
K5
VDDAPE
P2
VSS
U25
PECTP05
F25
VDDCORE
K22
VDDAPE
P3
VTTPE
U26
PECTN05
F26
VDDCORE
K23
VDDAPE
P4
VTTPE
V1
VDDCORE
G1
PEBTN07
K24
VDDAPE
P5
VSS
V2
VSS
G2
PEBTP07
K25
VSS
P22
VSS
V3
VDDAPE
G3
VDDPE
K26
VSS
P23
VTTPE
V4
VDDAPE
G4
PEBRN07
L1
PEBTN05
P24
VTTPE
V5
VDDAPE
G5
PEBRP07
L2
PEBTP05
P25
VSS
V22
VDDAPE
G22
PECRP00
L3
VDDPE
P26
VDDCORE
V23
VDDAPE
G23
PECRN00
L4
PEBRN05
R1
PEBTN03
V24
VDDAPE
G24
VDDPE
L5
PEBRP05
R2
PEBTP03
V25
VSS
G25
PECTP00
L22
PECRP02
R3
VDDPE
V26
VDDCORE
G26
PECTN00
L23
PECRN02
R4
PEBRN03
W1
PEBTN01
H1
VSS
L24
VDDPE
R5
PEBRP03
W2
PEBTP01
H2
VSS
L25
PECTP02
R22
PECRP04
W3
VDDPE
H3
VTTPE
L26
PECTN02
R23
PECRN04
W4
PEBRN01
H4
VTTPE
M1
VDDCORE
R24
VDDPE
W5
PEBRP01
H5
VSS
M2
VSS
R25
PECTP04
W22
PECRP06
H22
VSS
M3
VTTPE
R26
PECTN04
W23
PECRN06
H23
VTTPE
M4
VTTPE
T1
VDDCORE
W24
VDDPE
H24
VTTPE
M5
VSS
T2
VSS
W25
PECTP06
H25
VSS
M22
VSS
T3
VDDAPE
W26
PECTN06
H26
VSS
M23
VTTPE
T4
VDDAPE
Y1
VSS
J1
PEBTN06
M24
VTTPE
T5
VSS
Y2
VSS
J2
PEBTP06
M25
VSS
T22
VSS
Y3
VTTPE
J3
VDDPE
M26
VDDCORE
T23
VDDAPE
Y4
VTTPE
J4
PEBRN06
N1
PEBTN04
T24
VDDAPE
Y5
VSS
J5
PEBRP06
N2
PEBTP04
T25
VSS
Y22
VSS
J22
PECRP01
N3
VDDPE
T26
VDDCORE
Y23
VTTPE
J23
PECRN01
N4
PEBRN04
U1
PEBTN02
Y24
VTTPE
J24
VDDPE
N5
PEBRP04
U2
PEBTP02
Y25
VSS
J25
PECTP01
N22
PECRP03
U3
VDDPE
Y26
VSS
J26
PECTN01
N23
PECRN03
U4
PEBRN02
AA1
PEBTN00
K1
VSS
N24
VDDPE
U5
PEBRP02
AA2
PEBTP00
K2
VSS
N25
PECTP03
U22
PECRP05
AA3
VDDPE
K3
VDDAPE
N26
PECTN03
U23
PECRN05
AA4
PEBRN00
Alt
Table 16 PES24NT3 420-pin Signal Pin-Out (Part 2 of 3)
18 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
AA5
PEBRP00
AC3
VDDCORE
AD11
VDDPE
AE19
PEATP01
AA22
PECRP07
AC4
VDDCORE
AD12
VTTPE
AE20
VSS
AA23
PECRN07
AC5
VDDCORE
AD13
VDDPE
AE21
PEATP00
AA24
VDDPE
AC6
VTTPE
AD14
VTTPE
AE22
VSS
AA25
PECTP07
AC7
PEARN07
AD15
VDDPE
AE23
VDDCORE
AA26
PECTN07
AC8
VDDAPE
AD16
VDDAPE
AE24
VDDCORE
AB1
VSS
AC9
PEARN06
AD17
VSS
AE25
VSS
AB2
VSS
AC10
VDDAPE
AD18
VDDPE
AE26
VSS
AB3
VDDCORE
AC11
PEARN05
AD19
VDDPE
AF1
VSS
AB4
VDDCORE
AC12
VTTPE
AD20
VTTPE
AF2
VSS
AB5
VDDCORE
AC13
PEARN04
AD21
VDDPE
AF3
VDDCORE
AB6
VSS
AC14
VTTPE
AD22
VSS
AF4
VDDCORE
AB7
PEARP07
AC15
PEARN03
AD23
VDDCORE
AF5
VDDCORE
AB8
VSS
AC16
VDDAPE
AD24
VDDCORE
AF6
VSS
AB9
PEARP06
AC17
PEARN02
AD25
VSS
AF7
PEATN07
AB10
VDDAPE
AC18
VDDAPE
AD26
VSS
AF8
VSS
AB11
PEARP05
AC19
PEARN01
AE1
VSS
AF9
PEATN06
AB12
VSS
AC20
VTTPE
AE2
VSS
AF10
VDDCORE
AB13
PEARP04
AC21
PEARN00
AE3
VDDCORE
AF11
PEATN05
AB14
VDDAPE
AC22
VSS
AE4
VDDCORE
AF12
VDDCORE
AB15
PEARP03
AC23
VDDCORE
AE5
VSS
AF13
PEATN04
AB16
VSS
AC24
VDDCORE
AE6
VSS
AF14
VDDCORE
AB17
PEARP02
AC25
VSS
AE7
PEATP07
AF15
PEATN03
AB18
VDDAPE
AC26
VSS
AE8
VSS
AF16
VDDCORE
AB19
PEARP01
AD1
VSS
AE9
PEATP06
AF17
PEATN02
AB20
VSS
AD2
VSS
AE10
VSS
AF18
VSS
AB21
PEARP00
AD3
VDDCORE
AE11
PEATP05
AF19
PEATN01
AB22
VSS
AD4
VDDCORE
AE12
VSS
AF20
VSS
AB23
VDDCORE
AD5
VDDCORE
AE13
PEATP04
AF21
PEATN00
AB24
VDDCORE
AD6
VTTPE
AE14
VSS
AF22
VSS
AB25
VSS
AD7
VSS
AE15
PEATP03
AF23
VDDCORE
AB26
VSS
AD8
VDDPE
AE16
VSS
AF24
VDDCORE
AC1
VSS
AD9
VSS
AE17
PEATP02
AF25
VSS
AC2
VSS
AD10
VDDPE
AE18
VSS
AF26
VSS
Alt
Table 16 PES24NT3 420-pin Signal Pin-Out (Part 3 of 3)
19 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
Power Pins
VDDCore
VDDCore
VDDCore
VDDIO
VDDPE
VDDAPE
VTTPE
C4
F2
AE3
B3
G3
F3
H3
C14
F25
AE4
B24
G24
F24
H4
C16
F26
AE23
C5
J3
K3
H23
D5
M1
AE24
C7
J24
K4
H24
D6
M26
AF3
C9
L3
K5
M3
D8
P1
AF4
C11
L24
K22
M4
D10
P26
AF5
C13
N3
K23
M23
D12
T1
AF10
C15
N24
K24
M24
D13
T26
AF12
C17
R3
T3
P3
D15
V1
AF14
C19
R24
T4
P4
D17
V26
AF16
C21
U3
T23
P23
D18
AB3
AF23
C23
U24
T24
P24
D19
AB4
AF24
W3
V3
Y3
D21
AB5
W24
V4
Y4
D22
AB23
AA3
V5
Y23
E6
AB24
AA24
V22
Y24
E7
AC3
AD8
V23
AC6
E9
AC4
AD10
V24
AC12
E11
AC5
AD11
AB10
AC14
E13
AC23
AD13
AB14
AC20
E15
AC24
AD15
AB18
AD6
E17
AD3
AD18
AC8
AD12
E19
AD4
AD19
AC10
AD14
E20
AD5
AD21
AC16
AD20
E21
AD23
AC18
F1
AD24
AD16
Table 17 PES24NT3 Power Pins
20 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
Ground Pins
Vss
Vss
Vss
Vss
Vss
A1
D11
H1
Y22
AE2
A2
D14
H2
Y25
AE5
A3
D16
H5
Y26
AE6
A23
D20
H22
AB1
AE8
A24
D23
H25
AB2
AE10
A25
D24
H26
AB6
AE12
A26
D25
K1
AB8
AE14
B1
E1
K2
AB12
AE16
B2
E2
K25
AB16
AE18
B25
E3
K26
AB20
AE20
B26
E4
M2
AB22
AE22
C2
E5
M5
AB25
AE25
C3
E8
M22
AB26
AE26
C6
E10
M25
AC1
AF1
C8
E12
P2
AC2
AF2
C10
E14
P5
AC22
AF6
C12
E16
P22
AC25
AF8
C18
E18
P25
AC26
AF18
C20
E22
T2
AD1
AF20
C22
E23
T5
AD2
AF22
C24
E24
T22
AD7
AF25
C25
E25
T25
AD9
AF26
D2
E26
V2
AD17
D3
F4
V25
AD22
D4
F5
Y1
AD25
D7
F22
Y2
AD26
D9
F23
Y5
AE1
Table 18 PES24NT3 Ground Pins
21 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
Alternate Signal Functions
Pin
GPIO
Alternate
B18
GPIO[0]
PEBRSTN
A19
GPIO[1]
PECRSTN
B19
GPIO[2]
PALINKUPN
A20
GPIO[3]
PBLINKUPN
B20
GPIO[4]
PCLINKUPN
A21
GPIO[5]
FAILOVERP
Table 19 PES24NT3 Alternate Signal Functions
Signals Listed Alphabetically
Signal Name
I/O Type
Location
Signal Category
CCLKDS
I
A13
System
CCLKUS
I
A12
GPIO_00
I/O
B18
GPIO_01
I/O
A19
GPIO_02
I/O
B19
GPIO_03
I/O
A20
GPIO_04
I/O
B20
GPIO_05
I/O
A21
GPIO_06
I/O
B21
GPIO_07
I/O
A22
JTAG_TCK
I
B4
JTAG_TDI
I
A4
JTAG_TMS
I
A5
JTAG-TDO
O
B5
JTAG-TRST_N
I
B6
MSMBADDR_1
I
A6
MSMBADDR_2
I
B7
MSMBADDR_3
I
A7
MSMBADDR_4
I
B8
MSMBCLK
I/O
A8
MSMBDAT
I/O
B9
I
B22
MSMBSMODE
General Purpose Input/Output
JTAG
SMBus
System
Table 20 89PES24NT3 Alphabetical Signal List (Part 1 of 5)
22 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
Signal Name
I/O Type
Location
Signal Category
PEALREV
I
B13
PCI Express
PEARN00
I
AC21
PEARN01
I
AC19
PEARN02
I
AC17
PEARN03
I
AC15
PEARN04
I
AC13
PEARN05
I
AC11
PEARN06
I
AC9
PEARN07
I
AC7
PEARP00
I
AB21
PEARP01
I
AB19
PEARP02
I
AB17
PEARP03
I
AB15
PEARP04
I
AB13
PEARP05
I
AB11
PEARP06
I
AB9
PEARP07
I
AB7
PEATN00
O
AF21
PEATN01
O
AF19
PEATN02
O
AF17
PEATN03
O
AF15
PEATN04
O
AF13
PEATN05
O
AF11
PEATN06
O
AF9
PEATN07
O
AF7
PEATP00
O
AE21
PEATP01
O
AE19
PEATP02
O
AE17
PEATP03
O
AE15
PEATP04
O
AE13
PEATP05
O
AE11
PEATP06
O
AE9
PEATP07
O
AE7
PEBLREV
I
A14
PEBRN00
I
AA4
PEBRN01
I
W4
Table 20 89PES24NT3 Alphabetical Signal List (Part 2 of 5)
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April 11, 2007
IDT 89HPES24NT3 Data Sheet
Signal Name
I/O Type
Location
Signal Category
PEBRN02
I
U4
PCI Express
PEBRN03
I
R4
PEBRN04
I
N4
PEBRN05
I
L4
PEBRN06
I
J4
PEBRN07
I
G4
PEBRP00
I
AA5
PEBRP01
I
W5
PEBRP02
I
U5
PEBRP03
I
R5
PEBRP04
I
N5
PEBRP05
I
L5
PEBRP06
I
J5
PEBRP07
I
G5
PEBTN00
O
AA1
PEBTN01
O
W1
PEBTN02
O
U1
PEBTN03
O
R1
PEBTN04
O
N1
PEBTN05
O
L1
PEBTN06
O
J1
PEBTN07
O
G1
PEBTP00
O
AA2
PEBTP01
O
W2
PEBTP02
O
U2
PEBTP03
O
R2
PEBTP04
O
N2
PEBTP05
O
L2
PEBTP06
O
J2
PEBTP07
O
G2
PECLREV
I
B16
PECRN00
I
G23
PECRN01
I
J23
PECRN02
I
L23
PECRN03
I
N23
PECRN04
I
R23
Table 20 89PES24NT3 Alphabetical Signal List (Part 3 of 5)
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April 11, 2007
IDT 89HPES24NT3 Data Sheet
Signal Name
I/O Type
Location
Signal Category
PECRN05
I
U23
PCI Express
PECRN06
I
W23
PECRN07
I
AA23
PECRP00
I
G22
PECRP01
I
J22
PECRP02
I
L22
PECRP03
I
N22
PECRP04
I
R22
PECRP05
I
U22
PECRP06
I
W22
PECRP07
I
AA22
PECTN00
O
G26
PECTN01
O
J26
PECTN02
O
L26
PECTN03
O
N26
PECTN04
O
R26
PECTN05
O
U26
PECTN06
O
W26
PECTN07
O
AA26
PECTP00
O
G25
PECTP01
O
J25
PECTP02
O
L25
PECTP03
O
N25
PECTP04
O
R25
PECTP05
O
U25
PECTP06
O
W25
PECTP07
O
AA25
PENTBRSTN
I
B17
System
PEREFCLKN1
I
C1
PCI Express
PEREFCLKN2
I
D26
PEREFCLKP1
I
D1
PEREFCLKP2
I
C26
PERSTN
I
A17
System
REFCLKM
I
B23
PCI Express
RSTHALT
I
A18
System
Table 20 89PES24NT3 Alphabetical Signal List (Part 4 of 5)
25 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
Signal Name
I/O Type
Location
Signal Category
SSMBADDR_1
I
A9
SMBus
SSMBADDR_2
I
B10
SSMBADDR_3
I
A10
SSMBADDR_5
I
B11
SSMBCLK
I/O
A11
SSMBDAT
I/O
B12
SWMODE_0
I
B14
SWMODE_1
I
A15
SWMODE_2
I
B15
SWMODE_3
I
A16
SMBus
System
System
VDDCORE,
VDDAPE, VDDIO,
VDDPE, VTTPE
See Table 17 for a listing of power pins.
VSS
See Table 18 for a listing of ground pins.
Table 20 89PES24NT3 Alphabetical Signal List (Part 5 of 5)
26 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
PES24NT3 Pinout — Top View
1
2
3
4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
C
D
E
F
G
H
x x
x x
x x
x x
x x
x x
x x
x x
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
x
x
x
x
AC
AD
x
x
x
x
AE
AF
VDDCore (Power)
VDDI/O (Power)
x
VTTPE (Power)
Vss (Ground)
Signals
VDDPE (Power)
VDDAPE (Power)
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April 11, 2007
IDT 89HPES24NT3 Data Sheet
PES24NT3 Package Drawing — 420-Pin BX420/BXG420
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April 11, 2007
IDT 89HPES24NT3 Data Sheet
PES24NT3 Package Drawing — Page Two
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April 11, 2007
IDT 89HPES24NT3 Data Sheet
Revision History
March 15, 2007: Initial publication of Preliminary data sheet.
April 11, 2007: In Table 2, revised description of MSMBCLK.
30 of 31
April 11, 2007
IDT 89HPES24NT3 Data Sheet
Ordering Information
NN
A
AAA
NNAN
AA
AA
A
Product
Family
Operating
Voltage
Device
Family
Product
Detail
Revision
ID
Package
Temp Range
Legend
A = Alpha Character
N = Numeric Character
Blank
Commercial Temperature
(0°C to +70°C Ambient)
BX
BX420 420-ball BGA
BXG
BXG420 420-ball BGA, Green
ZA
Silicon revision
24NT3
24-lane, 3-port
Non-Transparent
PES
PCI Express Switch
H
1.0V +/- 0.1V Core Voltage
89
Serial Switching Product
Valid Combinations
89HPES24NT3ZABX
420-pin BX420 package, Commercial Temperature
89HPES24NT3ZABXG
420-pin Green BX420 package, Commercial Temperature
®
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31 of 31
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April 11, 2007