IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS DESCRIPTION: FEATURES: – – – – – – – – IDT74ALVC125 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V ± 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range VCC = 2.5V ± 0.2V CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin Available in SOIC, SSOP and TSSOP packages This quadruple bus buffer gate is built using advanced dual metal CMOS technology. The ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. The ALVC125 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. APPLICATIONS: Drive Features for ALVC125: – High Output Drivers: ±24mA – Suitable for heavy loads • 3.3V High Speed Systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 1 OE 1A 2 OE 2A 1 2 3 OE 3 1Y 3A 4 5 4 OE 6 2Y 4A 10 9 8 3Y 13 12 11 4Y SEPTEMBER 2000 INDUSTRIAL TEMPERATURE RANGE 1 c 1999 Integrated Device Technology, Inc. DSC-4635/- IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS (1) Symbol Description Max. Unit VTERM(2) Terminal Voltage with Respect to GND – 0.5 to + 4.6 V VTERM(3) Terminal Voltage with Respect to GND – 0.5 to VCC + 0.5 V TSTG Storage Temperature – 65 to + 150 °C IOUT DC Output Current – 50 to + 50 mA 4A IIK ± 50 mA 4Y IOK Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 – 50 mA ICC Continuous Current through each ±100 mA ISS VCC or GND 1 OE 1 14 V CC 1A 2 13 4 OE 1Y 3 2 OE 4 12 SO14-1 SO14-2 11 SO14-3 2A 5 10 2Y 6 9 3A GN D 7 8 3Y 3 OE ALVC QUAD Link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. SOIC/ SSOP/ TSSOP TOP VIEW CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 5 Max. 7 Unit pF COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF ALVC QUAD Link NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names xOE Description Output Enable Inputs (Active LOW) xA Data Inputs xY 3-State Outputs FUNCTION TABLE Inputs (1) xOE xA Output xY L H H L L L H X Z NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance 2 (each buffer) IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = −40°C to +85°C Symbol VIH Parameter Input HIGH Voltage Level VIL Input LOW Voltage Level Min. 1.7 Typ.(1) VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Test Conditions VCC = 2.3V to 2.7V — Max. — Unit V V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ± 10 µA IOZL (3-State Output pins) VO = GND — — ± 10 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V — 100 — mV ICCL ICCH ∆ICC Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC One input at VCC − 0.6V, other inputs at VCC or GND — 0.1 10 µA — — 750 µA Quiescent Power Supply Current Variation µA NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = – 0.1mA IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — 2.2 — VCC = 3.0V Output LOW Voltage Max. — VCC = 2.3V VCC = 2.7V VOL Min. VCC – 0.2 2.4 — VCC = 3.0V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3.0V IOL = 24mA — 0.55 Unit V V ALVC QUAD Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. c 3 IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, TA = 25oC Symbol CPD Parameter Power Dissipation Capacitance per gate Outputs enabled CPD Power Dissipation Capacitance per gate Outputs disabled SWITCHING CHARACTERISTICS Test Conditions CL = 0pF, f = 10Mhz Parameter Propagation Delay xA to xY Output Enable Time xOE to xY Output Disable Time xOE to xY VCC = 3.3V ± 0.3V Typical 20 Typical 30 Unit 3 6 pF pF (1) VCC = 2.5V ± 0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V Min. 1 Max. 3.1 Min. 1 Max. 3.1 Min. 1.1 Max. 3 Unit ns 1.5 5.4 1.5 5.3 1.5 4.5 ns 1 4.1 1.3 4.4 1.7 4.2 ns NOTE: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 4 IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V ± 0.3V VCC(1) = 2.7V 6 6 VIH 2.7 2.7 Vcc V SAM E PHASE INPUT TRANSITION VT 1.5 1.5 Vcc / 2 V OUTPUT VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 VCC(2)= 2.5V ± 0.2V Unit 2 x Vcc V 50 30 tPLH tPH L tPLH tPH L V IH VT 0V V OH VT V OL V IH VT 0V OPPOSITE PHASE INPUT TRANSITION pF ALVC QUAD Link ALVC Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V LO AD V CC 500 Ω (1, 2) V IN GND tPZL D.U.T. OUTPUT SW ITCH NORMALLY CLO SED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH 500 Ω RT CL ALVC Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. DATA INPUT Switch VLOAD GND ASYNCHRONOUS CONTROL Open SYNCHRONOUS CONTROL tPH Z VT V OH V HZ 0V 0V tS U V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH tR EM tS U tH V IH VT 0V tPH L1 tSK (x) V LZ V OL ALVC Link PULSE WIDTH V OH OUTPUT 1 V LO AD/2 TIM ING INPUT OUTPUT SKEW - TSK (x) tPLH1 V LO AD/2 VT SET-UP, HOLD, AND RELEASE TIMES ALVC QUAD Link INPUT 0V tPLZ ALVC Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests V IH VT CONTROL INPUT V OUT Pulse Generator DISABLE ENABLE Open LOW -HIGH-LOW PULSE VT V OL tSK (x) tW V OH VT V OL OUTPUT 2 VT HIGH-LOW -HIGH PULSE VT ALVC Link tPLH2 tPH L2 tSK (x) = tPL H2 - tP LH 1 or tPH L2 - tP HL1 ALV C Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION ID T XX Temp. R ange ALVC XXX XX Device Type Package DC PY PG Sm all Outline IC (SO 14-1) Shrink S m all Outline Package (S O14-2) Thin Shrink Small Outline Package (SO14-3) 125 Quadruple Bus Buffer Gate with 3-S tate Outputs, ±24m A 74 – 40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6