CY62148ESL MoBL® 4-Mbit (512 K × 8) Static RAM 4-Mbit (512 K × 8) Static RAM Features Functional Description ■ Higher speed up to 55 ns ■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V ■ Ultra low standby power ❐ Typical standby current: 1 µA ❐ Maximum standby current: 7 µA ■ Ultra low active power ❐ Typical active current: 2 mA at f = 1 MHz ■ Easy memory expansion with CE and OE features ■ Automatic power-down when deselected The CY62148ESL is a high performance CMOS static RAM organized as 512 K words by 8-bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. Placing the device in standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Available in Pb-free 32-Pin shrunk thin small outline package (STSOP) package To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram I/O00 IO INPUT BUFFER I/O1 IO 1 512K x 8 ARRAY I/O3 IO 3 I/O4 IO 4 I/O5 IO 5 I/O6 IO 6 CE • I/O IO77 POWER DOWN A18 A17 A15 A13 A14 OE A16 COLUMN DECODER WE Cypress Semiconductor Corporation Document #: 001-50045 Rev. *C I/O2 IO 2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 23, 2010 [+] Feedback CY62148ESL MoBL® Contents 4-Mbit (512 K × 8) Static RAM .......................................... 1 Features ............................................................................. 1 Functional Description ..................................................... 1 Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Document #: 001-50045 Rev. *C Truth Table ........................................................................ 9 Ordering Information ...................................................... 10 Ordering Code Definitions ............................................. 10 Package Diagram ............................................................ 11 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Page 2 of 13 [+] Feedback CY62148ESL MoBL® Pin Configuration Figure 1. 32-Pin STSOP (Top View) A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 STSOP Top View (not to scale) OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 Product Portfolio Power Dissipation Product CY62148ESL Range VCC Range (V)[1] Industrial/ 2.2 V to 3.6 V and 4.5 V to 5.5 V Automotive-A Speed (ns) 55 Operating ICC, (mA) f = 1 MHz f = fmax Standby, ISB2 (µA) Typ[2] Max Typ[2] Max Typ[2] Max 2 2.5 15 20 1 7 Notes 1. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document #: 001-50045 Rev. *C Page 3 of 13 [+] Feedback CY62148ESL MoBL® Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Operating Range Storage temperature ................................. –65 °C to +150 °C Device Ambient temperature with power applied.... 55 °C to +125 °C CY62148ESL Supply voltage to ground potential................. –0.5 V to 6.0 V DC voltage applied to outputs in high Z state [3, 4] ......................................... –0.5 V to 6.0 V Ambient Temperature Range VCC[5] Industrial/ –40 °C to +85 °C 2.2 V to 3.6 V, Automotive-A and 4.5 V to 5.5 V DC input voltage [3, 4] ..................................... –0.5 V to 6.0 V Output current into outputs (low)..................................20 mA Static discharge voltage .......................................... > 2001 V (MIL-STD-883, Method 3015) Latch-up current......................................................> 200 mA Electrical Characteristics Over the operating range Parameter VOH VOL Output HIGH voltage Output LOW voltage Input HIGH voltage VIH VIL Description [7] Input LOW voltage Test Conditions 55 ns (Industrial/Automotive-A) Min Typ[6] Max Unit 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 – – V 2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 – – 4.5 < VCC < 5.5 IOH = –1.0 mA 2.4 – – 2.2 < VCC < 2.7 IOL = 0.1 mA – – 0.4 2.7 < VCC < 3.6 IOL = 2.1 mA – – 0.4 4.5 < VCC < 5.5 IOL = 2.1 mA – – 0.4 2.2 < VCC < 2.7 1.8 – VCC + 0.3 2.7 < VCC < 3.6 2.2 – VCC + 0.3 4.5 < VCC < 5.5 2.2 – VCC + 0.5 2.2 < VCC < 2.7 –0.3 – 0.4 2.7 < VCC < 3.6 –0.3 – 0.6 4.5 < VCC < 5.5 –0.5 – 0.6 GND < VI < VCC –1 – +1 µA V V V IIX Input leakage current IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 µA ICC VCC operating supply current VCC = VCCmax IOUT = 0 mA, CMOS levels – 15 20 mA – 2 2.5 ISB1[8] Automatic CE CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, power-down current — f = fmax (address and data only), f = 0 (OE and WE), CMOS inputs VCC = VCC(max) Automatic CE CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, power-down current — f = 0, VCC = VCC(max) – 1 7 µA 1 7 µA ISB2[8] f = fmax = 1/tRC f = 1 MHz – – – CMOS inputs Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC (min) and 200 µs wait time after VCC stabilization. 6. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Under DC conditions the device meets a VIL of 0.8 V (for VCC range of 2.7 V to 3.6 V and 4.5 V to 5.5 V) and 0.6 V (for VCC range of 2.2 V to 2.7 V). However, in dynamic conditions Input LOW voltage applied to the device must not be higher than 0.6 V and 0.4 V for the above ranges. Refer to AN13470 for details. 8. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 001-50045 Rev. *C Page 4 of 13 [+] Feedback CY62148ESL MoBL® Capacitance Parameter [9] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(Typ) Max Unit 10 pF 10 pF Thermal Resistance Parameter [9] Description ΘJA Thermal resistance (junction to ambient) ΘJC Thermal resistance (junction to case) Test Conditions STSOP Unit 49.02 °C/W 14.07 °C/W Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board Figure 2. AC Test Loads and Waveforms R1 ALL INPUT PULSES VCC OUTPUT VCC 30 pF INCLUDING JIG AND SCOPE R2 90% 10% 90% 10% GND Rise Time = 1 V/ns Equivalent to: Fall Time = 1 V/ns THEVENIN EQUIVALENT RTH OUTPUT Parameter 2.5 V R1 R2 RTH 8000 VTH 1.20 V 3.0 V 5.0 V Unit 16667 1103 1800 Ω 15385 1554 990 Ω 645 639 Ω 1.75 1.77 V Notes 9. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-50045 Rev. *C Page 5 of 13 [+] Feedback CY62148ESL MoBL® Data Retention Characteristics Over the operating range Parameter Conditions VCC for data retention VDR ICCDR Description [11] Data retention current CE > VCC – 0.2 V, VIN > VCC – 0.2 V or Industrial/ VIN < 0.2 V, VCC = 1.5 V Automotive-A Min Typ[10] Max Unit 1.5 – – V – 1 7 µA tCDR Chip deselect to data retention time 0 – – ns tR [12] Operation recovery time 55 – – ns Figure 3. Data Retention Waveform DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5 V VCC(min) tR CE Notes 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 11. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. Document #: 001-50045 Rev. *C Page 6 of 13 [+] Feedback CY62148ESL MoBL® Switching Characteristics Over the operating range Parameter [13] Description 55 ns (Industrial/Automotive-A) Min Max Unit Read Cycle tRC Read cycle time 55 – ns tAA Address to data valid – 55 ns tOHA Data hold from address change 10 – ns tACE CE LOW to data valid – 55 ns tDOE OE LOW to data valid – 25 ns 5 – ns – 20 ns 10 – ns – 20 ns tLZOE OE LOW to low Z tHZOE [14] OE HIGH to high Z tLZCE CE LOW to low Z [14, 15] [14] [14, 15] tHZCE CE HIGH to high Z tPU CE LOW to power-up 0 – ns CE HIGH to power-up – 55 ns tWC Write cycle time 55 – ns tSCE CE LOW to write end 40 – ns tAW Address setup to write end 40 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 40 – ns tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns – 20 ns 10 – ns tPD Write Cycle tHZWE tLZWE [16] WE LOW to high Z [14, 15] WE HIGH to low Z [14] Notes 13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 5. 14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 15. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 16. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 001-50045 Rev. *C Page 7 of 13 [+] Feedback CY62148ESL MoBL® Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [17, 18] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [18, 19] ADDRESS tRC CE tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA VALID DATA OUT tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE ICC 50% 50% ISB Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [20, 21] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O NOTE 22 tHD DATA VALID tHZOE Notes 17. Device is continuously selected. OE, CE = VIL. 18. WE is HIGH for read cycles. 19. Address valid before or similar to CE transition LOW. 20. Data I/O is high impedance if OE = VIH. 21. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 22. During this period, the I/Os are in output state. Do not apply input signals. Document #: 001-50045 Rev. *C Page 8 of 13 [+] Feedback CY62148ESL MoBL® Switching Waveforms (continued) Figure 7. Write Cycle No. 2 (CE Controlled) [23, 24] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [24] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 25 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE WE OE H[26] I/O Mode Power X X High Z Deselect/power-down Standby (ISB) L H L Data out Read Active (ICC) L H H High Z Output disabled Active (ICC) L L X Data in Write Active (ICC) Notes 23. Data I/O is high impedance if OE = VIH. 24. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 25. During this period, the I/Os are in output state. Do not apply input signals. 26. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 001-50045 Rev. *C Page 9 of 13 [+] Feedback CY62148ESL MoBL® Ordering Information Table 1 lists the CY62148ESL MoBL key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Table 1. Key features and Ordering Information Speed (ns) 55 Package Diagram Ordering Code Package Type Operating Range CY62148ESL-55ZAXI 51-85094 32-Pin STSOP (Pb-free) Industrial CY62148ESL-55ZAXA 51-85094 32-Pin STSOP (Pb-free) Automotive-A Ordering Code Definitions CY 621 4 8 E SL 55 ZAX I/A Temperature grades: I = Industrial A = Automotive-A 32-Pin STSOP (Pb-free) Speed grade (55 ns) SL = Low power Process technology: 90-nm Bus Width = x8 Density = 4 Mbit Family: Low power SRAM Company ID: CY = Cypress Document #: 001-50045 Rev. *C Page 10 of 13 [+] Feedback CY62148ESL MoBL® Package Diagram Figure 9. 32-Pin Shrunk Thin Small Outline Package (8 mm × 13.4 mm), 51-85094 51-85094-*E Acronyms Document Conventions Acronym Description CMOS complementary metal oxide semiconductor I/O input/output MoBL more battery life SRAM static random access memory STSOP shrunk thin small outline package Document #: 001-50045 Rev. *C Units of Measure Symbol ns Unit of Measure nano seconds V volts µA micro amperes mA milli amperes pF pico Farad °C degree Celsius W watts Page 11 of 13 [+] Feedback CY62148ESL MoBL® Document History Page Document Title: CY62148ESL MoBL® 4-Mbit (512 K × 8) Static RAM Document Number: 001-50045 Revision ECN Orig. of Change Submission Date ** 2612938 VKN/PYRS 01/21/09 Description of Change New datasheet *A 2800124 VKN 11/06/2009 Included Automotive-A information *B 2947039 VKN 06/10/2010 Added footnote related to chip enable in Truth Table Added footnote for the ISB2 parameter in Electrical Characteristics Updated Package Diagram Updated links in Sales, Solutions, and Legal Information *C 3006318 AJU Document #: 001-50045 Rev. *C 08/23/10 Template update. Updated table of contents. Added acronyms, units of measure and ordering code definitions. Added reference to note 8 to parameter ISB1on page 4 under Electrical characterisitics table. Added reference to note 11 to parameter ICCDR on page 6 under data retention characteristics table. Page 12 of 13 [+] Feedback CY62148ESL MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-50045 Rev. *C Revised August 23, 2010 Page 13 of 13 MoBL is the registered trademark, and More Battery Life is the trademark of Cypress Semiconductor Corporation. All other product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback