CY62168DV30 MoBL® ® 16-Mbit (2M x 8) MoBL Static RAM Features ■ Very high speed ❐ 55 ns ■ Wide voltage range ❐ 2.2 V – 3.6 V ■ Ultra-low active power ❐ Typical active current: 2 mA @ f = 1 MHz ❐ Typical active current: 15 mA @ f = fMax (55 ns Speed) ■ Ultra-low standby power ■ Easy memory expansion with CE1, CE2 and OE features ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed/power ■ Available in non Pb-free 48-ball very fine ball grid array (VFBGA) package. automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins(A0 through A20). Reading from the device is accomplished by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. Functional Description[1] The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW). See the “Truth Table” on page 10 for a complete description of read and write modes. The CY62168DV30 is a high-performance CMOS static RAMs organized as 2048Kbit words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an Logic Block Diagram I/O0 Data in Drivers I/O1 2048K x 8 ARRAY I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O3 I/O4 I/O5 COLUMN DECODER CE1 CE2 I/O6 POWER DOWN I/O7 OE A17 A18 A19 A20 A16 A13 A14 A15 WE Note 1. For best-practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com. Cypress Semiconductor Corporation Document Number : 38-05329 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 19, 2010 [+] Feedback CY62168DV30 MoBL® Contents Pin Configuration .............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Document Number : 38-05329 Rev. *I Truth Table ...................................................................... 10 Ordering Information ...................................................... 10 Ordering Code Definition ........................................... 10 Package Diagram ............................................................ 11 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Page 2 of 13 [+] Feedback CY62168DV30 MoBL® Pin Configuration[2] 48-ball VFBGA Top View 1 2 3 4 5 6 DNU OE A0 A1 A2 CE2 A DNU DNU A3 A4 CE1 DNU B I/O0 DNU A5 A6 DNU I/O4 C VSS I/O1 A17 A7 I/O5 VCC D VCC I/O2 DNU A16 I/O6 VSS E I/O3 DNU A14 A15 DNU I/O7 F DNU A20 A12 A13 WE DNU G A18 A8 A9 A10 A11 A19 H Product Portfolio Power Dissipation VCC Range (V) Product CY62168DV30LL Speed (ns) Min Typ[3] Max 2.2 3.0 3.6 55 Operating ICC (mA) f = 1 MHz Standby ISB2(μA) f = fMax Typ [3] Max Typ[3] Max Typ[3] Max 2 4 15 30 2.5 22 Notes 2.DNU pins have to be left floating or tied to VSS to ensure proper operation. 3.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C. Document Number : 38-05329 Rev. *I Page 3 of 13 [+] Feedback CY62168DV30 MoBL® Maximum Ratings DC input voltage[4, 5] ......................–0.3 V to VCC(max) + 0.3 V (Above which the useful life may be impaired. For user guidelines, not tested.) Storage temperature................................. –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C Output current into outputs (LOW) .............................. 20 mA Static discharge voltage........................................... > 2001 V (per MIL-STD-883, Method 3015) Latch-up current ..................................................... > 200 mA Operating Range Supply voltage to ground potential ....................................... –0.3 V to VCC(max) + 0.3 V Range VCC[7] DC voltage applied to outputs in High-Z state[4, 5] .........................–0.3 V to VCC(max) + 0.3 V Ambient Temperature (TA)[6] Industrial –40 °C to +85 °C 2.2 V – 3.6 V DC Electrical Characteristics (Over the Operating Range) Parameter VOH VOL VIH VIL Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Test Conditions CY62168DV30-55 Min Typ[8] Max 2.2 V < VCC < 2.7 V IOH = −0.1 mA 2.0 – – 2.7 V < VCC < 3.6 V IOH = −1.0 mA 2.4 – – 2.2 V < VCC < 2.7 V IOL = 0.1 mA – – 0.4 2.7 V < VCC < 3.6 V IOL = 2.1 mA – – 0.4 2.2 V < VCC < 2.7 V 1.8 – VCC + 0.3 2.7 V < VCC < 3.6 V 2.2 – VCC + 0.3 2.2 V < VCC < 2.7 V –0.3 – 0.6 2.7 V < VCC < 3.6 V –0.3 – 0.8 Unit V V V V IIX Input leakage current GND < VI < VCC –1 – +1 μA IOZ Output leakage current GND < VO < VCC, Output disabled –1 – +1 μA ICC VCC operating supply current f = fMax = 1/tRC – 15 30 mA – 2 4 f = 1 MHz VCC = 3.6 V, IOUT = 0 mA, CMOS level ISB1 Automatic CE Power-down current — CMOS inputs CE1 > VCC − 0.2 V, CE2 < 0.2 V, VIN > VCC − 0.2 V, VIN < 0.2 V, f = fMax (Address and data only), f = 0 (OE, WE) – 2.5 22 μA ISB2 Automatic CE Power-down current— CMOS inputs CE1 > VCC − 0.2 V, CE2 < 0.2 V, VIN > VCC − 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.6 V – 2.5 22 μA Notes 4. VIL(min) = –2.0 V for pulse durations less than 20 ns. 5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 6. TA is the “Instant-On” case temperature. 7. Full device AC operation assumes a 100 μs ramp time from 0 to VCC(min) and 100 μs wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C Document Number : 38-05329 Rev. *I Page 4 of 13 [+] Feedback CY62168DV30 MoBL® Capacitance Parameter[9] Description CIN Input capacitance COUT Output capacitance Test Conditions Max Unit 8 pF 10 pF TA = 25 °C, f = 1 MHz, VCC = VCC(typ.) Thermal Resistance Parameter[9] Description ΘJA Thermal resistance (Junction to ambient) ΘJC Thermal resistance (Junction to case) Test Conditions VFBGA Unit 55 °C / W 16 °C / W Still air, soldered on a 3 × 4.5 inch, 2-layer printed circuit board AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 GND 90% 10% 90% 10% Fall time: 1 V/ns Rise Time: 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT Parameters 2.5 V R1 R2 RTH VTH VTH 3.0 V Unit 16600 1103 Ω 15400 1554 Ω 8000 645 Ω 1.2 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for data retention ICCDR Data retention current Conditions VCC = 1.5 V Min Typ[10] Max Unit 1.5 – 3.6 V – – 10 μA CE1 > VCC − 0.2 V or CE2 <0.2 V VIN > VCC − 0.2 V or VIN < 0.2 V tCDR[9] Chip deselect to data retention time 0 – – ns tR[11] Operation recovery time 55 – – ns Notes 9. Tested initially and after any design or process changes that may affect these parameters. 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C 11. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.. Document Number : 38-05329 Rev. *I Page 5 of 13 [+] Feedback CY62168DV30 MoBL® Data Retention Waveform DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5 V VCC(min) tR CE1 or CE2 Document Number : 38-05329 Rev. *I Page 6 of 13 [+] Feedback CY62168DV30 MoBL® Switching Characteristics Over the Operating Range Parameter[12] Description 55 ns Min. Max. Unit Read Cycle tRC Read cycle time 55 – ns tAA Address to data valid – 55 ns tOHA Data hold from address change 10 – ns tACE CE1 LOW and CE2 HIGH to data valid – 55 ns tDOE OE LOW to data valid – 25 ns tLZOE OE LOW to Low Z[13] 5 – ns tHZOE OE HIGH to High Z[13, 14] – 20 ns tLZCE CE1 LOW and CE2 HIGH to Low Z[13] 10 – ns tHZCE CE1 HIGH or CE2 LOW to High Z[13, 14] – 20 ns tPU CE1 LOW and CE2 HIGH to Power-up 0 – ns tPD CE1 HIGH or CE2 LOW to Power-down – 55 ns tWC Write cycle time 55 – ns tSCE CE1 LOW and CE2 HIGH to write end 40 – ns tAW Address set-up to write end 40 – ns tHA Address hold from write end 0 – ns tSA Address set-up to write start 0 – ns tPWE WE Pulse width 40 – ns tSD Data set-up to write end 25 – ns tHD Data hold from write end 0 – ns tHZWE WE LOW to High Z[13, 14] – 20 ns tLZWE WE HIGH to Low Z[13] 10 – ns Write Cycle[15] Notes 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns or less (1V/ns), timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 15. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document Number : 38-05329 Rev. *I Page 7 of 13 [+] Feedback CY62168DV30 MoBL® Switching Waveforms Figure 1. Read Cycle No. 1 (Address Transition Controlled)[16, 17] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 2. Read Cycle No. 2 (OE Controlled)[17, 18] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA OUT DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% 50% ICC ISB Figure 3. Write Cycle No. 1 (WE Controlled)[19, 20, 21] tWC ADDRESS tSCE CE1 CE2 tAW tSA tHA tPWE WE OE tSD DATA I/O See Note 22 tHD VALID DATA tHZOE Notes 16. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 17. WE is HIGH for read cycle. 18. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 19. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 20. Data I/O is high impedance if OE = VIH. 21. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high-impedance state. 22. During this period, the I/Os are in output state and input signals should not be applied. Document Number : 38-05329 Rev. *I Page 8 of 13 [+] Feedback CY62168DV30 MoBL® Switching Waveforms (continued) Figure 4. Write Cycle No. 2 (CE1 or CE2 Controlled)[23, 24, 25] tWC ADDRESS tSCE CE1 tSA CE2 tAW tHA tPWE WE OE tSD DATA I/O tHD VALID DATA Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)[26] tWC ADDRESS tSCE CE1 CE2 tAW tSA tHA tPWE WE tSD DATA I/O See Note 26 tHD VALID DATA tHZWE tLZWE Notes 23. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 24. Data I/O is high impedance if OE = VIH 25. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high-impedance state. 26. During this period, the I/Os are in output state and input signals should not be applied Document Number : 38-05329 Rev. *I Page 9 of 13 [+] Feedback CY62168DV30 MoBL® Truth Table CE1 CE2 WE OE Inputs/Outputs Mode Power H X X X High Z Deselect/Power-down Standby (ISB) X L X X High Z Deselect/Power-down Standby (ISB) L H H L Data out (I/O0-I/O7) Read Active (ICC) L H L X Data in (I/O0-I/O7) Write Active (ICC) L H H H High Z Output disabled Active (ICC) Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 55 Package Diagram Ordering Code CY62168DV30LL-55BVI Package Type 51-85178 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts Ordering Code Definition CY 621 6 8D V30 LL 55 XXX X Tem perature Grades I = Industrial Package Type = BV: VFBGA Speed Grade Low Power Voltage = 3.0 Bus W idth = X8 D = 130nm Technology Density = 16 M bit M oBL SRAM Fam ily Com pany ID: CY = Cypress Document Number : 38-05329 Rev. *I Page 10 of 13 [+] Feedback CY62168DV30 MoBL® Package Diagram 51-85178 *A Acronyms Document Conventions Description Units of Measure CMOS complementary metal oxide semiconductor Symbol I/O input/output °C degrees Celsius SRAM static random access memory μA microamperes VFBGA very fine ball grid array mA milliampere TSOP thin small outline package MHz megahertz Acronym Document Number : 38-05329 Rev. *I Unit of Measure ns nanoseconds pF picofarads V volts Ω ohms W watts Page 11 of 13 [+] Feedback CY62168DV30 MoBL® Document History Page Document Title: CY62168DV30 MoBL®, 16-Mbit (2M x 8) MoBL® Static RAM Document Number: 38-05329 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 118409 09/30/02 GUG New Data Sheet *A 123693 02/05/03 DPM Changed Advance Information to Preliminary Added package diagram *B 126556 04/24/03 DPM Minor change: Change sunset owner from DPM to HRT *C 132869 01/15/04 XRJ Changed Preliminary to Final *D 272589 See ECN PCI Updated Final data sheet and added Pb-free package. *E 335864 See ECN PCI Removed redundant packages from Ordering Information Table Added Address A20 to ball G2 in the Pin Configuration *F 492895 See ECN VKN Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed 70 ns speed bin Removed L power bin from product offering Updated Ordering Information Table *G 2914085 04/15/10 NIKM Removed inactive part from Ordering Information. Updated Packaging Information *H 3070774 10/27/2010 RAME Updated Template Added Acronyms and Units of Measure Added Ordering Code Definition Converted all tablenotes to footnote as per latest template *I 3090588 11/19/2010 AJU Document Number : 38-05329 Rev. *I Post to external web. Page 12 of 13 [+] Feedback CY62168DV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2002-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number : 38-05329 Rev. *I Revised November 19, 2010 Page 13 of 13 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders [+] Feedback