IDT 89HPES32H8ZAAR

89HPES32H8
Data Sheet
32-Lane 8-Port PCI Express®
System Interconnect Switch
®
Device Overview
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin algorithms
– Virtual channels arbitration based on priority
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all ports
– Supports locked transactions, allowing use with legacy software
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates thirty-two 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Redundant upstream port failover capability
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
◆
The 89HPES32H8 is a member of the IDT PRECISE™ family of PCI
Express® switching solutions. The PES32H8 is a 32-lane, 8-port system
interconnect switch optimized for PCI Express packet switching in highperformance applications, supporting multiple simultaneous peer-topeer traffic flows. Target applications include servers, storage, communications, and embedded systems.
Features
◆
High Performance PCI Express Switch
– Eight maximum switch ports
• Four main ports each of which consists of eight SerDes
• Each x8 main port can further bifurcate to 2 x4-ports
– Thirty-two 2.5 Gbps embedded SerDes
• Supports pre-emphasis and receive equalization on per-port
basis
– Delivers 128 Gbps (16 GBps) aggregate switching capacity
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– Supports two virtual channels and eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆
◆
Block Diagram
x8/x4/x2/x1
x8/x4/x2/x1
SerDes
SerDes
DL/Transaction Layer
DL/Transaction Layer
Port
Arbitration
Route Table
8-Port Switch Core
Scheduler
Frame Buffer
DL/Transaction Layer
DL/Transaction Layer
SerDes
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 40
© 2007 Integrated Device Technology, Inc.
July 19, 2007
IDT 89HPES32H8 Data Sheet
◆
◆
◆
◆
– Supports optional PCI Express end-to-end CRC checking
– Supports optional PCI Express Advanced Error Reporting
– Supports PCI Express Hot-Plug
• Compatible with Hot-Plug I/O expanders used on PC
motherboards
– Supports Hot-Swap
Power Management
– Supports PCI Power Management Interface specification,
Revision 1.1 (PCI-PM)
• Supports powerdown modes at the link level (L0, L0s, L1,
L2/L3 Ready and L3) and at the device level (D0, D3hot)
– Unused SerDes disabled
Testability and Debug Features
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Thirty-two General Purpose Input/Output pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 31mm x 31mm 900-ball Flip Chip BGA with
1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES32H8 provides
the most efficient system interconnect switching solution for applications
requiring maximum throughput, low latency, and simple board layout
with a minimum number of board layers. It provides 128 Gbps of aggregated, full-duplex switching capacity through 32 integrated serial lanes,
using proven and robust IDT technology. Each lane provides 2.5 Gbps
of bandwidth in both directions and is fully compliant with PCI Express
Base specification 1.1.
The PES32H8 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 1.1. The PES32H8 can operate either as a store and forward
or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and two Virtual Channels
(VC) with sophisticated resource management to enable efficient
switching and I/O connectivity for servers, storage, and embedded applications.
SMBus Interface
The PES32H8 contains two SMBus interfaces. The slave interface
provides full access to the configuration registers in the PES32H8,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configuration register values of the PES32H8 to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the SMBus
address to which the device responds to be configured. In the master
interface, these address pins allow the SMBus address of the serial
configuration EEPROM from which data is loaded to be configured. The
SMBus address is set up on negation of PERSTN by sampling the
corresponding address pins. When the pins are sampled, the resulting
address is assigned as shown in Table 1.
Non-bifurcated
Fully Bifurcated
x8
x4
1 0
x8
2
1
7 x8
6
3
x4
0
x4
2
7
x4
x4
3
6
x4
4 5
4
x8
x4
5
x4
Figure 2 Port Configuration Examples
Note: The configurations in the above diagram show the maximum port widths. The PES32H8 can negotiate to narrower port widths — x4,
x2, or x1.
2 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Bit
Slave
SMBus
Address
Master
SMBus
Address
1
SSMBADDR[1]
MSMBADDR[1]
2
SSMBADDR[2]
MSMBADDR[2]
3
SSMBADDR[3]
MSMBADDR[3]
4
0
MSMBADDR[4]
5
SSMBADDR[5]
1
6
1
0
7
1
1
Table 1 Master and Slave SMBus Address Assignment
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
3(a), the master and slave SMBuses are tied together and the PES32H8 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES32H8 registers supports SMBus arbitration. In some systems, this SMBus master
interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support
these systems, the PES32H8 may be configured to operate in a split configuration as shown in Figure 3(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES32H8 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the
serial EEPROM.
PES32H8
Processor
SMBus
Master
Serial
EEPROM
...
Other
SMBus
Devices
PES32H8
SSMBCLK
SSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
MSMBCLK
MSMBDAT
Processor
SMBus
Master
...
Other
SMBus
Devices
Serial
EEPROM
(b) Split Configuration and Management Buses
(a) Unified Configuration and Management Bus
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES32H8 supports PCI Express Hot-Plug on each downstream port (ports 1 through 7). To reduce the number of pins required on the device,
the PES32H8 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES32H8 generates an SMBus transaction to the I/O expander
with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES32H8. In response to an I/O expander interrupt, the PES32H8 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES32H8 provides 32 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
outputs, or alternate functions. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software,
SMBus slave interface, or serial configuration EEPROM.
3 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Pin Description
The following tables lists the functions of the pins provided on the PES32H8. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
Signal
Type
Name/Description
PE0RP[3:0]
PE0RN[3:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for
port 0. Port 0 is the upstream port.
PE0TP[3:0]
PE0TN[3:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for
port 0. Port 0 is the upstream port.
PE1RP[3:0]
PE1RN[3:0]
I
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for
port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs
for lanes 4 through 7.
PE1TP[3:0]
PE1TN[3:0]
O
PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pairs for
port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs
for lanes 4 through 7.
PE2RP[3:0]
PE2RN[3:0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for
port 2.
PE2TP[3:0]
PE2TN[3:0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for
port 2.
PE3RP[3:0]
PE3RN[3:0]
I
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pairs for
port 3. When port 2 is merged with port 3, these signals become port 2 receive pairs
for lanes 4 through 7.
PE3TP[3:0]
PE3TN[3:0]
O
PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pairs for
port 2. When port 2 is merged with port 3, these signals become port 2 transmit pairs
for lanes 4 through 7.
PE4RP[3:0]
PE4RN[3:0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for
port 4.
PE4TP[3:0]
PE4TN[3:0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for
port 4.
PE5RP[3:0]
PE5RN[3:0]
I
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pairs for
port 5. When port 4 is merged with port 5, these signals become port 4 receive pairs
for lanes 4 through 7.
PE5TP[3:0]
PE5TN[3:0]
O
PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pairs for
port 5. When port 4 is merged with port 5, these signals become port 4 transmit pairs
for lanes 4 through 7.
PE6RP[3:0]
PE6RN[3:0]
I
PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for
port 6.
PE6TP[3:0]
PE6TN[3:0]
O
PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for
port 6.
PE7RP[3:0]
PE7RN[3:0]
I
PCI Express Port 7 Serial Data Receive. Differential PCI Express receive pairs for
port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs
for lanes 4 through 7.
Table 2 PCI Express Interface Pins (Part 1 of 2)
4 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Signal
Type
Name/Description
PE7TP[3:0]
PE7TN[3:0]
O
PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit pairs for
port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs
for lanes 4 through 7.
REFCLKM
I
PCI Express Reference Clock Mode Select. This signal selects the frequency of the
reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
PEREFCLKP[3:0]
PEREFCLKN[3:0]
I
PCI Express Reference Clock. Differential reference clock pair input. This clock is
used as the reference clock by on-chip PLLs to generate the clocks required for the
system logic and on-chip SerDes. The frequency of the differential reference clock is
determined by the REFCLKM signal.
Table 2 PCI Express Interface Pins (Part 2 of 2)
Signal
Type
Name/Description
MSMBADDR[4:1]
I
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the
master SMBus. It is active and generating the clock only when the EEPROM or I/O
Expanders are being accessed.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
SSMBADDR[5,3:1]
I
Slave SMBus Address. These pins determine the SMBus address to which the slave
SMBus interface responds.
SSMBCLK
I/O
Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the
slave SMBus.
SSMBDAT
I/O
Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus.
Master SMBus Address. These pins determine the SMBus address of the serial
EEPROM from which configuration information is loaded.
Table 3 SMBus Interface Pins
Signal
Type
Name/Description
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[1]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[2]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[3]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[4]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[5]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
Table 4 General Purpose I/O Pins (Part 1 of 3)
5 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Signal
Type
Name/Description
GPIO[6]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P1RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 1
GPIO[7]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
GPIO[8]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
GPIO[9]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
GPIO[10]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P5RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 5
GPIO[11]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P6RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 6
GPIO[12]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P7RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 7
GPIO[13]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[14]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[15]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[16]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[17]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[18]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[19]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Table 4 General Purpose I/O Pins (Part 2 of 3)
6 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Signal
Type
Name/Description
GPIO[20]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[21]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 0
GPIO[22]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN1
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 1
GPIO[23]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN2
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 2
GPIO[24]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN3
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 3
GPIO[25]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[26]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[27]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[28]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[29]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[30]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[31]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN10
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 10
Table 4 General Purpose I/O Pins (Part 3 of 3)
7 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Signal
Type
Name/Description
CCLKDS
I
Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a
common clock is being used between the downstream device and the downstream
port.
CCLKUS
I
Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a
common clock is being used between the upstream device and the upstream port.
MSMBSMODE
I
Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 KHz. This value may not be overridden.
P01MERGEN
I
Port 0 and 1 Merge. When this pin is asserted, port 1 is merged with port 0 to form a
single x8 port. The SerDes lanes associated with port B become lanes 4 through 7 of
port 0.
P23MERGEN
I
Port 2 and 3 Merge. When this pin is asserted, port 3 is merged with port 2 to form a
single x8 port. The SerDes lanes associated with port D become lanes 4 through 7 of
port 2.
P45MERGEN
I
Port 4 and 5 Merge. When this pin is asserted, port 5 is merged with port 4 to form a
single x8 port. The SerDes lanes associated with port F become lanes 4 through 7 of
port 4.
P67MERGEN
I
Port 6 and 7 Merge. When this pin is asserted, port 7 is merged with port 6 to form a
single x8 port. The SerDes lanes associated with port H become lanes 4 through 7 of
port 6.
PERSTN
I
Fundamental Reset. Assertion of this signal resets all logic inside the PES32H8 and
initiates a PCI Express fundamental reset.
RSTHALT
I
Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the
PES32H8 executes the reset procedure and remains in a reset state with the Master
and Slave SMBuses active. This allows software to read and write registers internal to
the device before normal device operation begins. The device exits the reset state
when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master.
SWMODE[3:0]
I
Switch Mode. These configuration pins determine the PES32H8 switch operating
mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Normal switch mode with upstream port failover (port 0 selected as the
upstream port)
0x9 - Normal switch mode with upstream port failover (port 2 selected as the
upstream port)
0xA - Normal switch mode with Serial EEPROM initialization and upstream port
failover (port 0 selected as the upstream port)
0xB - Normal switch mode with Serial EEPROM initialization and upstream port
failover (port 2 selected as the upstream port)
0xC through 0xF - Reserved
Table 5 System Pins
8 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Signal
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data into or out of
the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system
clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG
Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary scan logic or
JTAG Controller. When no data is being shifted out, this signal is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the boundary
scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary scan logic
and JTAG TAP Controller. An external pull-up on the board is recommended to meet
the JTAG specification in cases where the tester can access this signal. However, for
systems running in functional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal
Type
VDDCORE
I
Core VDD. Power supply for core logic.
VDDIO
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPE
I
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
VDDAPE
I
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
VSS
I
Ground.
VTTPE
Name/Description
PCI Express Serial Data Transmit Termination Voltage. This pin allows
the driver termination voltage to be set, enabling the system designer to
control the Common Mode Voltage and output voltage swing of the corresponding PCI Serial Data Transmit differential pair.
Table 7 Power and Ground Pins
9 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Pin Characteristics
Note: Some input pads of the PES32H8 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function
Pin Name
Type
Buffer
I/O
Type
PCI Express Interface
PE0RN[3:0]
I
CML
Serial Link
PE0RP[3:0]
I
PE0TN[3:0]
O
PE0TP[3:0]
O
PE1RN[3:0]
I
PE1RP[3:0]
I
PE1TN[3:0]
O
PE1TP[3:0]
O
PE2RN[3:0]
I
PE2RP[3:0]
I
PE2TN[3:0]
O
PE2TP[3:0]
O
PE3RN[3:0]
I
PE3RP[3:0]
I
PE3TN[3:0]
O
PE3TP[3:0]
O
PE4RN[3:0]
I
PE4RP[3:0]
I
PE4TN[3:0]
O
PE4TP[3:0]
O
PE5RN[3:0]
I
PE5RP[3:0]
I
PE5TN[3:0]
O
PE5TP[3:0]
O
PE6RN[3:0]
I
PE6RP[3:0]
I
PE6TN[3:0]
O
PE6TP[3:0]
O
PE7RN[3:0]
I
PE7RP[3:0]
I
PE7TN[3:0]
O
PE7TP[3:0]
O
Internal
Resistor
Notes
Table 8 Pin Characteristics (Part 1 of 2)
10 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Function
Pin Name
Type
Buffer
I/O
Type
PCI Express Interface
(cont.)
PEREFCLKN[3:0]
I
PEREFCLKP[3:0]
I
LVPECL/
CML
Diff. Clock
Input
REFCLKM
I
LVTTL
Input
pull-down
MSMBADDR[4:1]
I
LVTTL
STI1
pull-up
MSMBCLK
I/O
STI
MSMBDAT
I/O
STI
SMBus
SSMBADDR[5,3:1]
I
SSMBCLK
I/O
STI
SSMBDAT
I/O
STI
General Purpose I/O
GPIO[31:0]
I/O
LVTTL
System Pins
CCLKDS
I
LVTTL
CCLKUS
I
EJTAG / JTAG
1.
Internal
Resistor
Refer to Table 9
pull-up
pull-up
Input
pull-up
pull-up
MSMBSMODE
I
pull-down
P01MERGEN
I
pull-down
P23MERGEN
I
pull-down
P45MERGEN
I
pull-down
P67MERGEN
I
pull-down
PERSTN
I
RSTHALT
I
pull-down
SWMODE[3:0]
I
pull-down
JTAG_TCK
I
LVTTL
STI
pull-up
STI
pull-up
JTAG_TDI
I
JTAG_TDO
O
JTAG_TMS
I
STI
pull-up
JTAG_TRST_N
I
STI
pull-up
Schmitt Trigger Input (STI).
Notes
External pull-down
Table 8 Pin Characteristics (Part 2 of 2)
11 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Logic Diagram — PES32H8
Reference
Clocks
PEREFCLKP[3:0]
PEREFCLKN[3:0]
REFCLKM
4
4
PE0TP[0]
PE0TN[0]
PE0RP[0]
PE0RN[0]
PE0RP[3]
PE0RN[3]
PE0TP[3]
PE0TN[3]
PCI Express
Switch
SerDes Input
Port 1
PE1RP[0]
PE1RN[0]
PE1TP[0]
PE1TN[0]
PE1RP[3]
PE1RN[3]
PE1TP[3]
PE1TN[3]
PCI Express
Switch
SerDes Input
Port 2
PE2RP[0]
PE2RN[0]
PE2TP[0]
PE2TN[0]
PE2RP[3]
PE2RN[3]
PE2TP[3]
PE2TN[3]
PCI Express
Switch
SerDes Input
Port 3
PE3RP[0]
PE3RN[0]
PE3TP[0]
PE3TN[0]
PCI Express
Switch
SerDes Input
Port 7
PE7RP[0]
PE7RN[0]
...
...
...
...
...
...
...
...
PCI Express
Switch
SerDes Input
Port 0
PE3TP[3]
PE3TN[3]
PES32H8
...
PE7TP[0]
PE7TN[0]
...
Master
SMBus Interface
PE7RP[3]
PE7RN[3]
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
PE7TP[3]
PE7TN[3]
4
4
32
System
Functions
MSMBSMODE
CCLKDS
CCLKUS
RSTHALT
PERSTN
SWMODE[3:0]
P01MERGEN
P23MERGEN
P45MERGEN
P67MERGEN
PCI Express
Switch
SerDes Output
Port 1
PCI Express
Switch
SerDes Output
Port 2
PCI Express
Switch
SerDes Output
Port 3
...
...
PE3RP[3]
PE3RN[3]
PCI Express
Switch
SerDes Output
Port 0
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
GPIO[31:0]
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
4
VDDCORE
VDDIO
VDDPE
VDDAPE
VSS
PCI Express
Switch
SerDes Output
Port 7
Slave
SMBus Interface
General Purpose
I/O
JTAG
Power/Ground
VTTPE
Figure 4 PES32H8 Logic Diagram
12 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Parameter
Description
Min
Typical
Max
Unit
1251
MHz
60
%
0.2*RCUI
RCUI3
1.6
V
125
ps
PEREFCLK
RefclkFREQ
Input reference clock frequency range
100
RefclkDC2
Duty cycle of input clock
40
TR, TF
Rise/Fall time of input clocks
VSW
Differential input voltage swing4
Tjitter
Input clock jitter (cycle-to-cycle)
50
0.6
Table 9 Input Clock Requirements
1. The input clock
frequency will be either 100 or 125 MHz depending on signal REFCLKM.
2.
ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
3.
RCUI (Reference Clock Unit Interval) refers to the reference clock period.
4. AC
coupling required.
AC Timing Characteristics
Parameter
Description
Min1
Typical1
Max1
Units
399.88
400
400.12
ps
0.7
.9
PCIe Transmit
UI
Unit Interval
TTX-EYE
Minimum Tx Eye Width
TTX-EYE-MEDIAN-toMAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median
TTX-RISE, TTX-FALL
D+ / D- Tx output rise/fall time
50
TTX- IDLE-MIN
Minimum time in idle
50
TTX-IDLE-SET-TO-
Maximum time to transition to a valid Idle after sending
an Idle ordered set
20
UI
IDLE
TTX-IDLE-TO-DIFF-
Maximum time to transition from valid idle to diff data
20
UI
500
1300
ps
400
400.12
ps
UI
0.15
90
UI
ps
UI
DATA
TTX-SKEW
Transmitter data skew between any 2 lanes
PCIe Receive
UI
Unit Interval
399.88
TRX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance)
TRX-EYE-MEDIUM TO
Max time between jitter median & max deviation
0.3
UI
Unexpected Idle Enter Detect Threshold Integration Time
10
ms
Lane to lane input skew
20
ns
0.4
UI
MAX JITTER
TRX-IDLE-DET-DIFFENTER TIME
TRX-SKEW
Table 10 PCIe AC Timing Characteristics
1. Minimum, Typical, and Maximum
values meet the requirements under PCI Specification 1.1
13 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Signal
Symbol
Reference
Edge
Min
Tpw_13b2
None
50
Max Unit
Timing
Diagram
Reference
GPIO
GPIO[31:0]1
—
ns
See Figure 5.
Table 11 GPIO AC Timing Characteristics
1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they
are asynchronous.
2.
The values for this symbol were determined by calculation, not by testing.
EXTCLK
Tpw_13b
GPIO (asynchronous input)
Figure 5 GPIO AC Timing Waveform
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Referenc
e
Tper_16a
none
50.0
—
ns
See Figure 6.
10.0
25.0
ns
2.4
—
ns
1.0
—
ns
—
20
ns
—
20
ns
25.0
—
ns
JTAG
JTAG_TCK
Thigh_16a,
Tlow_16a
JTAG_TMS1,
JTAG_TDI
JTAG_TDO
Tsu_16b
JTAG_TCK rising
Thld_16b
Tdo_16c
JTAG_TCK falling
Tdz_16c2
JTAG_TRST_N
Tpw_16d2
none
Table 12 JTAG AC Timing Characteristics
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determined by calculation, not by testing.
14 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
Thld_16b
Tsu_16b
JTAG_TDI
Thld_16b
Tsu_16b
JTAG_TMS
Tdo_16c
Tdz_16c
JTAG_TDO
Tpw_16d
JTAG_TRST_N
Figure 6 JTAG AC Timing Waveform
Recommended Operating Supply Voltages
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VDDCORE
Internal logic supply
0.9
1.0
1.1
V
VDDI/O
I/O supply except for SerDes LVPECL/CML
3.0
3.3
3.6
V
VDDPE
PCI Express Digital Power
0.9
1.0
1.1
V
VDDAPE
PCI Express Analog Power
0.9
1.0
1.1
V
VTTPE
PCI Express Serial Data Transmit
Termination Voltage
1.425
1.5
1.575
V
VSS
Common ground
0
0
0
V
Table 13 PES32H8 Operating Voltages
Power-Up Sequence
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the
PES32H8, the power-up sequence must be as follows:
1. VDDI/O — 3.3V
2. VDDCore, VDDPE, VDDAPE — 1.0V
3. VTTPE — 1.5V
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues
are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the
power-up sequence.
15 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Recommended Operating Temperature
Grade
Temperature
Commercial
0°C to +70°C Ambient
Industrial
-40°C to +85°C Ambient
Table 14 PES32H8 Operating Temperatures
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13 (and also listed below).
Core Supply
PCIe Digital
Supply
PCIe Analog
Supply
PCIe Termination Supply
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
1.5V
Max
1.575V
Typ
3.3V
Max
3.6V
Typ
Power
Max
Power
mA
1800
2100
1677
1990
792
909
804
826
1
2
5.5W
6.81W
Watts
1.81
2.31
1.68
2.19
0.79
1.0
1.21
1.3
0.003
0.01
Number of active
Lanes per Port
8/8/8/8
I/O Supply
Total
Table 15 PES32H8 Power Consumption
16 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Thermal Considerations
This section describes thermal considerations for the PES32H8 (31mm2 FCBGA900 package). The data in Table 16 below contains information
that is relevant to the thermal performance of the PES32H8 switch.
Symbol
Parameter
Value
TJ(max)
Junction Temperature
125
o
Maximum
70
o
Maximum
TA(max)
Ambient Temperature
Units
C
C
θJC
Thermal Resistance, Junction-to-Case
0.2
o
P
Power Dissipation of the Device
6.81
Watts
Conditions
C/W
Maximum
Table 16 Thermal Specifications for PES32H8, 31x31 mm FCBGA900 Package
Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value
specified in Table 16. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be
maintained below the value determined by the formula:
θJA = (TJ(max) - TA(max))/P
Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to
achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value
provided in Table 16), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the
circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 10 or
more layers AND the board size is larger than 4"x12" AND airflow in excess of 1 m/s is available. It is strongly recommended that users
perform their own thermal analysis for their own board and system design scenarios.
17 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13.
Note: See Table 8, Pin Characteristics, for a complete I/O listing.
I/O Type
Serial Link
Parameter
Min1
Description
Typ1
Max1
Unit
800
1200
mV
-3
-4
dB
3.7
V
Conditions
PCIe Transmit
VTX-DIFFp-p
VTX-DE-RATIO
Differential peak-to-peak output voltage
De-emphasized differential output voltage
VTX-DC-CM
DC Common mode voltage
VTX-CM-ACP
RMS AC peak common mode output voltage
20
mV
VTX-CM-DC-
Abs delta of DC common mode voltage
between L0 and idle
100
mV
Abs delta of DC common mode voltage
between D+ and D-
25
mV
Electrical idle diff peak output
20
mV
Voltage change during receiver detection
600
mV
active-idle-delta
VTX-CM-DC-linedelta
VTX-Idle-DiffP
VTX-RCV-Detect
-0.1
1
RLTX-DIFF
Transmitter Differential Return loss
12
dB
RLTX-CM
Transmitter Common Mode Return loss
6
dB
ZTX-DEFF-DC
DC Differential TX impedance
80
100
120
Ω
ZOSE
Single ended TX Impedance
40
50
60
Ω
Transmitter Eye
Diagram
TX Eye Height (De-emphasized bits)
505
650
mV
Transmitter Eye
Diagram
TX Eye Height (Transition bits)
800
950
mV
VRX-DIFFp-p
Differential input voltage (peak-to-peak)
175
VRX-CM-AC
Receiver common-mode voltage for AC
coupling
RLRX-DIFF
Receiver Differential Return Loss
15
dB
RLRX-CM
Receiver Common Mode Return Loss
6
dB
Differential input impedance (DC)
80
100
120
Ω
Single-ended input impedance
40
50
60
Ω
200k
350k
PCIe Receive
ZRX-DIFF-DC
ZRX-COMM-DC
ZRX-COMM-HIGH- Powered down input common mode
impedance (DC)
Z-DC
VRX-IDLE-DET-
Electrical idle detect threshold
65
Input Capacitance
1.5
1200
mV
150
mV
Ω
175
mV
DIFFp-p
PCIe REFCLK
CIN
—
pF
Table 17 DC Electrical Characteristics (Part 1 of 2)
18 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
I/O Type
Min1
Typ1
Max1
Unit
Conditions
IOL
—
2.5
—
mA
VOL = 0.4v
IOH
—
-5.5
—
mA
VOH = 1.5V
IOL
—
12.0
—
mA
VOL = 0.4v
IOH
—
-20.0
—
mA
VOH = 1.5V
Parameter
Description
Other I/Os
LOW Drive
Output
High Drive
Output
Schmitt Trigger Input
(STI)
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDIO +
0.5
V
—
Input
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDIO +
0.5
V
—
CIN
—
—
8.5
pF
—
Inputs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK W/O
Pull-ups/downs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK WITH
Pull-ups/downs
—
—
+ 80
μA
VDDI/O (max)
Capacitance
Leakage
Table 17 DC Electrical Characteristics (Part 2 of 2)
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a.
19 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Package Pinout — 900-BGA Signal Pinout for PES32H8
The following table lists the pin numbers and signal names for the PES32H8 device.
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
A1
VSS
B5
VSS
C9
VSS
D13
VSS
A2
VSS
B6
VSS
C10
VSS
D14
PE3RP01
A3
GPIO_19
B7
VSS
C11
VSS
D15
PE3RP00
A4
VDDIO
B8
VSS
C12
VSS
D16
VSS
A5
VSS
B9
VSS
C13
VSS
D17
PE2RP03
A6
VSS
B10
VSS
C14
VSS
D18
PE2RP02
A7
VSS
B11
PE3TN03
C15
VSS
D19
VSS
A8
VSS
B12
PE3TN02
C16
VSS
D20
PE2RP01
A9
VSS
B13
VSS
C17
VSS
D21
PE2RP00
A10
VSS
B14
PE3TN01
C18
VSS
D22
VSS
A11
PE3TP03
B15
PE3TN00
C19
VSS
D23
VSS
A12
PE3TP02
B16
VSS
C20
VSS
D24
VSS
A13
VSS
B17
PE2TN03
C21
VSS
D25
VSS
A14
PE3TP01
B18
PE2TN02
C22
VSS
D26
JTAG_TMS
A15
PE3TP00
B19
VSS
C23
VSS
D27
VDDIO
A16
VSS
B20
PE2TN01
C24
VSS
D28
SSMBADDR_5
A17
PE2TP03
B21
PE2TN00
C25
VSS
D29
SSMBADDR_3
A18
PE2TP02
B22
VSS
C26
MSMBADDR_4
D30
VDDIO
A19
VSS
B23
VSS
C27
JTAG_TDI
E1
VDDIO
A20
PE2TP01
B24
VSS
C28
JTAG_TRST_N
E2
GPIO_30
A21
PE2TP00
B25
VSS
C29
SSMBADDR_2
E3
GPIO_31
1
A22
VSS
B26
MSMBADDR_3
C30
SSMBADDR_1
E4
GPIO_24
1
A23
VSS
B27
MSMBADDR_2
D1
GPIO_28
1
E5
VSS
A24
VSS
B28
PERSTN
D2
GPIO_26
1
E6
VSS
A25
VSS
B29
VDDIO
D3
VDDIO
E7
VSS
A26
VDDIO
B30
VSS
D4
GPIO_23
E8
VSS
A27
MSMBADDR_1
C1
GPIO_29
D5
VSS
E9
PEREFCLKP1
A28
MSMBSMODE
C2
GPIO_27
1
D6
VSS
E10
VSS
A29
VSS
C3
GPIO_21
1
D7
VSS
E11
PE3RN03
A30
VSS
C4
GPIO_16
D8
VSS
E12
PE3RN02
B1
VSS
C5
VSS
D9
PEREFCLKN1
E13
VSS
B2
VDDIO
C6
VSS
D10
VSS
E14
PE3RN01
B3
GPIO_18
C7
VSS
D11
PE3RP03
E15
PE3RN00
B4
GPIO_17
C8
VSS
D12
PE3RP02
E16
VSS
1
Table 18 PES32H8 900-pin Signal Pin-Out (Part 1 of 7)
20 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
E17
PE2RN03
F23
VSS
G29
VSS
J5
PEREFCLKN2
E18
PE2RN02
F24
MSMBDAT
G30
VSS
J6
VSS
E19
VSS
F25
VDDIO
H1
VSS
J7
VSS
E20
PE2RN01
F26
SSMBCLK
H2
VSS
J8
VSS
E21
PE2RN00
F27
VSS
H3
VSS
J9
VSS
E22
VSS
F28
VSS
H4
VSS
J10
VSS
E23
VSS
F29
VSS
H5
VSS
J11
VDDPE
E24
VSS
F30
VSS
H6
VSS
J12
VDDPE
E25
MSMBCLK
G1
VSS
H7
VDDIO
J13
VDDPE
E26
VSS
G2
VSS
H8
GPIO_22
J14
VSS
E27
VSS
G3
VSS
H9
VSS
J15
VDDPE
E28
VSS
G4
VSS
H10
VSS
J16
VDDPE
E29
VSS
G5
VSS
H11
VTTPE
J17
VSS
E30
VSS
G6
VSS
H12
VSS
J18
VDDPE
F1
VSS
G7
GPIO_25
H13
VDDAPE
J19
VDDPE
F2
VSS
G8
VSS
H14
VSS
J20
VDDPE
F3
VSS
G9
VSS
H15
VTTPE
J21
VSS
F4
VSS
G10
VSS
H16
VTTPE
J22
VSS
F5
VSS
G11
VSS
H17
VSS
J23
VSS
F6
GPIO_20
G12
VDDPE
H18
VDDAPE
J24
VSS
F7
VDDIO
G13
VSS
H19
VSS
J25
VSS
F8
VSS
G14
VSS
H20
VTTPE
J26
VSS
F9
VSS
G15
VTTPE
H21
VSS
J27
VSS
F10
VSS
G16
VTTPE
H22
VSS
J28
VSS
F11
VSS
G17
VSS
H23
CCLKDS
J29
VSS
F12
VSS
G18
VSS
H24
JTAG_TCK
J30
VSS
F13
VSS
G19
VDDPE
H25
VSS
K1
VSS
F14
VSS
G20
VSS
H26
VSS
K2
VSS
F15
VSS
G21
VSS
H27
VSS
K3
VSS
F16
VSS
G22
VSS
H28
VSS
K4
VSS
F17
VSS
G23
JTAG_TDO
H29
VSS
K5
VSS
F18
VSS
G24
VDDIO
H30
VSS
K6
VSS
F19
VSS
G25
SSMBDAT
J1
VSS
K7
VSS
F20
VSS
G26
VSS
J2
VSS
K8
VSS
F21
VSS
G27
VSS
J3
VSS
K9
VSS
F22
VSS
G28
VSS
J4
PEREFCLKP2
K10
VSS
1
1
Alt
Table 18 PES32H8 900-pin Signal Pin-Out (Part 2 of 7)
21 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
K11
VDDPE
L17
VDDCORE
M23
VSS
N29
PE1TN01
K12
VSS
L18
VDDCORE
M24
VDDPE
N30
PE1TP01
K13
VDDPE
L19
VDDCORE
M25
VSS
P1
PE4TP02
K14
VSS
L20
VDDCORE
M26
VSS
P2
PE4TN02
K15
VDDPE
L21
VDDPE
M27
VSS
P3
VSS
K16
VDDPE
L22
VDDPE
M28
VSS
P4
PE4RP02
K17
VSS
L23
VTTPE
M29
VSS
P5
PE4RN02
K18
VDDPE
L24
VSS
M30
VSS
P6
VSS
K19
VSS
L25
VSS
N1
VSS
P7
VSS
K20
VDDPE
L26
PE1RN02
N2
VSS
P8
VSS
K21
VSS
L27
PE1RP02
N3
VSS
P9
VSS
K22
VSS
L28
VSS
N4
VSS
P10
VSS
K23
VSS
L29
PE1TN02
N5
VSS
P11
VSS
K24
VSS
L30
PE1TP02
N6
VSS
P12
VSS
K25
VSS
M1
PE4TP01
N7
VSS
P13
VDDCORE
K26
PE1RN03
M2
PE4TN01
N8
VDDAPE
P14
VSS
K27
PE1RP03
M3
VSS
N9
VDDPE
P15
VDDCORE
K28
VSS
M4
PE4RP01
N10
VDDPE
P16
VSS
K29
PE1TN03
M5
PE4RN01
N11
VDDCORE
P17
VDDCORE
K30
PE1TP03
M6
VSS
N12
VDDCORE
P18
VSS
L1
PE4TP00
M7
VDDPE
N13
VSS
P19
VDDCORE
L2
PE4TN00
M8
VSS
N14
VDDCORE
P20
VDDCORE
L3
VSS
M9
VDDPE
N15
VSS
P21
VSS
L4
PE4RP00
M10
VSS
N16
VDDCORE
P22
VSS
L5
PE4RN00
M11
VDDCORE
N17
VSS
P23
VSS
L6
VSS
M12
VSS
N18
VDDCORE
P24
VSS
L7
VSS
M13
VDDCORE
N19
VSS
P25
VSS
L8
VTTPE
M14
VSS
N20
VDDCORE
P26
PE1RN00
L9
VDDPE
M15
VDDCORE
N21
VDDPE
P27
PE1RP00
L10
VDDPE
M16
VSS
N22
VDDPE
P28
VSS
L11
VDDCORE
M17
VDDCORE
N23
VDDAPE
P29
PE1TN00
L12
VDDCORE
M18
VSS
N24
VSS
P30
PE1TP00
L13
VDDCORE
M19
VDDCORE
N25
VSS
R1
PE4TP03
L14
VSS
M20
VDDCORE
N26
PE1RN01
R2
PE4TN03
L15
VDDCORE
M21
VSS
N27
PE1RP01
R3
VSS
L16
VSS
M22
VDDPE
N28
VSS
R4
PE4RP03
Alt
Table 18 PES32H8 900-pin Signal Pin-Out (Part 3 of 7)
22 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
R5
PE4RN03
T11
VSS
U17
VSS
V23
VDDAPE
R6
VSS
T12
VSS
U18
VDDCORE
V24
VSS
R7
VTTPE
T13
VDDCORE
U19
VSS
V25
VSS
R8
VTTPE
T14
VSS
U20
VSS
V26
VSS
R9
VDDPE
T15
VDDCORE
U21
VSS
V27
VSS
R10
VDDPE
T16
VSS
U22
VSS
V28
VSS
R11
VDDCORE
T17
VDDCORE
U23
VSS
V29
VSS
R12
VDDCORE
T18
VSS
U24
VSS
V30
VSS
R13
VSS
T19
VDDCORE
U25
VSS
W1
VSS
R14
VDDCORE
T20
VDDCORE
U26
PE0RN02
W2
VSS
R15
VSS
T21
VDDPE
U27
PE0RP02
W3
VSS
R16
VDDCORE
T22
VDDPE
U28
VSS
W4
VSS
R17
VSS
T23
VTTPE
U29
PE0TN02
W5
VSS
R18
VDDCORE
T24
VTTPE
U30
PE0TP02
W6
VSS
R19
VSS
T25
VSS
V1
PE5TP01
W7
VDDPE
R20
VSS
T26
PE0RN03
V2
PE5TN01
W8
VSS
R21
VDDPE
T27
PE0RP03
V3
VSS
W9
VDDPE
R22
VDDPE
T28
VSS
V4
PE5RP01
W10
VSS
R23
VTTPE
T29
PE0TN03
V5
PE5RN01
W11
VDDCORE
R24
VTTPE
T30
PE0TP03
V6
VSS
W12
VDDCORE
R25
VSS
U1
PE5TP00
V7
VSS
W13
VSS
R26
VSS
U2
PE5TN00
V8
VDDAPE
W14
VDDCORE
R27
VSS
U3
VSS
V9
VDDPE
W15
VSS
R28
VSS
U4
PE5RP00
V10
VDDPE
W16
VDDCORE
R29
VSS
U5
PE5RN00
V11
VDDCORE
W17
VSS
R30
VSS
U6
VSS
V12
VSS
W18
VDDCORE
T1
VSS
U7
VSS
V13
VDDCORE
W19
VSS
T2
VSS
U8
VSS
V14
VSS
W20
VDDCORE
T3
VSS
U9
VSS
V15
VDDCORE
W21
VSS
T4
VSS
U10
VSS
V16
VSS
W22
VDDPE
T5
VSS
U11
VDDCORE
V17
VDDCORE
W23
VSS
T6
VSS
U12
VDDCORE
V18
VSS
W24
VDDPE
T7
VTTPE
U13
VSS
V19
VDDCORE
W25
VSS
T8
VTTPE
U14
VDDCORE
V20
VDDCORE
W26
PE0RN01
T9
VDDPE
U15
VSS
V21
VDDPE
W27
PE0RP01
T10
VDDPE
U16
VDDCORE
V22
VDDPE
W28
VSS
Alt
Table 18 PES32H8 900-pin Signal Pin-Out (Part 4 of 7)
23 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
W29
PE0TN01
AA5
PE5RN03
AB11
VDDPE
AC17
VSS
W30
PE0TP01
AA6
VSS
AB12
VDDPE
AC18
VDDAPE
Y1
PE5TP02
AA7
VSS
AB13
VDDPE
AC19
VSS
Y2
PE5TN02
AA8
VSS
AB14
VSS
AC20
VTTPE
Y3
VSS
AA9
VSS
AB15
VDDPE
AC21
VSS
Y4
PE5RP02
AA10
VSS
AB16
VDDPE
AC22
VSS
Y5
PE5RN02
AA11
VDDPE
AB17
VSS
AC23
GPIO_06
Y6
VSS
AA12
VSS
AB18
VDDPE
AC24
VDDIO
Y7
VSS
AA13
VDDPE
AB19
VDDPE
AC25
VSS
Y8
VTTPE
AA14
VSS
AB20
VDDPE
AC26
VSS
Y9
VDDPE
AA15
VDDPE
AB21
VSS
AC27
VSS
Y10
VDDPE
AA16
VDDPE
AB22
VSS
AC28
VSS
Y11
VDDCORE
AA17
VSS
AB23
VSS
AC29
VSS
Y12
VDDCORE
AA18
VDDPE
AB24
VSS
AC30
VSS
Y13
VDDCORE
AA19
VSS
AB25
VSS
AD1
VSS
Y14
VDDCORE
AA20
VDDPE
AB26
PEREFCLKN0
AD2
VSS
Y15
VSS
AA21
VSS
AB27
PEREFCLKP0
AD3
VSS
Y16
VDDCORE
AA22
VSS
AB28
VSS
AD4
VSS
Y17
VSS
AA23
VSS
AB29
VSS
AD5
VSS
Y18
VDDCORE
AA24
VSS
AB30
VSS
AD6
VSS
Y19
VDDCORE
AA25
VSS
AC1
VSS
AD7
VDDIO
Y20
VDDCORE
AA26
VSS
AC2
VSS
AD8
VDDIO
Y21
VDDPE
AA27
VSS
AC3
VSS
AD9
VSS
Y22
VDDPE
AA28
VSS
AC4
VSS
AD10
VSS
Y23
VTTPE
AA29
VSS
AC5
VSS
AD11
VSS
Y24
VSS
AA30
VSS
AC6
VSS
AD12
VDDPE
Y25
VSS
AB1
VSS
AC7
VDDIO
AD13
VSS
Y26
PE0RN00
AB2
VSS
AC8
VDDIO
AD14
VSS
Y27
PE0RP00
AB3
VSS
AC9
VSS
AD15
VTTPE
Y28
VSS
AB4
VSS
AC10
VSS
AD16
VTTPE
Y29
PE0TN00
AB5
VSS
AC11
VTTPE
AD17
VSS
Y30
PE0TP00
AB6
VSS
AC12
VSS
AD18
VSS
AA1
PE5TP03
AB7
VSS
AC13
VDDAPE
AD19
VDDPE
AA2
PE5TN03
AB8
VSS
AC14
VSS
AD20
VSS
AA3
VSS
AB9
VSS
AC15
VTTPE
AD21
VSS
AA4
PE5RP03
AB10
VSS
AC16
VTTPE
AD22
VSS
Alt
1
Table 18 PES32H8 900-pin Signal Pin-Out (Part 5 of 7)
24 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
AE29
VSS
AG5
VSS
AH11
VSS
AE30
VSS
AG6
VSS
AH12
VSS
VSS
AF1
VSS
AG7
VSS
AH13
VSS
AD26
VSS
AF2
VSS
AG8
VSS
AH14
VSS
AD27
VSS
AF3
VSS
AG9
VSS
AH15
VSS
AD28
VSS
AF4
VSS
AG10
PE6RP00
AH16
VSS
AD29
VSS
AF5
VSS
AG11
PE6RP01
AH17
VSS
AD30
VSS
AF6
REFCLKM
AG12
VSS
AH18
VSS
AE1
VSS
AF7
VSS
AG13
PE6RP02
AH19
VSS
AE2
VSS
AF8
VSS
AG14
PE6RP03
AH20
VSS
AE3
VSS
AF9
VSS
AG15
VSS
AH21
VSS
AE4
VSS
AF10
PE6RN00
AG16
PE7RP00
AH22
VSS
AE5
CCLKUS
AF11
PE6RN01
AG17
PE7RP01
AH23
VSS
AE6
VDDIO
AF12
VSS
AG18
VSS
AH24
VSS
AE7
VSS
AF13
PE6RN02
AG19
PE7RP02
AH25
VSS
AE8
VSS
AF14
PE6RN03
AG20
PE7RP03
AH26
VSS
AE9
VSS
AF15
VSS
AG21
VSS
AH27
GPIO_00
AE10
VSS
AF16
PE7RN00
AG22
PEREFCLKN3
AH28
GPIO_05
1
AE11
VSS
AF17
PE7RN01
AG23
VSS
AH29
GPIO_11
1
AE12
VSS
AF18
VSS
AG24
VSS
AH30
GPIO_13
AE13
VSS
AF19
PE7RN02
AG25
VSS
AJ1
VSS
AE14
VSS
AF20
PE7RN03
AG26
VSS
AJ2
VDDIO
AE15
VSS
AF21
VSS
AG27
GPIO_07
AJ3
VSS
AE16
VSS
AF22
PEREFCLKP3
AG28
VDDIO
AJ4
SWMODE_0
AE17
VSS
AF23
VSS
AG29
GPIO_10
1
AJ5
SWMODE_2
AE18
VSS
AF24
VSS
AG30
GPIO_12
1
AJ6
VSS
AE19
VSS
AF25
VSS
AH1
P23MERGEN
AJ7
VSS
AE20
VSS
AF26
VSS
AH2
P67MERGEN
AJ8
VSS
AE21
VSS
AF27
GPIO_08
AH3
VSS
AJ9
VSS
AE22
VSS
AF28
GPIO_15
AH4
VSS
AJ10
PE6TN00
AE23
VSS
AF29
GPIO_14
AH5
SWMODE_3
AJ11
PE6TN01
AE24
VDDIO
AF30
VDDIO
AH6
VSS
AJ12
VSS
AE25
GPIO_04
AG1
VDDIO
AH7
VSS
AJ13
PE6TN02
AE26
VSS
AG2
P01MERGEN
AH8
VSS
AJ14
PE6TN03
AE27
VSS
AG3
P45MERGEN
AH9
VSS
AJ15
VSS
AE28
VSS
AG4
VDDIO
AH10
VSS
AJ16
PE7TN00
AD23
VSS
AD24
GPIO_09
AD25
1
1
1
Table 18 PES32H8 900-pin Signal Pin-Out (Part 6 of 7)
25 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
AJ17
PE7TN01
AJ28
GPIO_02
AK9
VSS
AK20
PE7TP03
AJ18
VSS
AJ29
VDDIO
AK10
PE6TP00
AK21
VSS
AJ19
PE7TN02
AJ30
VSS
AK11
PE6TP01
AK22
VSS
AJ20
PE7TN03
AK1
VSS
AK12
VSS
AK23
VSS
AJ21
VSS
AK2
VSS
AK13
PE6TP02
AK24
VSS
AJ22
VSS
AK3
RSTHALT
AK14
PE6TP03
AK25
VSS
AJ23
VSS
AK4
SWMODE_1
AK15
VSS
AK26
VSS
AJ24
VSS
AK5
VDDIO
AK16
PE7TP00
AK27
VDDIO
AJ25
VSS
AK6
VSS
AK17
PE7TP01
AK28
GPIO_03
AJ26
VSS
AK7
VSS
AK18
VSS
AK29
VSS
AJ27
GPIO_01
AK8
VSS
AK19
PE7TP02
AK30
VSS
Alt
Table 18 PES32H8 900-pin Signal Pin-Out (Part 7 of 7)
Alternate Signal Functions
Pin
GPIO
Alternate
Pin
GPIO
Alternate
AH28
GPIO_05
GPEN
H8
GPIO_22
IOEXPINTN1
AC23
GPIO_06
P1RSTN
D4
GPIO_23
IOEXPINTN2
AG27
GPIO_07
P2RSTN
E4
GPIO_24
IOEXPINTN3
AF27
GPIO_08
P3RSTN
G7
GPIO_25
IOEXPINTN4
AD24
GPIO_09
P4RSTN
D2
GPIO_26
IOEXPINTN5
AG29
GPIO_10
P5RSTN
C2
GPIO_27
IOEXPINTN6
AH29
GPIO_11
P6RSTN
D1
GPIO_28
IOEXPINTN7
AG30
GPIO_12
P7RSTN
E3
GPIO_31
IOEXPINTN10
C3
GPIO_21
IOEXPINTN0
Table 19 PES32H8 Alternate Signal Functions
26 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Power Pins
VDDCore
VDDCore
VDDIO
VDDPE
VDDPE
VDDAPE
VTTPE
L11
T17
A4
G12
T9
H13
G15
L12
T19
A26
G19
T10
H18
G16
L13
T20
B2
J11
T21
N8
H11
L15
U11
B29
J12
T22
N23
H15
L17
U12
D3
J13
V9
V8
H16
L18
U14
D27
J15
V10
V23
H20
L19
U16
D30
J16
V21
AC13
L8
L20
U18
E1
J18
V22
AC18
L23
M11
V11
F7
J19
W7
R7
M13
V13
F25
J20
W9
R8
M15
V15
G24
K11
W22
R23
M17
V17
H7
K13
W24
R24
M19
V19
AC7
K15
Y9
T7
M20
V20
AC8
K16
Y10
T8
N11
W11
AC24
K18
Y21
T23
N12
W12
AD7
K20
Y22
T24
N14
W14
AD8
L9
AA11
Y8
N16
W16
AE6
L10
AA13
Y23
N18
W18
AE24
L21
AA15
AC11
N20
W20
AF30
L22
AA16
AC15
P13
Y11
AG1
M7
AA18
AC16
P15
Y12
AG4
M9
AA20
AC20
P17
Y13
AG28
M22
AB11
AD15
P19
Y14
AJ2
M24
AB12
AD16
P20
Y16
AJ29
N9
AB13
R11
Y18
AK5
N10
AB15
R12
Y19
AK27
N21
AB16
R14
Y20
N22
AB18
R16
R9
AB19
R18
R10
AB20
T13
R21
AD12
T15
R22
AD19
Table 20 PES32H8 Power Pins
27 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Ground Pins
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A1
C8
E13
F30
H21
K8
M29
R13
A2
C9
E16
G1
H22
K9
M30
R15
A5
C10
E19
G2
H25
K10
N1
R17
A6
C11
E22
G3
H26
K12
N2
R19
A7
C12
E23
G4
H27
K14
N3
R20
A8
C13
E24
G5
H28
K17
N4
R25
A9
C14
E26
G6
H29
K19
N5
R26
A10
C15
E27
G8
H30
K21
N6
R27
A13
C16
E28
G9
J1
K22
N7
R28
A16
C17
E29
G10
J2
K23
N13
R29
A19
C18
E30
G11
J3
K24
N15
R30
A22
C19
F1
G13
J6
K25
N17
T1
A23
C20
F2
G14
J7
K28
N19
T2
A24
C21
F3
G17
J8
L3
N24
T3
A25
C22
F4
G18
J9
L6
N25
T4
A29
C23
F5
G20
J10
L7
N28
T5
A30
C24
F8
G21
J14
L14
P3
T6
B1
C25
F9
G22
J17
L16
P6
T11
B5
D5
F10
G26
J21
L24
P7
T12
B6
D6
F11
G27
J22
L25
P8
T14
B7
D7
F12
G28
J23
L28
P9
T16
B8
D8
F13
G29
J24
M3
P10
T18
B9
D10
F14
G30
J25
M6
P11
T25
B10
D13
F15
H1
J26
M8
P12
T28
B13
D16
F16
H2
J27
M10
P14
U3
B16
D19
F17
H3
J28
M12
P16
U6
B19
D22
F18
H4
J29
M14
P18
U7
B22
D23
F19
H5
J30
M16
P21
U8
B23
D24
F20
H6
K1
M18
P22
U9
B24
D25
F21
H9
K2
M21
P23
U10
B25
E5
F22
H10
K3
M23
P24
U13
B30
E6
F23
H12
K4
M25
P25
U15
C5
E7
F27
H14
K5
M26
P28
U17
C6
E8
F28
H17
K6
M27
R3
U19
C7
E10
F29
H19
K7
M28
R6
U20
Table 21 PES32H8 Ground Pins (Part 1 of 2)
28 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U21
W17
AA27
AC9
AD23
AE28
AG25
AJ9
U22
W19
AA28
AC10
AD25
AE29
AG26
AJ12
U23
W21
AA29
AC12
AD26
AE30
AH3
AJ15
U24
W23
AA30
AC14
AD27
AF1
AH4
AJ18
U25
W25
AB1
AC17
AD28
AF2
AH6
AJ21
U28
W28
AB2
AC19
AD29
AF3
AH7
AJ22
V3
Y3
AB3
AC21
AD30
AF4
AH8
AJ23
V6
Y6
AB4
AC22
AE1
AF5
AH9
AJ24
V7
Y7
AB5
AC25
AE2
AF7
AH10
AJ25
V12
Y15
AB6
AC26
AE3
AF8
AH11
AJ26
V14
Y17
AB7
AC27
AE4
AF9
AH12
AJ30
V16
Y24
AB8
AC28
AE7
AF12
AH13
AK1
V18
Y25
AB9
AC29
AE8
AF15
AH14
AK2
V24
Y28
AB10
AC30
AE9
AF18
AH15
AK6
V25
AA3
AB14
AD1
AE10
AF21
AH16
AK7
V26
AA6
AB17
AD2
AE11
AF23
AH17
AK8
V27
AA7
AB21
AD3
AE12
AF24
AH18
AK9
V28
AA8
AB22
AD4
AE13
AF25
AH19
AK12
V29
AA9
AB23
AD5
AE14
AF26
AH20
AK15
V30
AA10
AB24
AD6
AE15
AG5
AH21
AK18
W1
AA12
AB25
AD9
AE16
AG6
AH22
AK21
W2
AA14
AB28
AD10
AE17
AG7
AH23
AK22
W3
AA17
AB29
AD11
AE18
AG8
AH24
AK23
W4
AA19
AB30
AD13
AE19
AG9
AH25
AK24
W5
AA21
AC1
AD14
AE20
AG12
AH26
AK25
W6
AA22
AC2
AD17
AE21
AG15
AJ1
AK26
W8
AA23
AC3
AD18
AE22
AG18
AJ3
AK29
W10
AA24
AC4
AD20
AE23
AG21
AJ6
AK30
W13
AA25
AC5
AD21
AE26
AG23
AJ7
W15
AA26
AC6
AD22
AE27
AG24
AJ8
Table 21 PES32H8 Ground Pins (Part 2 of 2)
29 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Signals Listed Alphabetically
Signal Name
I/O Type
Location
Signal Category
CCLKDS
I
H23
System
CCLKUS
I
AE5
GPIO_00
I/O
AH27
GPIO_01
I/O
AJ27
GPIO_02
I/O
AJ28
GPIO_03
I/O
AK28
GPIO_04
I/O
AE25
GPIO_05
I/O
AH28
GPIO_06
I/O
AC23
GPIO_07
I/O
AG27
GPIO_08
I/O
AF27
GPIO_09
I/O
AD24
GPIO_10
I/O
AG29
GPIO_11
I/O
AH29
GPIO_12
I/O
AG30
GPIO_13
I/O
AH30
GPIO_14
I/O
AF29
GPIO_15
I/O
AF28
GPIO_16
I/O
C4
GPIO_17
I/O
B4
GPIO_18
I/O
B3
GPIO_19
I/O
A3
GPIO_20
I/O
F6
GPIO_21
I/O
C3
GPIO_22
I/O
H8
GPIO_23
I/O
D4
GPIO_24
I/O
E4
GPIO_25
I/O
G7
GPIO_26
I/O
D2
GPIO_27
I/O
C2
GPIO_28
I/O
D1
GPIO_29
I/O
C1
GPIO_30
I/O
E2
GPIO_31
I/O
E3
General Purpose I/O
General Purpose I/O (cont.)
Table 22 89PES32H8 Alphabetical Signal List (Part 1 of 6)
30 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Signal Name
I/O Type
Location
Signal Category
JTAG_TCK
I
H24
Test
JTAG_TDI
I
C27
JTAG_TDO
O
G23
JTAG_TMS
I
D26
JTAG_TRST_N
I
C28
MSMBADDR_1
I
A27
MSMBADDR_2
I
B27
MSMBADDR_3
I
B26
MSMBADDR_4
I
C26
MSMBCLK
I/O
E25
MSMBDAT
I/O
F24
MSMBSMODE
I
A28
P01MERGEN
I
AG2
P23MERGEN
I
AH1
P45MERGEN
I
AG3
P67MERGEN
I
AH2
PE0RN00
I
Y26
PE0RN01
I
W26
PE0RN02
I
U26
PE0RN03
I
T26
PE0RP00
I
Y27
PE0RP01
I
W27
PE0RP02
I
U27
PE0RP03
I
T27
PE0TN00
O
Y29
PE0TN01
O
W29
PE0TN02
O
U29
PE0TN03
O
T29
PE0TP00
O
Y30
PE0TP01
O
W30
PE0TP02
O
U30
PE0TP03
O
T30
PE1RN00
I
P26
PE1RN01
I
N26
PE1RN02
I
L26
SMBus Interface
System
PCI Express
Table 22 89PES32H8 Alphabetical Signal List (Part 2 of 6)
31 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Signal Name
I/O Type
Location
Signal Category
PE1RN03
I
K26
PCI Express (cont.)
PE1RP00
I
P27
PE1RP01
I
N27
PE1RP02
I
L27
PE1RP03
I
K27
PE1TN00
O
P29
PE1TN01
O
N29
PE1TN02
O
L29
PE1TN03
O
K29
PE1TP00
O
P30
PE1TP01
O
N30
PE1TP02
O
L30
PE1TP03
O
K30
PE2RN00
I
E21
PE2RN01
I
E20
PE2RN02
I
E18
PE2RN03
I
E17
PE2RP00
I
D21
PE2RP01
I
D20
PE2RP02
I
D18
PE2RP03
I
D17
PE2TN00
O
B21
PE2TN01
O
B20
PE2TN02
O
B18
PE2TN03
O
B17
PE2TP00
O
A21
PE2TP01
O
A20
PE2TP02
O
A18
PE2TP03
O
A17
PE3RN00
I
E15
PE3RN01
I
E14
PE3RN02
I
E12
PE3RN03
I
E11
PE3RP00
I
D15
PE3RP01
I
D14
PE3RP02
I
D12
Table 22 89PES32H8 Alphabetical Signal List (Part 3 of 6)
32 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Signal Name
I/O Type
Location
Signal Category
PE3RP03
I
D11
PCI Express (cont.)
PE3TN00
O
B15
PE3TN01
O
B14
PE3TN02
O
B12
PE3TN03
O
B11
PE3TP00
O
A15
PE3TP01
O
A14
PE3TP02
O
A12
PE3TP03
O
A11
PE4RN00
I
L5
PE4RN01
I
M5
PE4RN02
I
P5
PE4RN03
I
R5
PE4RP00
I
L4
PE4RP01
I
M4
PE4RP02
I
P4
PE4RP03
I
R4
PE4TN00
O
L2
PE4TN01
O
M2
PE4TN02
O
P2
PE4TN03
O
R2
PE4TP00
O
L1
PE4TP01
O
M1
PE4TP02
O
P1
PE4TP03
O
R1
PE5RN00
I
U5
PE5RN01
I
V5
PE5RN02
I
Y5
PE5RN03
I
AA5
PE5RP00
I
U4
PE5RP01
I
V4
PE5RP02
I
Y4
PE5RP03
I
AA4
PE5TN00
O
U2
PE5TN01
O
V2
PE5TN02
O
Y2
Table 22 89PES32H8 Alphabetical Signal List (Part 4 of 6)
33 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Signal Name
I/O Type
Location
Signal Category
PE5TN03
O
AA2
PCI Express (cont.)
PE5TP00
O
U1
PE5TP01
O
V1
PE5TP02
O
Y1
PE5TP03
O
AA1
PE6RN00
I
AF10
PE6RN01
I
AF11
PE6RN02
I
AF13
PE6RN03
I
AF14
PE6RP00
I
AG10
PE6RP01
I
AG11
PE6RP02
I
AG13
PE6RP03
I
AG14
PE6TN00
O
AJ10
PE6TN01
O
AJ11
PE6TN02
O
AJ13
PE6TN03
O
AJ14
PE6TP00
O
AK10
PE6TP01
O
AK11
PE6TP02
O
AK13
PE6TP03
O
AK14
PE7RN00
I
AF16
PE7RN01
I
AF17
PE7RN02
I
AF19
PE7RN03
I
AF20
PE7RP00
I
AG16
PE7RP01
I
AG17
PE7RP02
I
AG19
PE7RP03
I
AG20
PE7TN00
O
AJ16
PE7TN01
O
AJ17
PE7TN02
O
AJ19
PE7TN03
O
AJ20
PE7TP00
O
AK16
PE7TP01
O
AK17
PE7TP02
O
AK19
Table 22 89PES32H8 Alphabetical Signal List (Part 5 of 6)
34 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Signal Name
I/O Type
Location
Signal Category
PE7TP03
O
AK20
PCI Express (cont.)
PEREFCLKN0
I
AB26
PEREFCLKN1
I
D9
PEREFCLKN2
I
J5
PEREFCLKN3
I
AG22
PEREFCLKP0
I
AB27
PEREFCLKP1
I
E9
PEREFCLKP2
I
J4
PEREFCLKP3
I
AF22
PERSTN
I
B28
System
REFCLKM
I
AF6
PCI Express
RSTHALT
I
AK3
System
SSMBADDR_1
I
C30
SMBus Interface
SSMBADDR_2
I
C29
SSMBADDR_3
I
D29
SSMBADDR_5
I
D28
SSMBCLK
I/O
F26
SSMBDAT
I/O
G25
SWMODE_0
I
AJ4
SWMODE_1
I
AK4
SWMODE_2
I
AJ5
SWMODE_3
I
AH5
System
VDDCORE,
VDDAPE, VDDIO,
VDDPE, VTTPE
See Table 20 for a listing of power pins.
VSS
See Table 21 for a listing of ground pins.
Table 22 89PES32H8 Alphabetical Signal List (Part 6 of 6)
35 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
PES32H8 Pinout — Top View
1
2
3
4
5
6
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
7 8
A
A
B
B
C
C
D
D
E
E
F
F
G
H
X
X X
X X
G
H
X
J
J
K
K
L
L
X
X
M
M
N
N
P
P
R
T
R
X X
X X
X X
X X
T
U
U
V
V
W
W
Y
Y
X
X
AA
AA
AB
AB
AC
X
AD
X X
X X
AC
X
AD
AE
AE
AF
AF
AG
AG
AH
AH
AJ
AJ
AK
AK
1
2
3
4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VDDCore (Power)
VDDPE (Power)
VDDI/O (Power)
VDDAPE (Power)
X VTTPE (Power)
36 of 40
Vss (Ground)
Signals
July 19, 2007
IDT 89HPES32H8 Data Sheet
PES32H8 Package Drawing — 900-Pin AL900/AR900
37 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
PES32H8 Package Drawing — Page Two
38 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Revision History
July 19, 2007: Initial publication of data sheet.
39 of 40
July 19, 2007
IDT 89HPES32H8 Data Sheet
Ordering Information
NN
A
AAA
NNAN
AA
Product
Family
Operating
Voltage
Device
Family
Product
Detail
Device
Revision
AA
Legend
A = Alpha Character
N = Numeric Character
A
Package Temp Range
Blank
Commercial Temperature
(0°C to +70°C Ambient)
I
Industrial Temperature
(-40° C to +85° C Ambient)
AL
900-ball FCBGA
AR
900-ball FCBGA, RoHS
ZA
ZA revision
32H8
32-lane, 8-port
PES
PCI Express Switch
H
1.0V +/- 0.1V Core Voltage
89
Serial Switching Product
Valid Combinations
89HPES32H8ZAAL
900-ball FCBGA package, Commercial Temperature
89HPES32H8ZAAR
900-ball RoHS FCBGA package, Commercial Temperature
89HPES32H8ZAALI
900-ball FCBGA package, Industrial Temperature
89HPES32H8ZAARI
900-ball RoHS FCBGA package, Industrial Temperature
®
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
40 of 40
for Tech Support:
email: [email protected]
phone: 408-284-8208
July 19, 2007