ISL6536 ® Data Sheet December 28, 2004 FN9114.2 Four Channel Supervisory IC Features The ISL6536 is a four channel supervisory IC designed to monitor voltages >, = 0.7V. This IC bias range is from 2.7V to 4V but can supervise any positive voltage using an external resistor divider to translate to a lower voltage for comparison to the internal 0.63V reference. • Adjustable undervoltage lockout for each supply Once properly biased and enabled when all four voltage monitor (VMON) inputs are satisfied the PGOOD output will be immediately released to go high to signal that voltage is valid on all four rails. Subsequently when the monitored voltage on any rail drops below its user defined threshold point, the PGOOD output is pulled low. Each rail’s VMON point is independently adjustable with a resistor divider. The PGOOD output is guaranteed to be valid with IC bias lower than 1V. The VMON inputs will ignore 30µs transients on the monitored supplies. The PGOOD output is an open-drain to allow ORing of multiple signals and interfacing to a range of logic levels. The ENABLE input provides for a reset of the PGOOD output when it is pulled down below 0.5V. With an internal 10uA pull-up to VDD it can be signalled with common logic or pulled to ground with a push button switch. • Pb-Free Available (RoHS Compliant) • Active high PGOOD Output • Guaranteed PGOOD Valid to Falling VDD < 1V • VMON Glitch Immunity Applications • Graphics Cards • Multi voltage DSPs and Processors • µP Voltage Monitoring • Embedded Control Systems • Intelligent Instruments • Medical Equipment • Network Routers • Portable Battery-Powered Equipment • Set-Top Boxes ISL6536 *OPT V1 in V2 in • Telecommunications Systems V3 in V4 in Typical Application Schematic Ordering Information PART NUMBER TEMP. RANGE (°C) PACKAGE PKG. DWG. # 1 VDD VMON1 8 ISL6536IB -40 to +85 8 LD SOIC M8.15 2 PGD VMON2 7 ISL6536IBZ (See Note) -40 to +85 8 LD SOIC (Pb-free) M8.15 3 EN VMON3 6 4 GND VMON4 5 ISL6536IB-T 8 LD SOIC Tape and Reel ISL6536IBZ-T (See Note) 8 LD SOIC (Pb-free) NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL6536 Pin Descriptions ISL6536 PIN NAME FUNCTION DESCRIPTION 1 VDD 2 PGOOD PGOOD is the boolean AND function of all the UV inputs being satisfied. This is an open drain output and can be pulled high to the appropriate level with an external resistor. Additionally a 20kΩ pull up to VDD is provided internally. 3 ENABLE Enabling input for supervisory function. Has a 10µA pull-up to VDD 4 GND 5-8 VMON1 VMON2 VMON3 VMON4 Bias IC from nominal 2.7V to 4V IC ground These inputs provide for a programmable monitored voltage threshold referenced to an internal 0.63V reference. These inputs have a 30µs glitch filter to prevent transient upsets from being recognized by PGOOD. VDD EN 10µA VMON1 20K VMON2 FALLING EDGE GLITCH FILTER PGOOD VMON3 VMON4 + ISL6536 633mV - 2 FN9114.2 December 28, 2004 ISL6536 Absolute Maximum Ratings Thermal Information VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V VMON, PGOOD, ENABLE. . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (HBM) Thermal Resistance (Typical, Note 1) θJA (°C/W) 8 LD SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C Operating Conditions VDD Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . +2.7V to +4V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details. 2. 2. All voltages are relative to GND, unless otherwise specified. Electrical Specifications Nominal VDD = 3.3V, TA = TJ = -40°C - 85°C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VMON > VMON_L2H 165 1000 µA BIAS IC Supply Current IVDD VDD Power On VDD_L2H VDD low to high 2.6 V VDD Power On Reset VDD_POR VDD high to low 2.4 V Pull-Down Current PGpd VPGOOD = 0.5V 2 mA Pull-Up Resistance PGpu 20 kΩ Output Low VPGl PGOOD Delay from VMON Rising TPGdelVMON VDD= 1V 0.05 Last valid input = Vth to PG release 0.1 V 2 µs Delay from EN Rising TPGdelENR EN high to PG release 0.05 µs Delay from EN Falling TPGdelENF EN low to PG pulling low 0.015 µs ENABLE Rising Threshold VEN Threshold Hysteresis ENABLE Low to High Threshold 0.4VDD VEN_HYS Pull-up Current IENpu VEN = 0.5V 0.5VDD 0.6VDD V 0.065 V 10 µA VMON Input Falling Threshold 3.3VMON_H2L Falling Threshold Temp Coeff. 3.3VMON_TC Hysteresis VVMON_HYS - 10 - mV Range VMON_RNG - 8 - mV - 30 - µs Glitch Filter Duration TFIL 3 Tj=+25c 0.623 0.633 0.643 100 VMON glitch to PGOOD low Filter V uV/°C FN9114.2 December 28, 2004 ISL6536 ISL6536 Description and Operation The ISL6536 is a four channel supervisory IC designed to monitor multiple voltages greater than 0.7V. This IC is suitable for both microprocessors or industrial system applications. Upon VDD bias power up the PGOOD output is held low with VDD as low as 0V. Once biased to 2.6V and enabled the IC continuously monitors from one to four voltages independently through external resistor dividers comparing each VMON pin voltage to an internal 0.63V reference. Once all VMON input voltages rise above 0.63V the PGOOD (power good) output signal is released and is pulled high via an external pull resistor to indicate that the power conditions have been met. The PGOOD output is an open-drain to allow ORing of the signals and interfacing to a wide range of logic levels. Once any VMON input falls below 0.63V the PGOOD output is pulled low, the VMON inputs are designed to reject fast transients (30µs). If less than four voltages are being monitored, connect the unused VMON pins to VDD. The PGOOD pin has an internal 20kΩ pull-up to VDD making an external pull-up resistor unnecessary. Figure 1 illustrates the operational timing diagram. 4/5 EN/VMON INPUTS HIGH VTH LAST EN/VMON INPUT TFIL <TFIL PGOOD OUTPUT FIGURE 1. ISL6536 OPERATIONAL TIMING DIAGRAM Typical Performance Curves 0.645 0.5 0.642 VMON<VMON_L2H 0.639 0.4 0.3 0.2 0.1 VMON>VMON_L2H 0 2.6 VMON THRESHOLD (V) VDD BIAS CURRENT (mA) 0.6 0.636 0.633 0.630 0.627 3.0 3.33 3.66 VDD BIAS VOLTAGE (V) FIGURE 2. VDD CURRENT vs. VDD VOLTAGE 4 4.0 2.6 3.3 3.5 3.7 3.9 VDD BIAS VOLTAGE (V) FIGURE 3. VMON THRESHOLD vs. VDD VOLTAGE FN9114.2 December 28, 2004 ISL6536 Typical Performance Curves (Continued) VMON PGOOD PGOOD EN PG = 1V/DIV EN = 1V/DIV 1µs/DIV PG = 2V/DIV VMON = 1V/DIV 1µs/DIV FIGURE 5. VMON HIGH to PGOOD FIGURE 4. EN HIGH to PGOOD VMON PGOOD PGOOD EN EN = 1V/DIV PG = 1V/DIV 10nS/DIV PGOOD = 2V/DIV VMON = 1V/DIV 10µs/DIV FIGURE 7. VMON LOW to PGOOD FIGURE 6. EN LOW to PGOOD VMON PGOOD PGOOD EN EN = 1V/DIV PG = 1V/DIV 10nS/DIV FIGURE 8. EN LOW to PGOOD 5 PGOOD = 2V/DIV VMON = 1V/DIV 10µs/DIV FIGURE 9. VMON LOW to PGOOD FN9114.2 December 28, 2004 ISL6536 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N INDEX AREA 0.25(0.010) M H 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- µα e A1 B 0.25(0.010) M C C A M B S 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MILLIMETERS MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N NOTES: MAX A1 e 0.10(0.004) MIN α 8 0o 8 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6 FN9114.2 December 28, 2004