INA3 INA3 26 INA326 INA327 27 SBOS222D – NOVEMBER 2001 – REVISED NOVEMBER 2004 Precision, Rail-to-Rail I/O INSTRUMENTATION AMPLIFIER FEATURES DESCRIPTION ● PRECISION LOW OFFSET: 100µV (max) LOW OFFSET DRIFT: 0.4µV/°C (max) EXCELLENT LONG-TERM STABILITY VERY-LOW 1/f NOISE The INA326 and INA327 (with shutdown) are high-performance, low-cost, precision instrumentation amplifiers with rail-to-rail input and output. They are true single-supply instrumentation amplifiers with very low DC errors and input common-mode ranges that extends beyond the positive and negative rails. These features make them suitable for applications ranging from general-purpose to high-accuracy. ● TRUE RAIL-TO-RAIL I/O INPUT COMMON-MODE RANGE: 20mV Below Negative Rail to 100mV Above Positive Rail WIDE OUTPUT SWING: Within 10mV of Rails SUPPLY RANGE: Single +2.7V to +5.5V ● SMALL SIZE microPACKAGE: MSOP-8, MSOP-10 ● LOW COST APPLICATIONS ● LOW-LEVEL TRANSDUCER AMPLIFIER FOR BRIDGES, LOAD CELLS, THERMOCOUPLES ● WIDE DYNAMIC RANGE SENSOR MEASUREMENTS ● HIGH-RESOLUTION TEST SYSTEMS ● WEIGH SCALES ● MULTI-CHANNEL DATA ACQUISITION SYSTEMS ● MEDICAL INSTRUMENTATION ● GENERAL-PURPOSE Excellent long-term stability and very low 1/f noise assure low offset voltage and drift throughout the life of the product. The INA326 (without shutdown) comes in the MSOP-8 package. The INA327 (with shutdown) is offered in an MSOP-10. Both are specified over the industrial temperature range, –40°C to +85°C, with operation from –40°C to +125°C. INA326 AND INA327 RELATED PRODUCTS PRODUCT INA337 INA114 INA118 INA122 INA128 INA321 FEATURES Precision, 0.4µV/°C Drift, Specified –40°C to +125°C 50µV VOS, 0.5nA IB, 115dB CMR, 3mA IQ, 0.25µV/°C Drift 50µV VOS, 1nA IB, 120dB CMR, 385µA IQ, 0.5µV/°C Drift 250µV VOS, –10nA IB, 85µA IQ, Rail-to-Rail Output, 3µV/°C Drift 50µV VOS, 2nA IB, 125dB CMR, 750µA IQ, 0.5µV/°C Drift 500µV VOS, 0.5pA IB, 94dB CMRR, 60µA IQ, Rail-to-Rail Output V+ 2 1 VIN− R1 VIN+ V− 7 4 6 INA326 8 3 5 R2 VO G = 2(R2/R1) C2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2001-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY MSOP-8 DGK –40°C to +85°C B26 " " " " INA326EA/250 INA326EA/2K5 Tape and Reel, 250 Tape and Reel, 2500 MSOP-10 DGS –40°C to +85°C B27 " " " " INA327EA/250 INA327EA/2K5 Tape and Reel, 250 Tape and Reel, 2500 INA326 " INA327 " NOTE: (1) For the most current package and ordering information, download the latest version of this data sheet and see the Package Option Addendum located at the end of the data sheet. ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage .................................................................................. +5.5V Signal Input Terminals: Voltage(2) .............................. –0.5V to (V+) + 0.5V Current(2) ................................................... ±10mA Output Short-Circuit ................................................................. Continuous Operating Temperature Range ....................................... –40°C to +125°C Storage Temperature Range .......................................... –65°C to +150°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 10s) ............................................... +300°C NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Input terminals are diode clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited to 10mA or less. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PIN CONFIGURATION Top View INA326 INA327 R1 1 8 R1 R1 1 10 R1 VIN− 2 7 V+ VIN− 2 9 V+ VIN+ 3 6 VO VIN+ 3 8 VO V− 4 5 R2 V− 4 7 R2 (Connect to V+) 5 6 Enable MSOP- 8 MSOP- 10 2 INA326, INA327 www.ti.com SBOS222D ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V BOLDFACE limits apply over the specified temperature range, TA = –40°C to +85°C At TA = +25°C, RL = 10kΩ, G = 100 (R1 = 2kΩ, R2 = 100kΩ), external gain set resistors, and IACOMMON = VS /2, with external equivalent filter corner of 1kHz, unless otherwise noted. INA326EA, INA327EA PARAMETER CONDITION INPUT Offset Voltage, RTI VOS VS = +5V, VCM = VS /2 Over Temperature vs Temperature dVOS/dT vs Power Supply PSR VS = +2.7V to +5.5V, VCM = VS /2 Long-Term Stability Input Impedance, Differential Common-Mode Input Voltage Range Safe Input Voltage Common-Mode Rejection CMR VS = +5V, VCM = (V–) – 0.02V to (V+) + 0.1V Over Temperature INPUT BIAS CURRENT Bias Current vs Temperature Offset Current IB VCM = VS /2 VS = +5V IOS VS = +5V NOISE Voltage Noise, RTI f = 10Hz f = 100Hz f = 1kHz f = 0.01Hz to 10Hz Voltage Noise, RTI f = 10Hz f = 100Hz f = 1kHz f = 0.01Hz to 10Hz Current Noise, RTI f = 1kHz f = 0.01Hz to 10Hz Output Ripple, VO Filtered(2) ±20 ±100 (V+) + 0.1 (V+) + 0.5 Ω || pF Ω || pF V V dB dB ±3 See Note (1) 1010 || 2 1010 || 14 (V–) – 0.02 (V–) – 0.5 100 94 µV µV µV/°C ±0.1 ±20 UNITS ±124 ±0.4 114 ±0.2 See Typical Characteristics ±0.2 µV/V ±2 nA ±2 nA 33 33 33 0.8 nV/ √Hz nV/ √Hz nV/ √Hz µVp-p 120 97 97 4 nV/ √Hz nV/ √Hz nV/ √Hz µVp-p 0.15 4.2 See Applications Information pA/ √Hz pAp-p G = 2(R2/R1) < 0.1 ±0.08 ±6 ±0.004 G = 10, 100, VS = +5V, VO = 0.075V to 4.925V G = 10, 100, VS = +5V, VO = 0.075V to 4.925V G = 10, 100, VS = +5V, VO = 0.075V to 4.925V RL = 100kΩ RL = 10kΩ, VS = +5V ISC INTERNAL OSCILLATOR Frequency of Auto-Correction Accuracy BW G = 1 to 1k SR VS = +5V, All Gains, CL = 100pF tS 1kHz Filter, G = 1 to 1k, VO = 2V step, CL = 100pF 10kHz Filter, G = 1 to 1k, VO = 2V step, CL = 100pF 1kHz Filter, 50% Output Overload, G = 1 to 1k 10kHz Filter, 50% Output Overload, G = 1 to 1k INA326, INA327 SBOS222D MAX RS = 0Ω, G = 10, R1 = 20kΩ, R2 = 100kΩ OUTPUT Voltage Output Swing from Rail FREQUENCY RESPONSE Bandwidth(4), –3dB Slew Rate(4) Settling Time(4), 0.1% 0.01% 0.1% 0.01% Overload Recovery(4) TYP RS = 0Ω, G = 100, R1 = 2kΩ, R2 = 100kΩ GAIN Gain Equation Range of Gain Gain Error(3) vs Temperature Nonlinearity Over Temperature Capacitive Load Drive Short-Circuit Current MIN www.ti.com 75 75 5 10 > 10000 ±0.2 ±25 ±0.01 V/V % ppm/°C % of FS 500 ±25 mV mV mV pF mA 90 ±20 kHz % 1 Filter Limited 0.95 1.3 130 160 30 5 kHz ms ms µs µs µs µs 3 ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V (Cont.) BOLDFACE limits apply over the specified temperature range, TA = –40°C to +85°C At TA = +25°C, RL = 10kΩ, G = 100 (R1 = 2kΩ, R2 = 100kΩ), external gain set resistors, and IACOMMON = VS /2, with external equivalent filter corner of 1kHz, unless otherwise noted. INA326EA, INA327EA PARAMETER POWER SUPPLY Specified Voltage Range Quiescent Current Over Temperature CONDITION TYP MAX UNITS 2.4 +5.5 3.4 3.7 V mA mA 0.25 V V µs µs µA +2.7 IQ SHUTDOWN Disable (Logic Low Threshold) Enable (Logic High Threshold) Enable Time(5) Disable Time Shutdown Current and Enable Pin Current TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance MIN IO = 0, Diff VIN = 0V, VS = +5V 1.6 75 100 2 VS = +5V, Disabled –40 –40 –65 θJA MSOP-8, MSOP-10 Surface-Mount 5 +85 +125 +150 150 °C °C °C °C/W NOTES: (1) 1000-hour life test at 150°C demonstrated randomly distributed variation in the range of measurement limits—approximately 10µV. (2) See Applications Information section, and Figures 1 and 3. (3) Does not include error and TCR of external gain-setting resistors. (4) Dynamic response is limited by filtering. Higher bandwidths can be achieved by adjusting the filter. (5) See Typical Characteristics, “Input Offset Voltage vs Warm-Up Time”. 4 INA326, INA327 www.ti.com SBOS222D TYPICAL CHARACTERISTICS At TA = 25°C, VS = +5V, Gain = 100, and RL = 10kΩ with external equivalent filter corner of 1kHz, unless otherwise noted. GAIN vs FREQUENCY 1kHz FILTER GAIN vs FREQUENCY 10kHz FILTER 80 80 60 60 G = 1k G = 1k 40 Gain (dB) Gain (dB) 40 G = 100 20 G = 10 0 G = 100 20 G = 10 0 G=1 G=1 −20 −20 −40 −40 10 100 1k 10k Frequency (Hz) 100k 1M 10 COMMON- MODE REJECTION vs FREQUENCY 1kHz FILTER 100 1k 10k Frequency (Hz) 100k 1M COMMON- MODE REJECTION vs FREQUENCY 10kHz FILTER 160 160 G = 1k 140 140 G = 100 120 CMR (dB) 100 G = 10 80 G=1 G = 1k 100 80 G = 100 60 60 40 40 G=1 20 20 10 100 1k 10k Frequency (Hz) 100k 1M 10 POWER- SUPPLY REJECTION vs FREQUENCY Input-Referred Voltage Noise (nV/√Hz) G = 100, 1k 100 G = 10 80 G=1 60 40 Filter Frequency 10kHz 1kHz 20 100 1k 10k Frequency (Hz) 100k 1M INPUT- REFERRED VOLTAGE NOISE AND INPUT BIAS CURRENT NOISE vs FREQUENCY 10kHz FILTER 120 PSR (dB) G = 10 0 10k 1 Current Noise (all gains) 1k 0.1 G=1 G = 10 100 0.01 G = 100 G = 1000 10 10 100 1k Frequency (Hz) 10k 100k INA326, INA327 SBOS222D www.ti.com Input Bias Current Noise (pA/√Hz) CMR (dB) 120 0.001 1 10 100 Frequency (Hz) 1k 10k 5 TYPICAL CHARACTERISTICS (Cont.) At TA = 25°C, VS = +5V, Gain = 100, and RL = 10kΩ with external equivalent filter corner of 1kHz, unless otherwise noted. INPUT OFFSET VOLTAGE vs TURN- ON TIME 1kHz FILTER, G = 100 INPUT OFFSET VOLTAGE vs WARM- UP TIME 10kHz FILTER, G = 100 Input Offset Voltage (20µV/div) Input Offset Voltage (20µV/div) Filter Settling Time Device Turn- On Time (75µs) 0 1 Turn- On Time (ms) 2 Device Turn- On Time Filter Settling Time 0 SMALL- SIGNAL RESPONSE G = 1, 10, AND 100 0.1 0.2 0.3 Warm- Up Time (ms) 0.4 SMALL- SIGNAL STEP RESPONSE G = 1000 50mV/div 1kHz Filter 50mV/div 1kHz Filter 10kHz Filter 500µs/div 500µs/div LARGE- SIGNAL RESPONSE G = 1 TO 1000 0.01Hz TO 10Hz VOLTAGE NOISE 2V/div 200nV/div 1kHz Filter 10kHz Filter 10s/div 500µs/div 6 INA326, INA327 www.ti.com SBOS222D TYPICAL CHARACTERISTICS (Cont.) At TA = 25°C, VS = +5V, Gain = 100, and RL = 10kΩ with external equivalent filter corner of 1kHz, unless otherwise noted. OFFSET VOLTAGE PRODUCTION DISTRIBUTION G=1 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 −10,000 −9000 −8000 −7000 −6000 −5000 −4000 −3000 −2000 −1000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 Population Population OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION G=1 Offset Voltage Drift (µV/°C) Offset Voltage (µV) OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION G = 10 −1000 −900 −800 −700 −600 −500 −400 −300 −200 −100 0 100 200 300 400 500 600 700 800 900 1000 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 Population Population OFFSET VOLTAGE PRODUCTION DISTRIBUTION G = 10 Offset Voltage Drift (µV/°C) Offset Voltage (µV) OFFSET VOLTAGE PRODUCTION DISTRIBUTION G = 100, 1000 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 0.32 0.34 0.36 0.38 0.40 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 Population Population OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION G = 100, 1000 Offset Voltage Drift (µV/°C) Offset Voltage (µV) INA326, INA327 SBOS222D www.ti.com 7 TYPICAL CHARACTERISTICS (Cont.) At TA = 25°C, VS = +5V, Gain = 100, and RL = 10kΩ with external equivalent filter corner of 1kHz, unless otherwise noted. GAIN ERROR PRODUCTION DISTRIBUTION G = 100 −100 100.000 −110 31.600 −120 1.000 −130 0.316 −140 0.100 −150 0.030 −160 0.010 −170 0.003 −200 −180 −160 −140 −120 −100 −80 −60 −40 −20 0 20 40 60 80 100 120 140 160 180 200 −180 0 200k 400k 600k Frequency (Hz) Gain Error (m%) QUIESCENT CURRENT vs TEMPERATURE 2.0 VS = +5V 1.5 2.5 1.0 IB− 0.5 VS = +2.7V IB (nA) IQ (mA) 2.0 1.5 0 −0.5 1.0 −1.0 0.5 8 0.001 1M INPUT BIAS CURRENT vs TEMPERATURE 3.0 0 −50 800k IB+ −1.5 −25 0 25 50 Temperature (°C) 75 100 125 −2.0 −50 −25 0 25 50 Temperature (°C) 75 100 125 INA326, INA327 www.ti.com SBOS222D VOUT (µVrms) Population VOUT (dBV) INPUT- REFERRED RIPPLE SPECTRUM G = 100 APPLICATIONS INFORMATION SETTING THE GAIN The INA326 is a 2-stage amplifier with each stage gain set by R1 and R2, respectively (see Figure 5, “Inside the INA326”, for details). Overall gain is described by the equation: Figure 1 shows the basic connections required for operation of the INA326. A 0.1µF capacitor, placed close to and across the power-supply pins is strongly recommended for highest accuracy. RoCo is an output filter that minimizes auto-correction circuitry noise. This output filter may also serve as an antialiasing filter ahead of an Analog-to-Digital (A/D) converter. It is also optional based on desired precision. G=2 Resistor values for commonly used gains are shown in Figure 1. Gain-set resistor values for best performance are different for +5V single-supply and for ±2.5V dual-supply operation. Optimum value for R1 can be calculated by: The INA326 uses a unique internal topology to achieve excellent Common-Mode Rejection (CMR). Unlike conventional instrumentation amplifiers, CMR is not affected by resistance in the reference connections or sockets. See “Inside the INA326” for further detail. To achieve best high-frequency CMR, minimize capacitance on pins 1 and 8. R1 (Ω) 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000 2000 5000 10000 400k 400k 400k 200k 100k 40k 20k 10k 4k 2k 2k 2k 2k 2k 2k 2k DESIRED GAIN R1 (Ω) 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000 2000 5000 10000 400k 400k 400k 400k 200k 80k 40k 20k 8k 4k 2k 2k 2k 2k 2k 2k R1 = VIN, MAX/12.5µA 5 2.5 1 1 1 1 1 1 1 1 0.5 0.2 0.1 0.05 0.02 0.01 −2.5V +2.5V 0.1µF 5 2.5 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.2 0.1 0.05 0.02 0.01 7 2 VIN− 1 R1 4 6 INA326 RO VO 100Ω VO Filtered CO(1) 1µF 8 5 3 VIN+ G = 2(R2/R1) fO = 1kHz C2(1) R2 IACOMMON(2) (1) C2 and CO combine to form a 2-pole response that is −3dB at 1kHz. Each individual pole is at 1.5kHz. (2) Output voltage is referenced to IACOMMON (see text). Single-supply operation may require R2 > 100kΩ for full output swing. This may produce higher input referred offset voltage. See Offset Voltage, Drift, and Circuit Values for detail. V+ R2 || C2 (Ω || nF) 20k || 40k || 100k || 200k || 200k || 200k || 200k || 200k || 200k || 200k || 200k || 500k || 1M || 2M || 5M || 10M || (2) where R1 must be no less than 2kΩ. R2 || C2 (Ω || nF) 20k || 40k || 100k || 100k || 100k || 100k || 100k || 100k || 100k || 100k || 200k || 500k || 1M || 2M || 5M || 10M || (1) The stability and temperature drift of the external gain-setting resistors will affect gain by an amount that can be directly inferred from the gain equation (1). The output reference terminal is taken at the low side of R2 (IACOMMON). DESIRED GAIN R2 R1 0.1µF VIN− 2 7 1 R1 4 6 INA326 RO VO 100Ω VIN+ 5 3 VO Filtered CO(1) 1µF 8 R2 G = 2(R2/R1) fO = 1kHz (3) C2(1) IACOMMON(2) (1) C2 and CO combine to form a 2-pole response that is −3dB at 1kHz. Each individual pole is at 1.5kHz. (2) Output voltage is referenced to IACOMMON (see text). (3) Output offset voltage required for measurement near zero (see Figure 28). NOTES: (1) C2 and CO combine to form a 2-pole response that is –3dB at 1kHz. Each individual pole is at 1.5kHz. (2) Output voltage is referenced to IACOMMON (see text). (3) Output offset voltage required for measurement near zero (see Figure 6). FIGURE 1. Basic Connections. NOTE: Connections for INA327 differ—see Pin Configuration for detail. INA326, INA327 SBOS222D www.ti.com 9 Following this design procedure for R1 produces the maximum possible input stage gain for best accuracy and lowest noise. Circuit layout and supply bypassing can affect performance. Minimize the stray capacitance on pins 1 and 8. Use recommended supply bypassing, including a capacitor directly from pin 7 to pin 4 (V+ to V–), even with dual (split) power supplies (see Figure 1). The enable time following shutdown is 75µs plus the settling time due to filters (see Typical Characteristics, “Input Offset Voltage vs Warm-up Time”). Disable time is 100µs. This allows the INA327 to be operated as a “gated” amplifier, or to have its output multiplexed onto a common output bus. When disabled, the output assumes a high-impedance state. INA327 PIN 5 OFFSET VOLTAGE, DRIFT, AND CIRCUIT VALUES As with other multi-stage instrumentation amplifiers, inputreferred offset voltage depends on gain and circuit values. The specified offset and drift performance is rated at R1 = 2kΩ, R2 = 100kΩ, and VS = ±2.5V. Offset voltage and drift for other circuit values can be estimated from the following equations: VOS = 10µV + (50nA)(R2)/G (3) dVOS/dT = 0.12µV/°C + (0.16nA/°C)(R2)/G (4) These equations might imply that offset and drift can be minimized by making the value of R2 much lower than the values indicated in Figure 1. These values, however, have been chosen to assure that the output current into R2 is kept less than or equal to ±25µA, while maintaining R1’s value greater than or equal to 2kΩ. Some applications with limited output voltage swing or low power-supply voltage may allow lower values for R2, thus providing lower input-referred offset voltage and offset voltage drift. Conversely, single-supply operation with R2 grounded requires that R2 values be made larger to assure that current remains under 25µA. This will increase the input-referred offset voltage and offset voltage drift. Pin 5 of the INA327 should be connected to V+ to ensure proper operation. DYNAMIC PERFORMANCE The typical characteristic “Gain vs Frequency” shows that the INA326 has nearly constant bandwidth regardless of gain. This results from the bandwidth limiting from the recommended filters. NOISE PERFORMANCE Internal auto-correction circuitry eliminates virtually all 1/f noise (noise that increases at low frequency) in gains of 100 or greater. Noise performance is affected by gain-setting resistor values. Follow recommendations in the “Setting Gain” section for best performance. Total noise is a combination of input stage noise and output stage noise. When referred to the input, the total mid-band noise is: VN = 33nV / Hz + 800nV / Hz G (5) Circuit conditions that cause more than 25µA to flow in R2 will not cause damage, but may produce more nonlinearity. The output noise has some 1/f components that affect performance in gains less than 10. See typical characteristic “Input-Referred Voltage Noise vs Frequency.” INA327 ENABLE FUNCTION High-frequency noise is created by internal auto-correction circuitry and is highly dependent on the filter characteristics chosen. This may be the dominant source of noise visible when viewing the output on an oscilloscope. Low cutoff frequency filters will provide lowest noise. Figure 3 shows the typical noise performance as a function of cutoff frequency. The INA327 can be enabled by applying a logic HIGH voltage level to the Enable pin. Conversely, a logic LOW voltage level will disable the amplifier, reducing its supply current from 2.4mA to typically 2µA. For battery-operated applications, this feature may be used to greatly reduce the average current and extend battery life. This pin should be connected to a valid high or low voltage or driven, not left open circuit. The Enable pin can be modeled as a CMOS input gate as in Figure 2. V+ 1k Total Output Noise (µVRMS) The INA327 adds an enable/shutdown function to the INA326. Its pinout differs from the INA326—see the Pin Configuration for detail. G = 1000 100 10 G = 100 G = 10 G=1 1 2µA 1 Enable 6 10 100 1k Required Filter Cutoff Frequency (Hz) 10k FIGURE 3. Total Output Noise vs Required Filter Cutoff Frequency. FIGURE 2. Enable Pin Model. 10 INA326, INA327 www.ti.com SBOS222D Applications sensitive to the spectral characteristics of highfrequency noise may require consideration of the spurious frequencies generated by internal clocking circuitry. “Spurs” occur at approximately 90kHz and its harmonics (see typical characteristic “Input-Referred Ripple Spectrum”) which may be reduced by additional filtering below 1kHz. Thermocouple INA326 5 Insufficient filtering at pin 5 can cause nonlinearity with large output voltage swings (very near the supply rails). Noise must be sufficiently filtered at pin 5 so that noise peaks do not “hit the rail” and change the average value of the signal. Figure 3 shows guidelines for filter cutoff frequency. FIGURE 4. Providing Input Bias Current Return Path. HIGH-FREQUENCY NOISE C2 and CO form filters to reduce internally generated autocorrection circuitry noise. Filter frequencies can be chosen to optimize the trade-off between noise and frequency response of the application, as shown in Figure 3. The cutoff frequencies of the filters are generally set to the same frequency. Figure 3 shows the typical output noise for four gains as a function of the –3dB cutoff frequency of each filter response. Small signals may exhibit the addition of internally generated auto-correction circuitry noise at the output. This noise, combined with broadband noise, becomes most evident in higher gains with filters of wider bandwidth. INPUT PROTECTION The inputs of the INA326 are protected with internal diodes connected to the power-supply rails. These diodes will clamp the applied signal to prevent it from damaging the input circuitry. If the input signal voltage can exceed the power supplies by more than 0.5V, the input signal current should be limited to less than 10mA to protect the internal clamp diodes. This can generally be done with a series input resistor. Some signal sources are inherently current-limited and do not require limiting resistors. FILTERING INPUT BIAS CURRENT RETURN PATH The input impedance of the INA326 is extremely high— approximately 1010Ω. However, a path must be provided for the input bias current of both inputs. This input bias current is approximately ±0.2nA. High input impedance means that this input bias current changes very little with varying input voltage. Filtering can be adjusted through selection of R2C2 and ROCO for the desired trade-off of noise and bandwidth. Adjustment of these components will result in more or less ripple due to auto-correction circuitry noise and will also affect broadband noise. Filtering limits slew rate, settling time, and output overload recovery time. Input circuitry must provide a path for this input bias current for proper operation. Figure 4 shows provision for an input bias current path in a thermocouple application. Without a bias current path, the inputs will float to an undefined potential and the output voltage may not be valid. It is generally desirable to keep the resistance of RO relatively low to avoid DC gain error created by the subsequent stage loading. This may result in relatively high values for CO to produce the desired filter response. The impedance of ROCO can be scaled higher to produce smaller capacitor values if the load impedance is very high. INPUT COMMON-MODE RANGE Certain capacitor types greater than 0.1µF may have dielectric absorption effects that can significantly increase settling time in high-accuracy applications (settling to 0.01%). Polypropylene, polystyrene, and polycarbonate types are generally good. Certain “high-K” ceramic types may produce slow settling “tails.” Settling time to 0.1% is not generally affected by high-K ceramic capacitors. Electrolytic types are not recommended for C2 and CO. Common instrumentation amplifiers do not respond linearly with common-mode signals near the power-supply rails, even if “railto-rail” op amps are used. The INA326 uses a unique topology to achieve true rail-to-rail input behavior (see Figure 5, “Inside the INA326”). The linear input voltage range of each input terminal extends to 20mV below the negative rail, and 100mV above the positive rail. INA326, INA327 SBOS222D www.ti.com 11 INSIDE THE INA326 The INA326 uses a new, unique internal circuit topology that provides true rail-to-rail input. Unlike other instrumentation amplifiers, it can linearly process inputs up to 20mV below the negative power-supply rail, and 100mV above the positive power-supply rail. Conventional instrumentation amplifier circuits cannot deliver such performance, even if rail-to-rail op amps are used. A1 and A2’s output stages. A2 combines the current in R1 with a mirrored replica of the current from A1. The resulting current in A2’s output and associated current mirror is two times the current in R1. This current flows in (or out) of pin 5 into R2. The resulting gain equation is: G=2 The ability to reject common-mode signals is derived in most instrumentation amplifiers through a combination of amplifier CMR and accurately matched resistor ratios. The INA326 converts the input voltage to a current. Current-mode signal processing provides rejection of common-mode input voltage and power-supply variation without accurately matched resistors. R2 R1 Amplifiers A1, A2, and their associated mirrors are powered from internal charge-pumps that provide voltage supplies that are beyond the positive and negative supply rails. As a result, the voltage developed on R2 can actually swing 20mV below the negative power-supply rail, and 100mV above the positive supply rail. A3 provides a buffered output of the voltage on R2. A3’s input stage is also operated from the charge-pumped power supplies for true rail-to-rail operation. A simplified diagram shows the basic circuit function. The differential input voltage, (VIN+) – (VIN–) is applied across R1. The signal-generated current through R1 comes from V+ V− 0.1µF 7 4 Current Mirror INA326 IR1 2 VIN− IR1 A1 1 Current Mirror IR1 R1 Current Mirror IR1 8 VIN+ 3 2IR1 2IR1 A2 2IR1 A3 2IR1 Current Mirror 6 VO 2IR1 5 R2 C2 IACOMMON FIGURE 5. Simplified Circuit Diagram. 12 INA326, INA327 www.ti.com SBOS222D APPLICATION CIRCUITS 2 R0 1 R1 6 INA326 VO 5 8 VREF C0 3 R′2 R2 and R′2 are chosen to R2 C2 create a small output offset voltage (e.g., 100mV). Gain is determined by G = 2 (R2 || R′2)/R1 the parallel combination of R2 and R′2. FIGURE 6. Generating Output Offset Voltage. VREF 2 1 INA326 2kΩ RO 100Ω 6 8 5 A/D Converter CO 1µF 3 200kΩ C2 200kΩ G = 2(200kΩ || 200kΩ)/2kΩ = 100 FIGURE 7. Output Referenced to VREF/2. +5V RS must be chosen so that the input voltage does not exceed 100mV beyond the rail. RS IL 2kΩ 2 7 1 R1 6 INA326 8 RO 100Ω 5 CO 1µF 3 NOTE: Connection point of V+ will include ( ) or exclude ( ) quiescent current in the measurement as desired. Output offset required for measurements near zero (see Figure 6). R2 RL VO C2 VO = 2(IL × RS) R2 R1 FIGURE 8. High-Side Current Shunt Measurement. INA326, INA327 SBOS222D www.ti.com 13 +5V 2 7 1 R1 6 INA326 R2 2kΩ IL VO = 2(IL × RS) VO 5 8 3 RO 100Ω CO 1µF C2 R2 R1 RL RS must be chosen so that the input voltage does not exceed 20mV beyond the rail. RS NOTE: Connection point of V− will include ( ) or exclude ( ) quiescent current in the measurement as desired. Output offset required for measurements near zero (see Figure 6). FIGURE 9. Low-Side Current Shunt Measurement. 1nF RF = 100kΩ NOTE: 0.2% accuracy. Current shunt monitor circuit can be designed for −250V supply with appropriate selection of high- voltage FET. +5V 2 3 7 OPA336PA ZVN4525G (zetex) 2 IL + RS VS = 0mV to 50mV max − VCC 8 INA326 GND 4 3 RF RI RPULL- DOWN 200kΩ 8.45kΩ (High- Voltage n- Channel 7 FET) 1 RI = 2kΩ VO = 2(IL × RS) 4 RSTART 100kΩ RL 6 6 ZMM5231BDICT 5.1V 0.1µF 5 −48V FIGURE 10. Low-Side –48V Current Shunt Monitor. +48V + 7 3 VSHUNT = 0mV to 50mV RSHUNT − RI 2kΩ VCC 8 6 INA326 1 GND 2 4 Load 5 ZMM5231BDICT 5.1V 0.1µF ZVP4525 (zetex) (High- Voltage p- Channel FET) 2 75kΩ 8.45kΩ +5V 3 7 OPA336PA 1nF 6 VO = 0.1V to 4.9V 4 49.9kΩ 165kΩ FIGURE 11. High-Side +48V Current Shunt Monitor. 14 INA326, INA327 www.ti.com SBOS222D 2 + 1 VIN 2kΩ 6 INA326 8 − VO = VIN (100) + VDAC 5 +5V 3 1nF 100kΩ 2 DAC VDAC = 0.075V to 4.925V 7 +15V 1 R1 VD 6 INA326 FIGURE 12. Output Offset Adjustment. NC(1) 5 8 2 4 3 3 OPA277 6 VO 4 (2) VCM 7 −15V +1.8V to +5V R2 C2 +5V Logic 2 9 1 R1 INA327 7 10 3 NOTES: (1) NC denotes No Connection. (2) Typical swing capability −20mV to (+5V + 100mV). 6 Enable 8 4 1nF R2(1) FIGURE 14. Output from Pin 5 to Allow Swing Beyond the Rail. +5V 2 9 1 R3 INA327 6 Enable 8 3 VO 7 10 4 0V < VDAC < +5V 1nF R4 DAC R1 200kΩ +5V VREF = +2.5V 2 9 1 R5 INA327 2 IOUT = 7 1 3 R1 ± 50nA 6 INA326 8 ((+VREF) − (VDAC)) 5 4 CF RF = 10k 6 Enable 8 NOTE: Output resistance is typically 800MΩ. Resolution < 5nA. Recommended values of CF = 1nF to 1µF. 7 10 3 +5V (1) 4 1nF R6(1) NOTE: (1) R2, R4, and R6 could be a single, shared resistor to save board space. FIGURE 13. Multiplexed Output. FIGURE 15. Programmable ±25µA Current Source with High Output Resistance. INA326, INA327 SBOS222D www.ti.com 15 VREF = +2.5V +2.5V 2 DAC 7 1 6 INA326 RI = 200kΩ 5 8 4 3 10kΩ −2.5V IOUT = 2 VREF − VDAC 200kΩ 49.9Ω IO 1+ 10kΩ 49.9Ω RL 0.1µF IO = ±5mA with 0.1µA stability. FIGURE 16. Programmable ±5mA Current Source. RI = 1kΩ RF = 100kΩ VI +30V 20kΩ 2 3 +5V 7 OPA551 4 2 IB 2kΩ 6 INA326 5 8 3 −30V 7 1 4 10nF 20kΩ 6 VO = –27V VOS = –100µV at 200mA G=− RF RI = −100V/V Offset of the high- voltage op amp is controlled by the INA326. Internal charge pump in the INA326 allows 1MΩ this node to swing 20mV below ground without a negative supply. NOTES: (1) The OPA551 is a 60V op amp. (2) The INA326 does not require a negative supply to correct for negative VOS values from the high-voltage op amp. (3) Voltage offset contribution of IB (OPA551) is 100pA • 2kΩ = 0.2µV. FIGURE 17. ±27V Output at 200mA Amplifier with 100µV Offset. 16 INA326, INA327 www.ti.com SBOS222D FIGURE 18. Single-Supply PID Temperature Control Loop. INA326, INA327 SBOS222D www.ti.com 17 R6 9.53kΩ R7 1kΩ POT R11 14.3kΩ IN− R9 2kΩ IN+ C6 10µF 2 1 8 3 VS 4 8 VBIAS R8 100kΩ 5 C2 470nF INA326 7 4 V+ V− 0.1µF REF1004- 2.5 D1 R10 1kΩ Bias Generator Gain = 100V/V Set Temp RTHERM 10k‰ R12 15kΩ + R13 20Ω Error Amplifier VO R4 20kΩ R5 20kΩ C5 1nF 6 VBIAS VS C1 1nF V− V+ 1/2 OPA2340 R14 10kΩ VS R15 200Ω C7 22nF R16 Loop Gain 2kΩ Adjust POT Common +5V Input VBIAS 1/4 OPA4340 R18 10kΩ + R20 5k‰ POT C4 10 F VS R2 100kΩ VBIAS VBIAS RINT 10MΩ R19 100kΩ CDIFF 1µF VBIAS R17 5kΩ POT 1/4 OPA4340 RDIFF 1MΩ Differentiator TC: 100ms to 1s 1/4 OPA4340 Proportional R1 100kΩ V− V+ 1/4 OPA4340 VS C3 1nF CINT 1µF Integrator TC: 1s to 10s R22 10kΩ R21 10kΩ R23 10kΩ VBIAS 1/2 OPA2340 R25 10kΩ C8 0.1µF Summing Amplifier Common Output to TEC Driver PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty INA326EA/250 ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR INA326EA/250G4 ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR INA326EA/2K5 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR INA326EA/2K5G4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR INA327EA/250 ACTIVE MSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR INA327EA/250G4 ACTIVE MSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR INA327EA/2K5 ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR INA327EA/2K5G4 ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant INA326EA/250 DGK 8 SITE 41 180 12 5.3 3.4 1.4 8 12 Q1 INA326EA/2K5 DGK 8 SITE 41 330 12 5.3 3.4 1.4 8 12 Q1 INA327EA/250 DGS 10 SITE 67 177 12 5.3 3.4 1.4 8 12 Q1 INA327EA/2K5 DGS 10 SITE 67 330 12 5.3 3.4 1.4 8 12 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) INA326EA/250 DGK 8 SITE 41 184.0 184.0 50.0 INA326EA/2K5 DGK 8 SITE 41 346.0 346.0 29.0 INA327EA/250 DGS 10 SITE 67 187.0 187.0 25.6 INA327EA/2K5 DGS 10 SITE 67 375.0 340.0 57.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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