TI TPS51117PW

TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER
FEATURES
•
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•
•
•
•
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•
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DESCRIPTION
High Efficiency, Low Power Consumption,
4.5-µA Typical Shutdown Current
Fixed Frequency Emulated On-Time Control,
Adjustable from 100 kHz to 550 kHz
Fast Transient Response
< 1% Initial Reference Accuracy
Output Voltage Range: 0.75 V to 5.5 V
Wide Input Voltage Range: 1.8 V to 28 V
Selectable Auto-Skip/PWM-Only Operation
Temperature Compensated (4500 ppm/°C)
Low-Side RDS(on) Overcurrent Sensing
Negative Overcurrent Limit
Integrated Boost Diode
Integrated OVP/UVP and Thermal Shutdown
Power-Good Signal
Internal 1.2-ms Voltage Softstart
Output Discharge (Softstop)
The TPS51117 is a cost effective, synchronous buck
controller for POL voltage regulation in notebook PC
applications. The controller is dedicated for Adaptive
On-Time D-CAP™ Mode operation that provides
ease of use, low external component count, and
excellent fast transient response at the same time.
Auto-skip mode for high efficiency down to the
milli-ampere load range, or PWM-only mode for low
noise operation is selectable.
The current sensing scheme for positive overcurrent
and negative overcurrent protection is loss-less
low-side
RDS(on)
sensing
plus
temperature
compensation. The device receives 5-V (4.5 V to 5.5
V) supply from another regulator such as the
TPS51120 or TPS51020 in the NBPC system. The
conversion input can be either VBAT or 5-V rail,
ranging from 1.8 V to 28 V, and the output voltage
range is from 0.75 V to 5.5 V.
The TPS51117 is available in the 14-pin TSSOP
package and is specified from –40°C to 85°C.
APPLICATIONS
•
•
•
Notebook Computers
I/O Supplies
System Power Supplies
+5V
+
+
TPS51117PW
VIN
1.8V~28V
C4
EN_PSV
1
EN_PSV
2
TON
3
VOUT
VBST
14
DRVH
13
LL
12
TRIP
11
V5DRV
10
R3
R5
R6
C3
PGOOD
Q1
4
V5FILT
5
VFB
C2
L1
+
R4
R1
C1
Q2
6
PGOOD
DRVL
9
7
GND
PGND
8
VOUT
R2
-
PGND
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
ORDERING INFORMATION (1) (2)
TA
PACKAGE
–40°C to 85°C
PLASTIC
TSSOP (PW)
(1)
(2)
ORDERING PART
NUMBER
TPS51117PW
PINS
14
TPS51117PWR
OUTPUT
SUPPLY
MINIMUM
ORDER
QUANTITY
Tube
90
Tape-and-Reel
2000
ECO PLAN
Green
(RoHS & no Sb/Br)
All packaging options have Cu NIPDAU lead/ball finish.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
Input voltage range
Output voltage range
UNIT
VBST
–0.3 to 36
VBST (with respect to LL)
–0.3 to 6
EN_PSV, TRIP, V5DRV, V5FILT
–0.3 to 6
VOUT
–0.3 to 6
TON
–0.3 to 6
DRVH
–1 to 36
DRVH (with respect to LL)
–0.3 to 6
LL
–1 to 30
PGOOD, DRVL
–0.3 to 6
PGND
V
V
–0.3 to 0.3
TA
Operating free-air temperature
–40 to 85
°C
Tstg
Storage temperature range
–55 to 150
°C
TJ
Junction temperature range
–40 to 125
°C
260
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
Ta <25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
14 pin TSSOP
750 mW
7.5 mW/°C
300 mW
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
Supply input voltage range
Input voltage range
Output voltage range
MAX
4.5
5.5
VBST
4.5
34
VBST (with respect to LL)
4.5
5.5
EN_PSV, TRIP, V5DRV, V5FILT
–0.1
5.5
VOUT
–0.1
5.5
TON
–0.1
5.5
DRVH
–0.8
34
DRVH (with respect to LL)
–0.1
5.5
LL
–0.8
28
PGOOD, DRVL
–0.1
5.5
PGND
–0.1
0.1
–40
85
Operating free-air temperature, TA
2
MIN
UNIT
V
V
V
°C
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IV5FILTPWM
Supply current
V5FILT + V5DRV current, PWM, EN_PSV = float, VFB
= 0.77V, LL = –0.1 V
400
750
µA
IV5FILTSKIP
Supply current
V5FILT + V5DRV current, auto-skip, EN_PSV = 5 V,
VFB = 0.77V, LL = 0.5 V
250
470
µA
IV5DRVSDN
V5DRV shutdown current
V5DRV current, EN_PSV = 0 V
0
1
µA
IV5FILTSDN
V5FILT shutdown current
V5FILT current, EN_PSV = 0 V
4.5
7.5
µA
5.5
V
VOUT AND VFB VOLTAGES
VOUT
Output voltage
VVFB
VFB regulation voltage
Adjustable output range
0.75
750
mV
TA = 25°C, bandgap initial accuracy
–0.9%
0.9%
TA = 0°C to 85°C
–1.3%
1.3%
TA = -40°C to 85°C
–1.6%
VVFB_TOL
VFB regulation voltage
tolerance
IVFB
VFB input current
VFB = 0.75 V, absolute value
0.02
0.1
µA
RDischg
VOUT discharge resistance
EN_PSV = 0 V, VOUT = 0.5 V
20
32
Ω
1.6%
ON-TIME TIMER AND INTERNAL SOFT START
TONN
Nominal on time
VLL = 12 V, VOUT = 2.5 V, RTON = 250 kΩ
TONF
Fast on time
VLL = 12 V, VOUT = 2.5 V, RTON = 100 kΩ
TONS
Slow on time
VLL = 12 V, VOUT = 2.5 V, RTON = 400 kΩ
TON(MIN)
V (1)
Minimum on time
VOUT = 0.75 V, RTON = 100 kΩ to 28
TOFF(MIN)
Minimum off time
VFB = 0.7 V, LL = -0.1 V,
TRIP = open
TSS
Internal soft start time
Time from EN_PSV > 3 V to VFB regulation
value = 0.735 V
750
264
330
ns
396
1169
80
110
ns
140
440
0.82
ns
ns
ns
1.2
1.5
ms
5
7
Ω
1.5
2.5
Ω
5
7
Ω
1.5
2.5
Ω
OUTPUT DRIVERS
RDRVH
RDRVL
TD
DRVH resistance
DRVL resistance
Dead time
Source, VVBST-DRVH = 0.5 V
Sink, VDRVH-LL = 0.5 V
Source, VV5DRV-DRVL = 0.5 V
Sink, VDRVL-PGND = 0.5 V
DRVH-low (DRVH = 1 V) to DRVL-high
(DRVL = 4 V), LL = –0.05 V
10
20
50
ns
DRVL-low (DRVL = 1 V) to DRVH-high
(DRVH = 4V), LL = –0.05 V
30
40
60
ns
0.7
0.8
0.9
0.1
1
INTERNAL BST DIODE
VFBST
Forward voltage
VV5DRV-VBST, IF = 10 mA, TA = 25°C
IVBSTLK
VBST leakage current
VBST = 34 V, LL = 28 V
(1)
V
µA
Design constraint, ensure actual on-time is larger than the max value (i.e., design RTON such that the min tolerance is 100 kΩ).
3
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
ELECTRICAL CHARACTERISTICS (Continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Wake up
3.7
3.9
4.1
V
Hysteresis
200
300
400
mV
EN_PSV low
0.7
1.0
1.3
V
Hysteresis
150
200
250
mV
EN_PSV float (set PWM_only mode)
1.7
1.95
2.25
V
EN_PSV high (set Auto_skip mode)
2.4
2.65
2.9
V
Hysteresis
100
175
250
mV
UVLO/LOGIC THRESHOLD
VUVLO
VEN_PSV
IEN_PSV
V5FILT UVLO Threshold
EN_PSV logic input
voltage
EN_PSV source current
EN_PSV = GND, absolute value (1)
µA
1
POWERGOOD COMPARATOR
VTHPG
PG threshold
PG in from lower (PGOOD goes high)
92.5%
95%
97.5%
PG low hysteresis (PGOOD goes low)
–4%
–5.5%
–7%
PG in from higher (PGOOD goes high)
102%
105%
107%
PG high hysteresis (PGOOD goes low)
4%
5.5%
7%
IPGMAX
PG sink current
PGOOD = 0.5 V
2.5
7.5
mA
TPGDEL
PG delay
Delay for PGOOD in
45
63
85
µs
9
10
11
µA
CURRENT SENSE
ITRIP
TRIP source current
VTRIP < 0.3 V, TA = 25°C
TCITRIP
ITRIP temperature
coefffecient
On the basis of 25°C
VRtrip
Current limit threshold
range setting range
VTRIP-GND voltage (1), all temperatures
VOCLoff
Overcurrent limit
comparator offset
(VTRIP-GND-VPGND-LL) voltage VTRIP-GND = 60 mV
–10
VUCLoff
Negative overcurrent limit
comparator offset
(VTRIP-GND-VLL-PGND) voltage VTRIP-GND = 60 mV,
EN_PSV = float
VZCoff
Zero crossing comparator
offset
VPGND-LL voltage, EN_PSV = 3.3 V
4500
30
ppm/°C
200
mV
0
10
mV
–9.5
0.5
10.5
mV
–9.5
0.5
10.5
mV
111%
115%
119%
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
VFB OVP trip threshold
TOVPDEL
VFB OVP propagation
delay
VUVP
VFB UVP trip threshold
TUVPDEL
VFB UVP delay
TUVPEN
UVP enable delay
OVP detect
See
(1)
UVP detect
65%
Hysteresis
After 1.7 × TSS, UVP protection engaged
µs
1.5
70%
75%
10%
22
32
42
µs
1.4
2
2.6
ms
THERMAL SHUTDOWN
TSDN
(1)
4
Thermal shutdown
threshold
Ensured by design. Not production tested.
Shutdown temperature (1)
Hysteresis (1)
160
°C
12
°C
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
DRVH
13
O
High-side NFET gate driver output. Source 5 Ω, sink 1.5 Ω LL-node referenced driver. Drive voltage
corresponds to VBST to LL voltage.
DRVL
9
O
Rectifying (low-side) NFET gate driver output. Source 5 Ω, sink 1.5 Ω PGND referenced driver. Drive voltage
is V5DRV voltage.
EN_PSV
1
I
Enable/power save pin. Connect to ground to disable SMPS. Connect to 3.3 V or 5 V to turn on SMPS and
activate skip mode. Float to turn on SMPS but disable skip mode (forced continuous conduction mode).
GND
7
I
Signal ground pin.
LL
12
I/O
High-side NFET gate driver return. Also serves as anode of overcurrent comparator.
PGND
8
I/O
Ground return for rectifying NFET gate driver. Also cathode of overcurrent protection and source node of the
output discharge switch.
PGOOD
6
O
Power-good window comparator, open-drain, output. Pull up to 5-V rail with a pull-up resistor. Current
capability is 7.5 mA.
TON
2
I
On-time / frequency adjustment pin. Connect to LL with 100-kΩ to 600-kΩ resistor.
TRIP
11
I
Overcurrent trip point set input. Connect resistor from this pin to signal ground to set threshold for both
overcurrent and negative overcurrent limit.
VBST
14
I
Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to LL-node. An
internal PN diode is connected between V5DRV to this pin. Designer can add external schottky diode if
forward drop is critical to drive the power NFET.
VFB
5
I
SMPS voltage feedback input. Connect the resistor divider here for adjustable output.
VOUT
3
I
Connect to SMPS output. This terminal serves two functions: output voltage monitor for on-time adjustment,
and input for the output discharge switch.
V5DRV
10
I
5-V Power supply input for FET gate drivers. Internally connected to VBST by a PN diode. Connect 1 µF or
more between this pin and PGND to support instantaneous current for gate drivers.
V5FILT
4
I
5-V Power supply input for all the control circuitry except gate drivers. Supply 5-V ramp rate should be 17
mV/us or less and TJ < 85°C to secure safe start-up of the internal reference circuit. Apply RC filter consists of
300 Ω + 1 µF or 100 Ω + 4.7 µF at the pin input.
TSSOP (PW) PACKAGE
(TOP VIEW)
EN_PSV
1
14
VBST
TON
2
13
DRVH
VOUT
3
12
LL
V5FILT
4
11
TRIP
VFB
5
10
V5DRV
PGOOD
6
9
DRVL
GND
7
8
PGND
5
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
FUNCTIONAL BLOCK DIAGRAM
2.9
3.9 /3.6
48
6
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
DETAILED DESCRIPTION
PWM OPERATION
The main control loop of the TPS51117 is designed as an adaptive on-time pulse width modulation (PWM)
controller. It supports proprietary D-CAP™ Mode that uses an internal compensation circuit and is suitable for
minimal external component count configuration when an appropriate amount of ESR at the output capacitor(s) is
allowed. Basic operation of D-CAP Mode can be described as follows.
At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or becomes ON state. This
MOSFET is turned off, or becomes OFF state, after the internal one shot timer expires. This one shot is
determined by VIN and VOUT to keep the frequency fairly constant over the input voltage range at steady state,
hence it is called adaptive on-time control or fixed frequency emulated on-time control (see PWM frequency and
Adaptive On-Time Control). The MOSFET is turned on again when both feedback information, monitored at VFB
voltage, indicates insufficient output voltage AND inductor current information indicates below the overcurrent
limit. Repeating the operation in this manner, the controller regulates the output voltage. The synchronous
low-side or rectifying MOSFET is turned on each OFF state to keep the conduction loss to a minimum.
The TPS51117 supports selectable PWM-only and auto-skip operation modes. If EN_PSV is grounded, the
switching regulator is disabled. If the EN_PSV pin is connected to 3.3 V or 5 V, the regulator is enabled with
auto-skip mode selected. The rectifying MOSFET is turned off when inductor current information detects zero
level. This enables a seamless transition to reduced frequency operation during a light load condition so that high
efficiency is maintained over a broad range of load currents. If the EN_PSV pin is floated, it is internally pulled up
to 1.95 V, and the regulator is enabled with PWM-only mode selected. The rectifying MOSFET is not turned off
when inductor current reaches zero. The converter runs forced continuous conduction mode for the entire load
range. System designers may want to use this mode to avoid a certain frequency during a light load condition but
with the cost of low efficiency. However, be aware the output has the capability to both source and sink current in
this mode. If the output terminal is connected to a voltage source higher than the regulator’s target, the converter
sinks current from the output and boosts the charge into the input capacitor. This may cause unexpected high
voltage at VIN and may damage the power FETs.
DC output voltage can be set by the external resistor divider as follows (refer to Figure 22 and Figure 23).
V
OUT
R
1 1
R2
0.75 V
(1)
LIGHT LOAD CONDITION WITH AUTO-SKIP FUNCTION
If auto-skip mode is selected, the TPS51117 automatically reduces the switching frequency during a light load
condition to maintain high efficiency. This reduction of frequency is achieved smoothly and without an increase of
Vout ripple or load regulation. Detailed operation is described as follows. As the output current decreases from a
heavy load condition, the inductor current is also reduced and eventually comes to the point that its valley
touches zero current, which is the boundary between continuous conduction and discontinuous conduction
modes. The rectifying MOSFET is turned off when this zero inductor current is detected. Since the output voltage
is still higher than the reference at this moment, both high-side and low-side MOSFETs are turned off and wait
for the next cycle. As the load current decreases further, the converter runs in discontinuous conduction mode,
taking longer time to discharge the output capacitor below the reference voltage. Note the ON time is kept the
same as during the heavy load condition. In reverse, when the output current increases from a light load to a
heavy load, the switching frequency increases to the preset value as the inductor current reaches to the
continuous conduction. The transition load point to light load operation, IOUT(LL) (i.e., the threshold between
continuous and discontinuous conduction mode), can be calculated as follows:
I
OUT(LL)
1
2 L ƒsw
VIN VOUT VOUT
V
IN
(2)
where fsw is the PWM switching frequency.
Switching frequency versus output current in the light load condition is a function of L, fsw, VIN and VOUT, but it
decreases almost proportional to the output current from the IOUT(LL) given above. For example, it is about 60 kHz
at IOUT(LL)/5 if the PWM switching frequency is 300 kHz.
7
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
DETAILED DESCRIPTION (continued)
PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL
The TPS51117 employs an adaptive on-time control scheme and does not have a dedicated oscillator on board.
However, the device emulates a constant frequency by feed-forwarding the input and output voltages into the
on-time one-shot timer. The ON time is controlled inverse proportional to the input voltage, and proportional to
the output voltage, so that the duty ratio is kept as VOUT/VIN technically with the same cycle time. Equation
Equation 3 shows a simplified calculation of the on time.
(23)V
T
ON
19 10 12 R
TON
100 mV
OUT
V
IN
50 ns
(3)
Here, RTON is the external resistor connected from TON pin to the LL node. In the equation, 19 pF represents the
internal timing capacitor with some typical parasitic capacitance at the TON pin. Also, 50 nsec is the turn-off
delay time contributed by the internal circuit and that of the high-side MOSFET. Although this equation provides a
good approximation to start with, the accuracy depends on each design and selection of the high-side MOSFET.
Figure 1 shows the relationship of RTON to the switching frequency.
700
VIN = 15 V,
VOUT = 2.5 V,
PWM
600
f - Frequency - kHz
500
400
300
200
100
0
100
200
300
400
RTON - kW
500
600
Figure 1. Switching Frequency vs RTON
The TPS51117 does not have a pin connected to VIN, but the input voltage information comes from the switch
node (LL node) during the ON state. An advantage of LL monitoring is that the loss in the high-side NFET is now
a part of the on-time calculation, thereby making the frequency more stable with load.
Another consideration about frequency is jitter. Jitter may be caused by many reasons, but the constant on-time
D-CAP mode scheme has some amount of inherent jitter. Since the output voltage ripple height is in the range of
a couple of tens of milli-volts. A milli-volt order of noise on the feedback signal can affect the frequency by a few
to ten percent. This is normal operation and has little harm to the power supply performance.
LOW-SIDE DRIVER
The low-side driver is designed to drive high-current, low RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which is 5 Ω for V5DRV to DRVL and 1.5 Ω for DRVL to PGND. A dead
time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on,
and low-side MOSFET off to high-side MOSFET on. A 5-V bias voltage is delivered from V5DRV supply. The
average drive current is calculated by the FET gate charge at Vgs = 5 V times the switching frequency. The
instantaneous drive current is supplied by an input capacitor connected between V5DRV and GND.
8
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
DETAILED DESCRIPTION (continued)
HIGH-SIDE DRIVER
The high-side driver is designed to drive high-current, low RDS(on) N-channel MOSFET(s). When configured as a
floating driver, 5-V bias voltage is delivered from V5DRV supply. An internal PN diode is connected between
V5DRV to this pin. The designer can add an external schottky diode if forward drop is critical to drive the
high-side NFET or to achieve the last one percent efficiency improvement. The average drive current is also
estimated by the gate charge at Vgs = 5 V times the switching frequency. The instantaneous drive current is
supplied by the flying capacitor between the VBST pin and LL pin. The drive capability is represented by its
internal resistance, which is 5 Ω for VBST to DRVH and 1.5 Ω for DRVH to LL.
SOFTSTART
The TPS51117 has an internal, 1.2-ms, voltage servo softstart with overcurrent limit. When the EN_PSV pin
becomes high, an internal DAC begins ramping up the reference voltage to the error amplifier. Smooth control of
the output voltage is maintained during start up.
POWERGOOD
The TPS51117 has power-good output. PGOOD is an open drain 7.5-mA pull-down output. This pin should be
typically connected to a 5-V power supply node through a 100-kΩ resistor. The power-good function is activated
after the soft start has finished. If the output voltage becomes within ±5% of the target value, internal
comparators detect the power-good state and the power-good signal becomes high after a 64-µs internal delay. If
the output voltage goes outside ±10% of the target value, the power-good signal becomes low immediately.
OUTPUT DISCHARGE CONTROL (SOFTSTOP)
The TPS51117 discharges output when EN_PSV is low or the converter is in a fault condition (UVP, OVP,
UVLO, or thermal shutdown). The TPS51117 discharges output using an internal 20-Ω MOSFET which is
connected to VOUT and PGND. The discharge time-constant is a function of the output capacitance and
resistance of the discharge transistor.
OVERCURRENT LIMIT
The TPS51117 has cycle-by-cycle overcurrent limiting control. Inductor current is monitored during the OFF state
and the controller keeps the OFF state when inductor current is larger than the overcurrent trip level. In order to
provide both good accuracy and a cost effective solution, the TPS51117 supports temperature compensated
MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor,
RTRIP. The TRIP terminal sources 10-µA ITRIP current, and the trip level is set to the OCL trip voltage, VTRIP as in
the following equation.
V
(mV) R
(k) 10 (A)
TRIP
TRIP
(4)
Inductor current is monitored by the voltage between the PGND pin and the LL pin so the LL pin should be
connected to the drain terminal of the low-side MOSFET. ITRIP has 4500 ppm/°C temperature coefficient to
compensate the temperature dependency of the RDS(on). PGND is used as the positive current sensing node so
PGND should be connected to the source terminal of the bottom MOSFET.
As the comparison is done during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load
current at overcurrent threshold, Iocp, can be calculated as follows;
Iocp V
VIN VOUT V OUT
V
1
R
I
2 TRIP TRIP DS(on)
ripple
R
2Lƒ
V
DS(on)
IN
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall. Eventually it crosses the undervoltage protection threshold and shutdown.
9
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
DETAILED DESCRIPTION (continued)
NEGATIVE OVERCURRENT LIMIT (PWM-ONLY MODE)
The TPS51117 also supports cycle-by-cycle negative overcurrent limiting in PWM-only mode. The overcurrent
limit is set to be negative but is the same absolute value as the positive overcurrent limit. If output voltage
continues to rise, the bottom MOSFET stays on, thus inductor current is reduced and reverses direction after it
reaches zero. When there is too much negative current in the inductor, the bottom MOSFET is turned off and the
current flows to VIN through the body diode of the top MOSFET. Because this protection reduces current to
discharge the output capacitor, output voltage tends to rise, eventually hitting the overvoltage protection
threshold and shutdown. In order to prevent false OVP from triggering, the bottom MOSFET is turned on again
400 ns after it is turned off. If the device hits the negative overcurrent threshold again before output voltage is
discharged to the target level, the bottom MOSFET is turned off and the process repeats, which is called NOCL
Buzz. It ensures maximum allowable discharge capability when output voltage continues to rise. On the other
hand, if the output voltage is discharged to the target level before the NOCL threshold is reached, the bottom
MOSFET is turned off, the top MOSFET is then turned on, and the device resumes normal operation.
OVERVOLTAGE PROTECTION
The TPS51117 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage condition.
When the feedback voltage becomes higher than 115% of the target value, the top MOSFET is turned off and
the bottom MOSFET is turned on immediately. The output is also discharged by the internal 20-Ω transistor.
Also, the TPS51117 monitors VOUT terminal voltage directly and if it becomes greater than 5.75 V, it turns off
the top MOSFET driver.
UNDERVOLTAGE PROTECTION
When the feedback voltage becomes lower than 70% of the target value, the UVP comparator output goes high
and an internal UVP delay counter begins counting. After 32 µs, the TPS51117 latches off the high-side and
low-side MOSFETs and discharges the output with the internal 20-Ω transistor. This function is enabled after 2
ms from when EN_PSV is brought high, i.e., UVP is disabled during start up.
UVLO PROTECTION
The TPS51117 has V5FILT undervoltage lockout protection (UVLO). When the V5FILT voltage is lower than the
UVLO threshold voltage, the TPS51117 is shut off. This is a nonlatched protection.
THERMAL SHUTDOWN
The TPS51117 monitors the temperature of itself. If the temperature exceeds the threshold value (typically
160°C), the TPS51117 shuts itself off. Both top and bottom gate drivers are tied low with output discharged
through the VOUT terminal. This is also a nonlatched protection. The device recovers once the temperature has
decreased approximately 12°C.
10
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
TYPICAL CHARACTERISTICS
V5FILT SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
800
8
700
7
IV5FILT_SHDN - Shutdown Current - mA
IV5FILTPWM - Supply Current - mA
PWM SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
600
500
400
300
200
100
0
-50
0
50
100
TJ - Junction Temperature - ºC
4
3
2
1
0
50
100
TJ - Junction Temperature - ºC
Figure 2.
Figure 3.
TRIP CURRENT
vs
JUNCTION TEMPERATURE
OVP/UVP THRESHOLD
vs
JUNCTION TEMPERATURE
150
130
VOVP, VUVP - OVP/UVP Threshold - %
ITRIP - TRIP Source Current - mA
5
0
-50
150
16
14
12
10
8
6
4
-50
6
0
50
100
TJ - Junction Temperature - º C
Figure 4.
150
OVP
120
110
100
90
80
UVP
70
60
50
-50
0
50
100
TJ - Junction Temperature - ºC
150
Figure 5.
11
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
TYPICAL CHARACTERISTICS (continued)
MEASURED SWITCHING FREQUENCY
vs
TON RESISTANCE
SWITCHING FREQUENCY
vs
INPUT VOLTAGE
800
500
VI = 15 V,
PWM Mode
600
500
400
300
VO = 2.5 V
200
100
VO = 1.05 V
400
350
300
VO = 2.5 V
250
200
150
100
50
VO = 1.05 V
0
100
VI = 15 V,
PWM Mode
450
fsw - Switching Frequency - kHz
fsw - Switching Frequency - kHz
700
0
200
300
400
500
600
5
700
SWITCHING FREQUENCY
vs
OUTPUT CURRENT (1.05 V)
SWITCHING FREQUENCY
vs
OUTPUT CURRENT (2.5 V)
450
400
400
PWM Only
300
250
200
150
100
50
0
0.001
0.010
0.100
1.000
Figure 8.
10.000
21
25
350
PWM Only
300
250
200
150
100
50
Auto Skip
IO - Output Current - A
12
13
17
VI - Input Voltage - V
Figure 7.
450
350
9
Figure 6.
fsw - Switching Frequency - kHz
fsw - Switching Frequency - kHz
RTON - TON Resistance - kW
0
0.001
Auto Skip
0.010
0.1
1
IO - Output Current - A
Figure 9.
10
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
TYPICAL CHARACTERISTICS (continued)
2.5 V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.07
2.54
1.06
2.52
VO - Output Voltage - V
VO - Output Voltage - V
1.05 V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
PWM Only
1.05
Skip Mode
1.04
1.03
2.50
Auto Skip
2.48
2.46
0
2
4
6
IO - Output Current - A
8
10
0
4
6
IO - Output Current - A
Figure 11.
1.05 V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
2.5 V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
1.07
2.54
1.06
2.52
IO = 10 A
1.05
2
Figure 10.
VO - Output Voltage - V
VO - Output Voltage - V
PWM Only
IO = 0 A
10
IO = 10 A
2.50
IO = 0 A
2.48
1.04
8
Auto Skip
Auto Skip
1.03
2.46
5
9
13
17
VI - Input Voltage - V
Figure 12.
21
25
5
9
13
17
VI - Input Voltage - V
21
25
Figure 13.
13
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
TYPICAL CHARACTERISTICS (continued)
1.05 V EFFICIENCY
vs
OUTPUT CURRENT
2.5 V EFFICIENCY
vs
OUTPUT CURRENT
100
100
90
Auto Skip
90
70
60
50
VI = 8 V
VI = 12 V
VI = 8 V
VI = 12 V
VI = 20 V
40
30
20
70
60
VI = 12 V
VI = 8 V
VI = 20 V
VI = 12 V
50
40
VI = 20 V
30
VI = 20 V
20
PWM Only
fsw = 350 kHz
10
0
0.001
VI = 8 V
80
h - Efficiency - %
h - Efficiency - %
80
0.01
0.1
1
IO - Output Current - A
PWM Only
fsw = 300 kHz
10
10
0
0.001
0.01
0.1
1
IO - Output Current - A
Figure 14.
Figure 15.
1.05 V LOAD TRANSIENT RESPONSE
2.5 V LOAD TRANSIENT RESPONSE
VO (50 mV/div)
VO (50 mV/div)
IIND (5 A/div)
IO (5 A/div)
t - Time - 10 ms/div
Figure 16.
14
IIND (5 A/div)
IO (5 A/div)
t - Time - 10 ms/div
Figure 17.
10
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
TYPICAL CHARACTERISTICS (continued)
MODE TRANSITION
AUTO-SKIP TO PWM
MODE TRANSITION
PWM TO AUTO-SKIP
VO (20 mV/div)
VO (20 mV/div)
LL (10 V/div)
LL (10 V/div)
DRVL (5 V/div)
DRVL (5 V/div)
EN_PSV (5 V/div)
EN_PSV (5 V/div)
Figure 18.
Figure 19.
2.5 V START-UP WAVEFORMS
2.5 SHUTDOWN WAVEFORMS
EN_PSV (2 V/div)
EN_PSV (2 V/div)
VO (1 V/div)
VO (1 V/div)
PGOOD (5 V/div)
PDOOD (5 V/div)
DRVL (5 V/div)
t - Time - 1 ms/div
Figure 20.
t - Time - 10 ms/div
Figure 21.
15
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
APPLICATION INFORMATION
LOOP COMPENSATION AND EXTERNAL PARTS SELECTION
D-CAP™ Mode Operation
A buck converter system using D-CAP™ Mode can be simplified as shown in Figure 22.
VIN
R1
DRVH
PWM
-
VFB
+
+
R2
Control
Logic
and
Driver
DRVL
Lx
Ic
IL
0.75V
ESR
RL
Vc
Voltage Divider
Io
Switching Modulator
Co
Output Capacitor
Figure 22. Simplified Diagram of the Modulator
The VFB voltage is compared with the internal reference voltage after the divider resistors. The PWM comparator
determines the timing to turn on the top MOSFET. The gain and speed of the comparator is high enough to keep
the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output
voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage increases.
For loop stability, the 0 dB frequency, f0, defined in the follow equation must be lower than 1/4 of the switching
frequency.
ƒ
1
ƒo sw
4
2 ESR Co
(6)
As f0 is determined solely by the output capacitor characteristics, loop stability of D-CAP™ Mode is determined
by capacitor chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of several 100
µF and ESR in range of 10 mΩ. These values make f0 in the order of 100 kHz or less and the loop is stable.
However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational mode.
Although D-CAP™ Mode provides many advantages such as ease-of-use, minimum external component
configuration, and extremely short response time, due to not employing an error amplifier in the loop, a sufficient
feedback signal needs to be provided by an external circuit to reduce the jitter level. The required signal level is
approximately 15 mV at the comparing point. This generates Vripple = (VOUT/0.75) × 15 mV at the output node.
The output capacitor ESR should meet this requirement.
The external component selection is simple in D-CAP™ Mode:
1. Determine the value of R1 and R2
The recommended R2 value is 10 kΩ to 100 kΩ. Calculate R1 by Equation 7.
R1 VOUT 0.75
2. Choose RTON
16
0.75
R2
(7)
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
APPLICATION INFORMATION (continued)
Switching frequency is usually determined by the overall view of the DC-DC converter design of: size,
efficiency or cost, and mostly dictated by external component constraints such as the size of inductor and/or
output capacitor. In the case where an extremely low or high duty factor is expected, the minimum on-time or
off-time also needs to be considered to satisfy the required duty factor. Once the switching frequency is
decided, RTON can be determined by Equation 8 and Equation 9,
V
OUT
T
1
ON(max)
ƒ V
IN(min)
(8)
R
3
TON
2
T ON(max) 50 ns
19 10 12
V
IN(min)
VOUT 150 mV
[]
(9)
3. Choose inductor
A good starting point inductance value is where the ripple current is approximately 1/4 to 1/2 of the maximum
output current.
L
IND
1
I
IND(ripple)
ƒ
VIN(max) VOUT VOUT
V
IN(max)
3
I
OUT(max)
ƒ
VIN(max) VOUT VOUT
V
IN(max)
(10)
For applications that require fast transient response with minimum VOUT overshoot, consider a smaller
inductance than above. The cost of a small inductance value is higher steady state ripple, larger line
regulation, and higher switching loss.
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated as follows.
V
I
TRIP 1 IND(peak)
R
Lƒ
DS(on)
VIN(max) VOUT VOUT
V
IN(max)
(11)
4. Choose output capacitor(s)
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to
meet the required ripple voltage above. A quick approximation is shown in Equation 12.
V
0.015
V
OUT 60 [m]
ESR OUT
I
0.75
I
ripple
OUT(max)
(12)
5. Choose MOSFETs
Loss-less current sensing and overcurrent protection of the TPS51117 is determined by RDS(on) of the
low-side MOSFET. So, RDS(on) times the inductor current value at the overcurrent point should be in the
range of 30 mV to 200 mV for the entire operational temperature range. Assuming a 20% guard band, RDS(on)
in the following equation should satisfy the full temperature range.
30 mV
200 mV
R
DS(on)
1.2 I
0.5 I
1.2 I
0.5 I
OUT(max)
ripple
OUT(max)
ripple
(13)
6. Choose Rtrip
Once the low-side FET is decided, select an appropriate Rtrip value that provides Vtrip equal to RDS(on) times
Ipeak.
7. LPF for V5FILT
In order to reject high frequency noise and also secure safe start-up of the internal reference circuit, apply
1 µF of MLCC closely at the V5FILT pin with a 300-Ω resistor to create a LPF between +5-V supply and the
pin.
8. VBST capacitor, VBST diode
17
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
APPLICATION INFORMATION (continued)
Apply 0.1-µF MLCC between VBST and the LL node as the flying capacitor for the high-side FET driver. The
TPS51117 has its own boost diode on-board between V5DRV and VBST. This is a PN junction diode and
strong enough for most typical applications. However, in case efficiency has priority over cost, the designer
may add a Schottky diode externally to improve gate drive voltage of the high-side FET. A Schottky diode
has a higher leakage current, especially at high temperature, than a PN junction diode. A low leakage diode
should be selected in order to maintain VBST voltage during low frequency operation in skip mode.
THERMAL CONSIDERATION
Power dissipation of the TPS51117 is mainly generated from the FET drivers. Average drive current can be
estimated by gate charge, Qg, times the switching frequency.
I Q g ƒsw
G
(14)
Qg is the charge needed to charge gate capacitance up to the V5DRV voltage of 5 V. Actual values are shown
on MOSFET datasheets provided by the manufacturer. Total power dissipation, therefore, to drive the top and
bottom MOSFETs can be calculated by the following equation Equation 15.
W
DRIVE
V
V5DRV
Q
g(top)
Q
g(btm)
ƒsw
(15)
This power plus a small amount of dissipation (less than 5 mW) from controller circuitry needs to be effectively
dissipated from the package. Maximum power dissipation allowed for the package is calculated by:
T
T
J(max)
A(max)
W
PKG
JA
(16)
Where
• TJ(max) is 125°C
• TA(max) is the maximum ambient temperature in the system
• θJA is the thermal resistance from the silicon junction to the ambient
This thermal resistance strongly depends on board layout. The TPS51117 is assembled in a standard TSSOP
package and the heat mainly moves to the board through its leads.
LAYOUT CONSIDERATIONS
Certain points must be considered before starting a layout work using the TPS51117.
• Connect the RC low-pass filter from 5-V supply to V5FILT, 300 kΩ and 1 µF are recommended. Place the
filter capacitor close to the IC, within 12 mm (0.5 inches) if possible.
• Connect the overcurrent setting resistors from TRIP to GND close to the IC, right next to the IC, if possible.
The trace from TRIP to resistor and resistor to GND should avoid coupling to a high voltage switching node.
• The discharge path (VOUT) should have a dedicated trace to the output capacitor(s); separate from the
output voltage sensing trace, and use a 1,5 mm (60 mils) or wider trace with no loops. Make sure the
feedback current setting resistor (the resistor between VFB to GND) is tied close to the IC GND. The trace
from this resistor to the VFB pin should be short and thin. Place on the component side and avoid vias
between this resistor and the IC.
• Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use a 0.65 mm (25 mils) or wider trace.
• All sensitive analog traces and components such as VOUT, VFB, GND, EN_PSV, PGOOD, TRIP, V5FILT,
and TON should be placed away from high-voltage switching nodes such as LL, DRVL, DRVH or VBST to
avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and
components.
• Gather the ground terminals of the VIN capacitor(s), VOUT capacitor(s), and the source of the low-side
MOSFETs as close as possible. GND (signal ground) and PGND (power ground) should be connected
strongly together near the IC. The PCB trace defined as LL node, which connects to the source of the
high-side MOSFET, the drain of the low-side MOSFET, and the high-voltage side of the inductor, should be
as short and wide as possible.
18
TPS51117
www.ti.com
SLVS631 – DECEMBER 2005
APPLICATION INFORMATION (continued)
+5V
+
TPS51117PW
EN_PSV
+ +VBAT
C4
0.1 mF
1
EN_PSV
VBST
14
2
TON
DRVH
13
3
VOUT
LL
12
4
V5FILT
TRIP
11
5
VFB
V5DRV
10
6
PGOOD
DRVL
9
7
GND
PGND
8
Q1
R3
C2
20 m F
249k W
R5
R6
100kW
300 W
C3
1u F
PGOOD
L1
1.0uH
+
R4
R1
8.5k W
GND
Q2
C1A
VO
1.05V/10A
C1B
R2
22k W
-
PGND
GND
Figure 23. 1.05-V/10-A Application From VBAT
Table 1. Typical Application Circuit Components
SYMBOL
SPECIFICATION
MANUFACTURER
PART NUMBER
C1A, C1B
470 µF, 2.5 V, 12 mΩ
SANYO
2R5TPE470MC
C2
10 µF, 25 V, 2 pcs
Murata
GRM31CR61E106KA12B
L1
1.0 µH
Vishay, Toko
IHLP-5050, FDA1254-1R0M
Q1
30V, 13 mΩ
International Rectifier
IRF7821
Q2
30 V, 5.8 mΩ
International Rectifier
IRF8113
R4
8.06 kΩ
—
Std
19
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS51117PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS51117PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS51117PWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS51117PWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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