INTERSIL EL2171CN

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1-888
EL2071, EL2171
FN7032
150MHz Current Feedback Amplifier
Features
The EL2071 and EL2171 are wide
bandwidth, fast settling monolithic
amplifiers built using an advanced
complementary bipolar process. The EL2071 has a
disable/enable feature which allows power down and analog
multiplexing. These amplifiers use current-mode feedback to
achieve more bandwidth at a given gain than conventional
operational amplifiers. Designed for closed-loop gains of ±7
to ±50, the EL2071 and EL2171 have a 150MHz - 3dB
bandwidth (AV = +20), and 2.5ns rise/fall time, while
consuming only 15mA of supply current. The EL2071
consumes only 1.5mA when disabled.
• 150MHz - 3dB bandwidth, AV = 20
The wide 150MHz bandwidth and extremely linear phase
(0.2dB deviation from linear at 50MHz) allow superior signal
fidelity. These features make the EL2071 and EL2171
especially suited for many digital communication system
applications.
The EL2071's and EL2171's settling to 0.1% in 10ns and
ability to drive capacitive loads make them ideal in flash A/D
applications. D/A systems can also benefit from the EL2071
and EL2171, especially if linearity and drive levels are
important.
Elantec products and facilities comply with MIL-I-45208A,
and other applicable quality specifications. For information
on Elantec's processing, see Elantec document, QRA-1:
Elantec's Processing, Monolithic Integrated Circuits.
• 10ns settling to 0.1%
• VS = ±5V @ 15mA
• 2.5ns rise/fall times (2V step)
• Overload/short-circuit protected
• ±7 to ±50 closed-loop gain range
• Low cost
• EL2171 is direct replacement for CLC401
• Disable capability on EL2071
Applications
• Line drivers
• DC-coupled log amplifiers
• High-speed modems, radios
• High-speed A/D conversion
• D/A I-V conversion
• Photodiode, CCD preamps
• IF processors
• High-speed communications
• Analog multiplexing (using disable—EL2071)
• Power down mode (using disable—EL2071)
Pinout
Ordering Information
EL2071
(8-PIN PDIP, SO)
TOP VIEW
EL2171
(8-PIN PDIP, SO)
TOP VIEW
PART
NUMBER
TEMP.
RANGE
PACKAGE
PKG. NO.
EL2171CN
-40°C to +85°C
8-Pin PDIP
MDP0031
EL2171CS
-40°C to +85°C
8-Pin SO
MDP0027
EL2071CN
-40°C to +85°C
8-Pin PDIP
MDP0031
EL2071CS
-40°C to +85°C
8-Pin SO
MDP0027
Manufactured under U.S. Patent No. 4,893,091
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL2071, EL2171
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7V
(Output Current Output is short-circuit protected to ground, however,maximum
reliability is obtained if IOUT does not exceed 70mA.)
Common Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature
Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-60°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Open-Loop DC Electrical Specifications
PARAMETER
VOS
DESCRIPTION
VS = ±5V, RL = 100Ω, unless otherwise specified
TEST CONDITIONS
Input Offset Voltage
TEMP
MIN
25°C
TYP
MAX
UNITS
3
6
mV
10
mV
TMIN, TMAX
TC VOS
Average Offset
Voltage Drift
+IIN
+Input Current
(Note 1)
All
20
50
µV/°C
25°C, TMAX
10
20
µA
36
µA
TMIN
TC (+IIN)
Average +Input
Current Drift
-IIN
-Input Current
(Note 1)
All
100
200
nA/°C
25°C
10
30
µA
TMIN
46
µA
TMAX
40
µA
200
nA/°C
TC (-IIN)
Average -Input
Current Drift
(Note 1)
All
PSRR
Power Supply
Rejection Ratio
(Note 2)
All
50
55
dB
CMRR
Common-Mode
Rejection Ratio
All
40
50
dB
IS
Supply Current—Quiescent
No Load
All
15
21
mA
ISOFF
Supply Current—Disabled
EL2071 (Note 3)
All
1.5
3.0
mA
+RIN
+Input Resistance
100
25°C, TMAX
100
TMIN
50
200
kΩ
kΩ
CIN
Input Capacitance
All
0.5
2.5
pF
ROUT
Output Resistance (DC)
All
0.2
0.3
Ω
ROUTD
Output Resistance (DC)
EL2071
Disabled
All
COUTD
Output Capacitance (DC)
EL2071
Disabled
All
CMIR
Common-Mode Input
Range
(Note 4)
25°C, TMAX
±2.5
TMIN
±2
25°C, TMAX
50
TMIN
35
25°C, TMAX
3.2
TMIN
3
IOUT
VOUT
Output Current
Output Voltage Swing
2
No Load
100
200
0.5
±2.8
kΩ
2.0
pF
V
V
70
mA
mA
3.5
V
V
EL2071, EL2171
Open-Loop DC Electrical Specifications
PARAMETER
VS = ±5V, RL = 100Ω, unless otherwise specified (Continued)
DESCRIPTION
TEST CONDITIONS
RL = 100Ω
TEMP
MIN
TYP
25°C
3.2
3.4
V
25°C
250
1000
V/mA
VOUTL
Output Voltage Swing
ROL
Transimpedance
ILOGIC
Pin 8 Current @+5V
EL2071
All
VDIS
Minimum Pin 8
V to Disable
EL2071
25°C
4.3
TMIN
4.0
TMAX
4.6
VEN
Maximum Pin 8
V to Enable
EL2071
All
IDIS
Minimum Pin 8
I to Disable
EL2071
All
IEN
Maximum Pin 8
I to Enable
EL2071
All
500
MAX
750
UNITS
µA
V
0.7
750
V
µA
35
µA
NOTES:
1. Measured from TMIN to TMAX.
2. PSRR is measured at VS = ±4.5V and VS = ±5.5V. Both supplies are changed simultaneously.
3. Supply current when disabled is measured at the negative supply.
4. Common-Mode Input Range for Rated Performance.
Closed-Loop AC Electrical Specifications
PARAMETER
DESCRIPTION
VS = ±5V, RF = 1.5kΩ, AV = +20, RL = 100Ω unless otherwise specified
TEST CONDITIONS
TEMP
MIN
TYP
MAX
UNITS
25°C
100
150
TMIN
100
MHZ
TMAX
70
MHz
25°C, TMIN
65
TMAX
55
FREQUENCY RESPONSE
SSBW
LSBW
-3dB Bandwidth
(VOUT < 2.0 VPP)
-3dB Bandwidth
(VOUT < 5.0 VPP)
MHz
100
MHz
MHz
GAIN FLATNESS
GFPL
GFPH
GFR
LPD
Peaking
VOUT < 2.0 VPP
< 25MHz
Peaking
VOUT < 2.0 VPP
> 25MHz
Rolloff
VOUT < 2.0 VPP
< 50MHz
Linear Phase Deviation
VOUT < 2.0 VPP
25°C
0.0
0.1
dB
0.1
dB
0.2
dB
0.2
dB
1.0
dB
TMIN
1.0
dB
TMAX
1.3
dB
1.0
°
1.5
°
3.5
ns
5
ns
7
ns
8
ns
15
ns
TMIN, TMAX
25°C
0.0
TMIN, TMAX
< 50MHz
25°C
25°C, TMIN
0.2
0.2
TMAX
TIME-DOMAIN RESPONSE
tR1, tF1
Rise Time, Fall Time
2.0V Step
25°C, TMIN
2.5
TMAX
tR2, tF2
Rise Time, Fall Time
5.0V Step
25°C, TMIN
5
TMAX
tS
Settling Time to 0.1%
3
2.0V Step
All
10
EL2071, EL2171
Closed-Loop AC Electrical Specifications
PARAMETER
DESCRIPTION
OS
Overshoot
SR
Slew Rate
VS = ±5V, RF = 1.5kΩ, AV = +20, RL = 100Ω unless otherwise specified (Continued)
TEST CONDITIONS
2.0V Step
TEMP
MIN
All
25°C, TMIN
800
TMAX
700
TYP
MAX
UNITS
0
10
%
1200
V/µs
V/µs
DISTORTION
HD2
HD3
2nd Harmonic
Distortion @20MHz
2VPP
3rd Harmonic
Distortion @20MHz
2VPP
25°C
-45
-35
dBc
-35
dBc
-50
dBc
TMIN
-50
dBc
TMAX
-45
dBc
-155
dBm (1Hz)
TMIN
-155
dBm (1Hz)
TMAX
-154
dBm (1Hz)
50
µV
TMIN
50
µV
TMAX
55
µV
TMIN, TMAX
25°C
-60
EQUIVALENT INPUT NOISE
NF
INV
Noise Floor >100kHz
25°C
Integrated Noise
100kHz to 200MHz
-158
25°C
35
DISABLE/ENABLE PERFORMANCE—EL2071C
TOFF
VOUT = 2 VPP
Disable Time to >40dB
TON
Enable Time
ISO
Off Isolation
20MHz
20MHz
4
All
70
200
ns
All
40
100
ns
All
50
55
dB
EL2071, EL2171
Typical Performance Curves
Non-Inverting
Frequency Response
Inverting Frequency
Response
Frequency Response for
Various RLs
Open-Loop Transimpedance
Gain and Phase
Frequency Response,
AV = -1, RF = 2.5kΩ
Equivalent Input Noise
Single Power Supply
Rejection Ratio
Common Mode
Rejection Ratio (AV = +20)
5
Recommended RS vs
Load Capacitance
EL2071, EL2171
Typical Performance Curves (Continued)
2nd and 3rd
Harmonic Distortion
Pulse Response AV = +20
Forward and Reverse Gain
during Disable—EL2071
6
2-Tone 3rd Order
Intermodulation Intercept
Pulse Response AV = +20
Disabled Attenuation vs
Time for Various
Output Levels—EL2071
EL2071, EL2171
Typical Performance Curves (Continued)
Disable Response—EL2071
8-Pin SO
Maximum Power Dissipation
vs Ambient Temperature
7
Enable Response—EL2071
8-Pin Plastic DIP
Maximum Power Dissipation
vs Ambient Temperature
EL2071, EL2171
Equivalent Circuit
flowing into the inverting input in the steady-state (nonslewing) condition is very small.
Burn-In Circuit
Therefore we can still use op-amp assumptions as a firstorder approximation for circuit analysis, namely that:
1.The voltage across the inputs is approximately 0V.
2.The current into the inputs is approximately 0mA.
Resistor Value Selection and Optimization
ALL PACKAGES USE THE SAME SCHEMATIC.
Applications Information
Theory of Operation
The EL2071/EL2171 have a unity gain buffer from the noninverting input to the inverting input. The error signal of the
EL2071/EL2171 is a current flowing into (or out of) the
inverting input. A very small change in current flowing
through the inverting input will cause a large change in the
output voltage. This current amplification is called the
transimpedance (ROL) of the EL2071/EL2171
[VOUT = (ROL) * (-IIN)]. Since ROL is very large, the current
8
The value of the feedback resistor (and an internal capacitor)
sets the AC dynamics of the EL2071/EL2171. The nominal
value for the feedback resistor is 1.5kΩ, which is the value
used for production testing. This value guarantees stability.
For a given closed-loop gain the bandwidth may be
increased by decreasing the feedback resistor and,
conversely, the bandwidth may be decreased by increasing
the feedback resistor.
Reducing the feedback resistor too much will result in
overshoot and ringing, and eventually oscillations. Increasing
the feedback resistor results in a lower -3dB frequency.
Attenuation at high frequency is limited by a zero in the
closed-loop transfer function which results from stray
capacitance between the inverting input and ground.
Consequently, it is very important to keep stray capacitance
to a minimum at the inverting input.
EL2071, EL2171
Capacitive Feedback
The EL2071/EL2171 rely on their feedback resistor for
proper compensation. A reduction of the impedance of the
feedback element results in less stability, eventually resulting
in oscillation. Therefore, circuit implementations which have
capacitive feedback should not be used because of the
capacitor's impedance reduction with frequency. Similarly,
oscillations can occur when using the technique of placing a
capacitor in parallel with the feedback resistor to
compensate for shunt capacitances from the inverting input
to ground.
the EL2071 is connected in a gain of +7 configuration and is
disabled while the analog bus is driven externally to +5V.
Pin 2 is consequently at +0.71V, and if VIN is driven to -5V,
then 5.71V appears between pins 3 and 2. Internally, this
voltage appears across a forward biased VBE in series with
a reverse biased VBE and is past the threshold for zenering
the reverse biased VBE. In a typical application, a 50Ω or
75Ω terminating resistor from pin 3 to ground will prevent
pin 3 from approaching -5V.
Printed Circuit Layout
As with any high frequency device, good PCB layout is
necessary for optimum performance. Ground plane
construction is a requirement, as is good power-supply
bypassing close to the package. The inverting input is
sensitive to stray capacitance, therefore connections at the
inverting input should be minimal, close to the package, and
constructed with as little coupling to the ground plane as
possible.
Capacitance at the output node will reduce stability,
eventually resulting in peaking, and finally oscillation if the
capacitance is large enough. The design of the
EL2071/EL2171 allow a larger capacitive load than
comparable products, yet there are occasions when a series
resistor before the capacitance may be needed. Please refer
to the graphs to determine the proper resistor value needed.
Disable/Enable Operation for EL2071
The EL2071 has a disable/enable control input at pin 8. The
device is enabled and operates normally when pin 8 is left
open or returned to ground. When the voltage at pin 8 is
brought to within 0.4V of pin 7 (VS+), the EL2071 is disabled.
The output becomes a high impedance, the inverting input is
no longer driven to the positive input voltage, and the supply
current is reduced to less than 2.2.mA. There are internal
resistors which limit the current at pin 8 to a safe level
(~ ±500µA) if pin 8 is shorted to either supply.
Typically, analog and digital circuits should have separate
power supplies. This usually leads to slight differences
between the power supply voltages. The EL2071's disable
feature is dependent on the voltage at pins 8 and 7.
Therefore, to operate the disable feature of the EL2071
dependably over temperature, it is recommended that the
logic circuitry which drives pin 8 of the EL2071 operate from
the same +5V supply as the EL2071 to avoid voltage
differences between the digital and analog power supplies.
Since VDIS is temperature dependent, it is recommended
that 5V CMOS logic (with a VOH > 4.6V sourcing > 750µA
over temperature) be used to drive the disable pin of the
EL2071.
When disabled, (as well as in enabled mode), care must be
taken to prevent a differential voltage between the + and inputs greater than 5.0V. For example, in the figure below,
9
Using the EL2071 as a Multiplexer
An interesting use of the enable feature is to combine
several amplifiers in parallel with their outputs in common.
This combination then acts similar to a MUX in front of an
amplifier. A typical circuit is shown. The series resistance at
each output helps to further increase isolation between
amplifiers.
When the EL2071 is disabled, the DC output impedance is
> 100kΩ in parallel with 2pF capacitance.
To operate properly, the decoder that is used must have a
VOH > (VS+) - 0.4V with IOH = 750µA, and should be
connected to the same power supply as the EL2071.
EL2071, EL2171
EL2071 Macromodel
* Revision A. March 1992
* Enhancements include PSRR, CMRR, and Slew Rate Limiting
* Connections: +input
*
| -input
*
| | +Vsupply
*
| | | -Vsupply
*
| | | | output
*
| | | | |
.subckt M2071 3 2 7 4 6
*
* Input Stage
*
e1 10 0 3 0 1.0
vis 10 9 0V
h2 9 12 vxx 1.0
r1 2 11 2
l1 11 12 1nH
iinp 3 0 10µA
iinm 2 0 10µA
*
* Slew Rate Limiting
*
*h1 13 0 vis 1K
h1 13 0 vis 600
r2 13 14 100
d1 14 0 dclamp
d2 0 14 dclamp
*
* High Frequency Pole
*
*e2 30 0 14 0 0.00166666666
e2 30 0 14 0 0.001
13 30 17 1.0µH
c5 17 0 0.1pF
r5 17 0 500
*
* Transimpedance Stage
*
g1 0 18 17 0 1.0
rol 18 0 1Meg
cdp 18 0 0.88pF
*
* Output Stage
*
q1 4 18 19 qp
q2 7 18 20 qn
q3 7 19 21 qn
q4 4 20 22 qp
r7 21 6 2
r8 22 6 2
ios1 7 19 2.5mA
ios2 20 4 2.5mA
*
* Supply Current
*
ips 7 4 9mA
*
* Error Terms
*
10
EL2071, EL2171
EL2071 Macromodel
(Continued)
ivos 0 23 3mA
vxx 23 0 0V
e4 24 0 3 0 1.0
e5 25 0 7 0 1.0
e6 26 0 4 0 1.0
r9 24 23 316
r10 25 23 562
r11 26 23 562
*
* Models
*
.model qn npn (is=5e-15 bf=500 tf=0.05nS)
.model qp pnp (is=5e-15 bf=500 tf=0.05nS)
.model dclamp d(is=1e-30 ibv=1pA bv=3.5 n=4)
.ends
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11